CN120091632A

CN120091632A - Electrostatic protection structure and method for forming the same

Info

Publication number: CN120091632A
Application number: CN202311598438.XA
Authority: CN
Inventors: 安钰欣; 石慧; 袁俊
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2023-11-27
Filing date: 2023-11-27
Publication date: 2025-06-03
Anticipated expiration: 2043-11-27
Also published as: CN120091632B

Abstract

The structure comprises a substrate with a deep N-type well region, a first isolation structure, a P-type well region, an N-type drain region, a grid structure, a P-type source region, a P-type drain region, an N-type drain region and an N-type drain region, wherein the first isolation structure is positioned in the deep N-type well region of a PMOS region and an NMOS region and is spaced apart from the deep N-type well region, the P-type well region and the N-type well region are positioned in the same MOS region, the N-type well region and the P-type well region of the adjacent MOS region are arranged opposite to each other, the grid structure is positioned on the P-type well region and is close to one side of the N-type well region of the same MOS region, the P-type source region is positioned in the P-type well region of the PMOS region and is positioned on one side of the N-type well region of the grid structure facing away from the PMOS region, the N-type well region is positioned in the P-type well region of the NMOS region and the N-type drain region is positioned in the N-type well region of the NMOS region. The electrostatic protection structure realizes bidirectional protection, forms a silicon controlled device and improves electrostatic protection performance.

Description

Electrostatic protection structure and forming method thereof

Technical Field

The embodiment of the invention relates to the field of electrostatic protection manufacturing, in particular to an electrostatic protection structure and a forming method thereof.

Background

With integrated circuits susceptible to electrostatic damage, in existing chip designs, electrostatic discharge (Electrostatic Discharge, ESD) protection circuits are often used to reduce chip damage.

However, with the rapid growth of the semiconductor integrated circuit (INTEGRATED CIRCUIT, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in the development of integrated circuits with smaller volumes, higher circuit precision, and higher circuit complexity.

Therefore, the performance of the electrostatic protection structure in the prior art needs to be improved.

Disclosure of Invention

The embodiment of the invention provides an electrostatic protection structure and a forming method thereof, so as to improve the performance of the electrostatic protection structure.

In order to solve the problems, the embodiment of the invention provides an electrostatic protection structure, which comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a PMOS region and an NMOS region which are adjacently arranged, and a deep N-type well region is formed in the substrate of the PMOS region and the NMOS region; the first isolation structures are respectively positioned in the deep N-type well regions of the PMOS region and the NMOS region and are arranged at intervals; the P-type well region is respectively arranged in the PMOS region and the NMOS region and is positioned in the deep N-type well region at the first side of the first isolation structure, the P-type well region is respectively arranged in the PMOS region and the NMOS region and is positioned in the deep N-type well region at the second side of the first isolation structure, the N-type well region of the PMOS region and the P-type well region of the NMOS region are arranged oppositely in the PMOS region and the NMOS region which are adjacently arranged, the grid structure is respectively positioned on the P-type well region of the PMOS region and the NMOS region and is positioned at one side of the P-type well region close to the N-type well region of the same MOS region, the P-type source region is positioned in the P-type well region of the PMOS region and is positioned at one side of the N-type well region of the grid structure which is opposite to the PMOS region, the P-type well region is positioned in the N-type well region of the NMOS region, and the N-type well region is positioned at one side of the N-type well region of the grid structure which is opposite to the N-type well region of the PMOS region.

Optionally, in the PMOS region and the NMOS region that are adjacently disposed, an N-type well region sidewall of the PMOS region is in contact with a P-type well region sidewall of the NMOS region.

Optionally, the gate structure further extends to cover a top of an adjacent first isolation structure.

Optionally, the electrostatic protection structure further comprises a body region, wherein the body region is positioned in the deep N-type well region and surrounds the outermost periphery of the P-type well region and the N-type well region.

Optionally, the electrostatic protection structure further comprises a second isolation structure located in the deep N-type well region between the body region and the adjacent well region.

Optionally, the material of the first isolation structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

Optionally, the electrostatic protection structure further comprises an interconnection structure, wherein the interconnection structure is respectively and electrically connected with the grid structure, the P-type source region, the P-type drain region, the N-type source region and the N-type drain region, and electric signals are respectively applied to the interconnection structure.

Optionally, the interconnection structure electrically connected to the P-type drain region is used for applying a negative potential, the interconnection structure electrically connected to the N-type drain region is used for applying a positive potential, and the interconnection structure electrically connected to the gate structure, the P-type source region and the N-type source region is used for applying a zero potential.

Optionally, an interconnection structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.

Correspondingly, the embodiment of the invention also provides a forming method of the electrostatic protection structure, which comprises the steps of providing a substrate, forming a first isolation structure in the deep N-type well region of the PMOS region and the NMOS region at intervals, forming a P-type well region in the deep N-type well region of the first side of the first isolation structure, forming an N-type well region in the deep N-type well region of the PMOS region and the NMOS region at intervals, forming N-type well regions in the deep N-type well region of the second side of the first isolation structure, forming P-type well regions in the P-type well region of the PMOS region and the NMOS region at intervals, in the P-type well region and the NMOS region which are adjacently arranged, forming gate structures on the P-type well region of the PMOS region and the P-type well region of the NMOS region respectively, forming P-type well regions in the P-type well region of the PMOS region and the NMOS region, forming P-type well regions in the P-type well region and the N-type well region of the NMOS region respectively, forming the P-type well region and the N-type well region between the P-well region and the N well region, forming the P-type well region and the drain region in the P-type well region, the P-type well region and the P-type well region are formed in the P-type well region and the N well region, the P-type well region, the P-well region is formed in the P-type well region and the P-region, the P-type well region and the N well region, the P well region is formed in the P-type well region, the P well region and the N well region is formed.

Optionally, in the step of forming the P-type well region and the N-type well region, in the PMOS region and the NMOS region that are adjacently disposed, an N-type well region sidewall of the PMOS region is in contact with a P-type well region sidewall of the NMOS region.

Optionally, in the step of forming the gate structure, the gate structure further extends to cover a top of the adjacent first isolation structure.

Optionally, in the step of forming the P-type source region and the P-type drain region, a body region is formed in the deep N-type well region, and the body region surrounds the outermost peripheries of the P-type well region and the N-type well region.

Optionally, in the step of forming the first isolation structure, a second isolation structure spaced from the first isolation structure of the same MOS region is formed in a deep N-type well region of the PMOS region and the NMOS region, respectively, in the same MOS region, the second isolation structure is located on a side of the first isolation structure facing away from the other MOS region, in the step of forming the P-type well region and the N-type well region, the P-type well region and the N-type well region of the same MOS region are located on a side of the second isolation structure facing the other MOS region, in the step of forming the P-type drain region, the P-type source region, the N-type drain region, the N-type source region, and the body region, the P-type drain region and the P-type source region are located on a side of the second isolation structure of the PMOS region facing the other MOS region, the body region is located on the other side of the second isolation structure of the NMOS region, and the body region is located on the other side of the second isolation structure of the NMOS region.

Optionally, after forming the gate structure, the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region, the forming method further includes forming an interconnection structure electrically connected to and applying an electrical signal to the gate structure, the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region, respectively.

Optionally, in the step of forming the interconnection structure, the interconnection structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

The electrostatic protection structure provided by the embodiment of the invention comprises a substrate, wherein the substrate comprises a PMOS region and an NMOS region which are adjacently arranged, deep N-type well regions are formed in the substrate of the PMOS region and the NMOS region, P-type well regions which are respectively positioned in the deep N-type well regions of the PMOS region and the NMOS region and are arranged at intervals, N-type well regions which are respectively positioned in the deep N-type well regions at the side parts of the P-type well regions of the PMOS region and the NMOS region, N-type well regions of the PMOS region and the P-type well regions of the NMOS region are oppositely arranged, P-type source regions which are positioned in the P-type well regions of the PMOS region, P-type drain regions which are positioned in the N-type well regions of the PMOS region, N-type source regions which are positioned in the P-type well regions of the NMOS region, and N-type drain regions which are positioned in the P-type well regions of the NMOS region. The PMOS region and the NMOS region have different conduction characteristics, so that the electrostatic protection structure of the embodiment of the invention can realize bidirectional protection, thereby improving the protection capability of the electrostatic protection structure and correspondingly improving the performance of the electrostatic protection structure, and in the PMOS region and the NMOS region which are adjacently arranged, the N-type well region of the PMOS region and the P-type well region of the NMOS region are oppositely arranged, so that the P-type drain region, the N-type well region of the PMOS region, the deep N-type well region, the P-type well region of the NMOS region and the N-type source region form a silicon controlled rectifier (Silicon Controlled Rectifier, SCR) device, when PN junctions of the deep N-type well region and the P-type well region are reversely broken down, an avalanche current is generated in the P-type well region, and a parasitic bipolar junction transistor (Bipolar Junction Transistor, BJT) is conducted, a current release path is increased, thereby improving the secondary breakdown current (It 2) of the electrostatic protection structure and further improving the performance of the electrostatic protection structure.

The embodiment of the invention provides a method for forming an electrostatic protection structure, which comprises providing a substrate comprising a PMOS region and an NMOS region which are adjacently arranged, wherein a deep N-type well region is formed in the substrate of the PMOS region and the NMOS region, a P-type well region is formed in the deep N-type well region at the first side of a first isolation structure, the P-type well region in the PMOS region and the NMOS region is alternately arranged, an N-type well region is formed in the deep N-type well region at the second side of the first isolation structure, the N-type well region of the PMOS region and the P-type well region of the NMOS region are adjacently arranged, a P-type source region is formed in the P-type well region of the PMOS region, a P-type drain region is formed in the N-type well region of the PMOS region, an N-type source region is formed in the P-type well region of the NMOS region, and an N-type drain region is formed in the N-type well region of the NMOS region. Because the types of the conducting channels of the PMOS region and the NMOS region are different, and correspondingly, the PMOS region and the NMOS region have different conducting characteristics, the electrostatic protection structure of the embodiment of the invention can realize bidirectional protection, thereby improving the protection capability of the electrostatic protection structure and correspondingly improving the performance of the electrostatic protection structure; in addition, in the PMOS region and the NMOS region which are adjacently arranged, the N-type well region of the PMOS region and the P-type well region of the NMOS region are oppositely arranged, so that the P-type drain region, the N-type well region of the PMOS region, the deep N-type well region, the P-type well region of the NMOS region and the N-type source region form a silicon controlled device, when PN junctions of the deep N-type well region and the P-type well region are reversely biased to be broken down, avalanche current is generated, so that voltage drop is formed in the P-type well region, a parasitic bipolar junction transistor is conducted, a current discharge path is increased, the secondary breakdown current of the electrostatic protection structure is improved, and the performance of the electrostatic protection structure is further improved.

Drawings

FIG. 1 is a schematic view of an embodiment of an electrostatic protection structure according to the present invention;

fig. 2 to fig. 6 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming an electrostatic protection structure according to the present invention.

Detailed Description

As known from the background art, the performance of the current electrostatic protection structure needs to be improved.

In order to solve the technical problems, the embodiment of the invention provides an electrostatic protection structure, which comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a PMOS region and an NMOS region which are adjacently arranged, and deep N-type well regions are formed in the substrate of the PMOS region and the NMOS region; the first isolation structures are respectively positioned in the deep N-type well regions of the PMOS region and the NMOS region and are arranged at intervals; the P-type well region is respectively arranged in the PMOS region and the NMOS region and is positioned in the deep N-type well region at the first side of the first isolation structure, the P-type well region is respectively arranged in the PMOS region and the NMOS region and is positioned in the deep N-type well region at the second side of the first isolation structure, the N-type well region of the PMOS region and the P-type well region of the NMOS region are arranged oppositely in the PMOS region and the NMOS region which are adjacently arranged, the grid structure is respectively positioned on the P-type well region of the PMOS region and the NMOS region and is positioned at one side of the P-type well region close to the N-type well region of the same MOS region, the P-type source region is positioned in the P-type well region of the PMOS region and is positioned at one side of the N-type well region of the grid structure which is opposite to the PMOS region, the P-type well region is positioned in the N-type well region of the NMOS region, and the N-type well region is positioned at one side of the N-type well region of the grid structure which is opposite to the N-type well region of the PMOS region.

The electrostatic protection structure provided by the embodiment of the invention comprises a substrate, wherein the substrate comprises a PMOS region and an NMOS region which are adjacently arranged, deep N-type well regions are formed in the substrate of the PMOS region and the NMOS region, P-type well regions which are respectively positioned in the deep N-type well regions of the PMOS region and the NMOS region and are arranged at intervals, N-type well regions which are respectively positioned in the deep N-type well regions at the side parts of the P-type well regions of the PMOS region and the NMOS region, N-type well regions of the PMOS region and the P-type well regions of the NMOS region are oppositely arranged, P-type source regions which are positioned in the P-type well regions of the PMOS region, P-type drain regions which are positioned in the N-type well regions of the PMOS region, N-type source regions which are positioned in the P-type well regions of the NMOS region, and N-type drain regions which are positioned in the P-type well regions of the NMOS region. Because the types of the conducting channels of the PMOS region and the NMOS region are different, and correspondingly, the PMOS region and the NMOS region have different conducting characteristics, the electrostatic protection structure of the embodiment of the invention can realize bidirectional protection, thereby improving the protection capability of the electrostatic protection structure and correspondingly improving the performance of the electrostatic protection structure; in addition, in the PMOS region and the NMOS region which are adjacently arranged, the N-type well region of the PMOS region and the P-type well region of the NMOS region are oppositely arranged, so that the P-type drain region, the N-type well region of the PMOS region, the deep N-type well region, the P-type well region of the NMOS region and the N-type source region form a silicon controlled device, when PN junctions of the deep N-type well region and the P-type well region are reversely biased to be broken down, avalanche current is generated, so that voltage drop is formed in the P-type well region, a parasitic bipolar junction transistor is conducted, a current discharge path is increased, the secondary breakdown current of the electrostatic protection structure is improved, and the performance of the electrostatic protection structure is further improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings.

Fig. 1 is a schematic structural view of an embodiment of the electrostatic protection structure of the present invention.

Referring to fig. 1, in the present embodiment, the electrostatic protection structure includes a substrate 100, wherein the substrate 100 includes a PMOS region 11 and an NMOS region 12 disposed adjacently, and a deep N-type well region 110 is formed in the substrate 100 of the PMOS region 11 and the NMOS region 12; the first isolation structure 111 is respectively located in the deep N-type well region 110 of the PMOS region 11 and the NMOS region 12 and is arranged at intervals, the P-type well region 121 is respectively located in the deep N-type well region 110 of the PMOS region 11 and the NMOS region 12 and is located on the first side of the first isolation structure 111, the P-type well region 121 in the PMOS region 11 and the NMOS region 12 is arranged at intervals, the N-type well region 122 is respectively located in the deep N-type well region 110 of the second side of the first isolation structure 111 and is located in the deep N-type well region 110 of the second side of the first isolation structure 111, the N-type well region 122 of the PMOS region 11 and the P-type well region 121 of the NMOS region 12 are arranged opposite to each other, the gate structure 140 is respectively located on the P-type well region 121 of the PMOS region 11 and the NMOS region 12 and is located on one side of the P-type well region 122 of the same MOS region, the P-type source region 131 is located in the PMOS region 11 and the NMOS region 12 and is located on one side of the P-type well region 122 of the P-well region 135 and is located in the P-type well region 122 of the N-well region 122 of the PMOS region 12 and the N-type well region 122 is located on one side of the P-well region 121 and the N-well region 122 of the PMOS region 11 and the N-well region 12 is located on the side of the P-well region 122.

The substrate 100 is used to provide a process platform for the formation of an electrostatic discharge protection structure.

In this embodiment, the substrate 100 is used to form a laterally diffused metal oxide semiconductor transistor (lateral diffusion metal oxide semiconductor, LDMOS). Specifically, PMOS region 11 is used to form a PLDMOS, and NMOS region 12 is used to form a NLDMOS.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

In this embodiment, the substrate 100 is a P-type substrate (P-sub), that is, P-type ions are doped In the substrate 100, and the P-type ions include B ions, ga ions, or In ions.

The deep N-well region (DEEP N WELL, DNW) 110 is used to isolate the P-well region 121 from the P-substrate and also to isolate the N-well region 122 from the P-substrate, thereby reducing coupling noise of the substrate 100.

The first isolation structure 111 makes the lateral resistance between the source region and the drain region larger, thereby forcing the current to move longitudinally, increasing the transmission path of the current between the source region and the drain region, further increasing the resistance between the source region and the drain region, and correspondingly reducing the bleeder current, thereby increasing the protection capability.

Here, the lateral direction refers to a direction perpendicular to the sidewall of the gate structure 140, and the longitudinal direction refers to a normal direction of the top surface of the substrate 100.

Specifically, the material of the first isolation structure 111 includes silicon oxide.

Silicon oxide is a common material in the field of semiconductor manufacturing, has high process compatibility, is beneficial to reducing the forming difficulty and the process cost of the first isolation structure 111, and has a small dielectric constant, so that the effect of moving current longitudinally is good. In other embodiments, the material of the first isolation structure may be silicon nitride, silicon oxynitride, or other types of dielectric materials.

In the PMOS region 11, the P-type well region 121 is used to receive a larger partial pressure, the N-type well region 122 is used as a lateral diffusion region to form a channel having a concentration gradient, and in the NMOS region 12, the P-type well region 121 is used as a lateral diffusion region to form a channel having a concentration gradient, and the N-type well region 122 is used to receive a larger partial pressure. The P-well 121 of PMOS region 11 is subjected to a larger partial pressure, which is advantageous for increasing the breakdown voltage between P-source 131 and P-drain 132, and the N-well 122 of NMOS region 12 is also subjected to a larger partial pressure, which is advantageous for increasing the breakdown voltage between N-source 135 and N-drain 136.

That is, the P-type well region 121 of the PMOS region 11 and the N-type well region 122 of the NMOS region 12 are high-resistance regions, and the P-type well region 121 of the PMOS region 11 and the P-type well region 121 of the NMOS region 12 are formed, and the N-type well region 122 of the PMOS region 11 and the N-type well region 122 of the NMOS region 12 are formed, in the same step, in general, so that the doping ion concentrations of the P-type well region 121 and the N-type well region 122 are small, the ion doping concentration of the P-type well region 121 is smaller than the doping ion concentration of the P-type drain region 132, and the ion doping concentration of the N-type well region 122 is smaller than the doping ion concentration of the N-type drain region 136.

It is understood that the doped ions In the P-type well 121 are P-type ions, such As B-ions, ga-ions, or In-ions, and the doped ions In the N-type well 122 are N-type ions, such As P-ions, as-ions, or Sb-ions.

The P-type well region 121 is located on a first side of the first isolation structure 111, and the N-type well region 122 is located on a second side of the first isolation structure 111, that is, a space is provided between the N-type well region 122 and the P-type well region 121 of the same MOS region.

It should be noted that the P-type well region 121 also has a first side and a second side, the first side of the P-type well region 121 is opposite to the first side of the first isolation structure 111, the N-type well region 122 also has a first side and a second side, the second side of the first isolation structure 111 is opposite to the second side of the N-type well region 122, and in the PMOS region and the NMOS region that are adjacently disposed, the N-type well region of the PMOS region is opposite to the P-type well region of the NMOS region, and it is understood that in the PMOS region and the NMOS region that are adjacently disposed, the first side of the N-type well region 122 is opposite to the second side of the P-type well region 121.

In this embodiment, in the PMOS region 11 and the NMOS region 12 that are adjacently disposed, the sidewall of the N-type well region 122 of the PMOS region 11 is in contact with the sidewall of the P-type well region 121 of the NMOS region 12.

The sidewall of the N-type well region 122 of the PMOS region 11 contacts the sidewall of the P-type well region 121 of the NMOS region 12, which is beneficial to reducing the area of the substrate 100 occupied by the PMOS region 11 and the NMOS region 12, thereby saving the chip area.

The gate structure 140 is used to control the on and off of the channel.

The gate structures are respectively located on the P-type well region 121 of the PMOS region 11 and the NMOS region 12, so that the drain region and the gate structure 140 of the same MOS region are separated by a certain lateral distance, so as to improve the voltage-withstanding performance of the LDMOS transistor.

The gate structure 140 includes a gate dielectric layer (not shown), and a gate layer (not shown) covering the gate dielectric layer. In this embodiment, the gate structure 140 is a polysilicon gate structure, the gate dielectric layer is made of silicon oxide, and the gate layer is made of polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and the material of the gate dielectric layer may be a high-k gate dielectric material, for example HfO ₂ or Al ₂O₃, and the material of the gate layer may be metal, and the metal may be copper, aluminum, tungsten, or the like.

In this embodiment, the gate structure 140 further extends to cover the top of the adjacent first isolation structure 111.

The gate structure 140 further extends to cover the top of the adjacent first isolation structure 111, so as to increase a process window for forming the gate structure 140, reduce difficulty in forming the gate structure 140, and further facilitate weakening the electric field strength at the bottom corner of the gate structure 140, thereby facilitating improvement of the breakdown voltage of the LDMOS transistor.

In this embodiment, the semiconductor structure further includes a sidewall (not shown) located on the sidewall of the gate structure 140.

The sidewalls protect the sidewalls of the gate structure 140.

It should be noted that the material of the side wall may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride.

It should be noted that the side wall may have a single-layer structure or a stacked-layer structure.

The P-type source region 131 is used as a source terminal of the PLDMOS transistor, and the P-type drain region 132 is used as a drain terminal of the PLDMOS transistor. Accordingly, the P-type source region 131 and the P-type drain region 132 have P-type ions.

The N-type source region 135 is used as a source terminal of the NLDMOS transistor, and the N-type drain region 136 is used as a drain terminal of the NLDMOS transistor. Accordingly, the N-type source region 135 and the N-type drain region 136 have N-type ions.

In this embodiment, the electrostatic protection structure further includes a body region 133 located in the deep N-type well region 110 and surrounding the outermost peripheries of the P-type well region 121 and the N-type well region 122.

The deep N-well 110 is externally connected through a body region 133. The body region 133 has the same ion doping type as the substrate 100. Thus, as an example, the body region 133 is doped with P-type ions. And, the doping ion concentration of the body region 133 is greater than that of the deep N-type well region 110, so that the resistance of the body region 133 is smaller.

In other embodiments, the body region may be located only in the deep N-type well region at the outermost periphery of the P-type well region and the N-type well region.

In this embodiment, the electrostatic protection structure further includes a second isolation structure 112 located in the deep N-type well region 110 between the body region 133 and an adjacent well region.

The second isolation structure 112 is used for isolation between the body region 133 and an adjacent source or drain region, and blocks ion diffusion.

It is understood that, in the same MOS region, the P-type well region 121 and the N-type well region 122 are both located on a side of the second isolation structure 112 facing away from the body region 133, that is, in the same MOS region, the P-type well region 121 or the N-type well region 122 is located between the second isolation structure 112 and the first isolation structure 111. Accordingly, the second isolation structure 112 has a space from the adjacent first isolation structure 111.

Generally, the second isolation structure 112 and the first isolation structure 111 are formed in the same step, and the second isolation structure 112 and the first isolation structure 111 are formed in the same step, which is beneficial to simplifying the process flow and improving the process efficiency.

Accordingly, the material of the second isolation structure 112 is the same as that of the first isolation structure 111.

In this embodiment, the electrostatic protection structure further includes an interconnection structure (not shown), which is electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, respectively, and applies an electrical signal thereto, respectively.

The interconnection structure is electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, respectively, so that electrical signals can be applied to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region, respectively, through the interconnection structure.

Note that, the interconnection structure electrically connected to the P-type drain region 132 is used for applying a negative potential, the interconnection structure electrically connected to the N-type drain region 136 is used for applying a positive potential, and the interconnection structure electrically connected to the gate structure 140, the P-type source region 131, and the N-type source region 135 is used for applying a zero potential.

That is, the interconnect structure electrically connecting the P-type source region 131 serves as the anode of the PMOS region 11, the interconnect structure electrically connecting the P-type drain region 132 serves as the cathode of the PMOS region 11, the interconnect structure electrically connecting the N-type drain region 136 serves as the anode of the NMOS region 12, and the interconnect structure electrically connecting the N-type source region 135 serves as the cathode of the NMOS region 12.

Depending on the application, zero potential may be applied to the gate structures 140 of the PMOS region 11 and the NMOS region 12, or non-zero potential may be applied to the gate structures 140 of the PMOS region 11 and the NMOS region 12.

It should be further noted that the interconnection structure electrically connecting the gate structure 140, the P-type source region 131, and the N-type source region 135 is shorted.

The interconnection structure electrically connecting the gate structure 140, the P-type source region 131 and the N-type source region 135 is short-circuited, so that a process window of the interconnection structure electrically connecting the gate structure 140, the P-type source region 131 and the N-type source region 135 is easily increased, and the process difficulty is reduced.

Specifically, the material of the interconnection structure is a conductive material, such as copper.

In this embodiment, the electrostatic protection structure further includes plugs (not shown) electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, respectively, such that each of the interconnection structures is electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, respectively, through each of the plugs.

Specifically, the material of the plug is also a conductive material, such as tungsten, cobalt, ruthenium, and the like.

Correspondingly, the invention also provides a forming method of the electrostatic protection structure. Fig. 2 to fig. 6 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming an electrostatic protection structure according to the present invention.

Referring to fig. 2, a substrate 500 is provided, the substrate 500 including a PMOS region 51 and an NMOS region 52 disposed adjacently, the PMOS region 51 and the NMOS region 52 having a deep N-type well region 510 formed therein the substrate 500.

The substrate 500 is used to provide a process platform for the formation of an electrostatic discharge protection structure.

In this embodiment, the substrate 500 is used to form a laterally diffused metal oxide semiconductor transistor. Specifically, PMOS region 51 is used to form a PLDMOS, and NMOS region 52 is used to form a NLDMOS.

In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

In this embodiment, the substrate 500 is a P-type substrate, that is, the substrate 500 is doped with P-type ions, where the P-type ions include B ions, ga ions, or In ions.

The deep N-well 510 is used to isolate the P-well from the P-substrate and also to isolate the N-well from the P-substrate, thereby reducing noise coupling to the substrate 500.

Referring to fig. 3, first isolation structures 511 are formed in the deep N-well regions 510 of the PMOS region 51 and the NMOS region 52 at intervals.

In the subsequent step of forming the P-type well region and the N-type well region, in the same MOS region, adjacent P-type well region and N-type well region are respectively located at two sides of the same first isolation structure 511, so that the lateral resistance between the subsequently formed source region and drain region is correspondingly larger, thereby forcing the current to move longitudinally, increasing the transmission path of the current between the source region and the drain region, further increasing the resistance between the source region and the drain region, and correspondingly reducing the bleeder current, and further increasing the protection capability.

Here, the lateral direction refers to a direction perpendicular to the sidewall of the gate structure, and the longitudinal direction refers to a normal direction of the top surface of the substrate 500.

In this embodiment, the first isolation structure 511 is formed before the P-type well region and the N-type well region are formed, so that the positions of the P-type well region and the N-type well region are conveniently defined. In other embodiments, the first isolation structure may be formed after the P-type well region and the N-type well region are formed.

Specifically, the material of the first isolation structure 511 includes silicon oxide.

Silicon oxide is a common material in the semiconductor manufacturing field, has higher process compatibility, is favorable for reducing the forming difficulty and the process cost of the first isolation structure 511, and has smaller dielectric constant, so that the effect of moving current longitudinally is better. In other embodiments, the material of the first isolation structure may be silicon nitride, silicon oxynitride, or other types of dielectric materials.

In this embodiment, in the step of forming the first isolation structure 511, a second isolation structure 512 is formed in the deep N-well region 510 of the PMOS region 51 and the NMOS region 52, respectively, and the second isolation structure 512 is located on a side of the first isolation structure 511 facing away from the other MOS region in the same MOS region.

The second isolation structure 512 is used to isolate the body region formed later from the adjacent source or drain region and to block ion diffusion.

In the subsequent step of forming the P-type well region and the N-type well region, in the same MOS region, the P-type well region and the N-type well region are both located on a side of the second isolation structure 512 facing away from the body region, that is, the P-type well region and the N-type well region of the same MOS region are both located in a deep N-type well region on a side of the second isolation structure 512 facing toward the other MOS region, and then a P-type well region is formed on a first side of the first isolation structure 511, and an N-type well region is formed on a second side of the first isolation structure 511, that is, in the same MOS region, the P-type well region or the N-type well region is located between the second isolation structure 512 and the first isolation structure 511. Accordingly, in the step of forming the second isolation structure 512, in the same MOS region, there is a space between the second isolation structure 512 and the adjacent first isolation structure 511.

The second isolation structure 512 and the first isolation structure 511 are formed in the same step, which is beneficial to simplifying the process flow and improving the process efficiency.

Accordingly, the material of the second isolation structure 512 is the same as that of the first isolation structure 511.

In other embodiments, the second isolation structure may also be formed in a different step than the first isolation structure.

Referring to fig. 4, a P-type well region 521 is formed in the deep N-type well region 510 on the first side of the first isolation structure 511, the P-type well regions 521 in the PMOS region 51 and the NMOS region 52 are disposed at intervals, an N-type well region 522 is formed in the deep N-type well region 510 on the second side of the first isolation structure 511, and the N-type well region 522 of the PMOS region 51 is disposed opposite to the P-type well region 521 of the NMOS region 52 in the PMOS region 51 and the NMOS region 52 that are disposed adjacently.

In PMOS region 51, P-type well region 521 is used to receive a larger partial pressure, N-type well region 522 is used as a lateral diffusion region to form a channel having a concentration gradient, and in NMOS region 52, P-type well region 521 is used as a lateral diffusion region to form a channel having a concentration gradient, and N-type well region 522 is used to receive a larger partial pressure. The P-well 521 of PMOS region 51 receives a greater partial pressure, which is advantageous for increasing the breakdown voltage between the subsequently formed P-source and P-drain regions, and the N-well 522 of NMOS region 52 receives a greater partial pressure, which is advantageous for increasing the breakdown voltage between the subsequently formed N-source and N-drain regions.

That is, the P-type well 521 of the PMOS region 51 and the N-type well 522 of the NMOS region 52 are high-resistance regions, and in the same step, the P-type well 521 of the PMOS region 51 and the P-type well 521 of the NMOS region 52 are formed, and in the same step, the N-type well 522 of the PMOS region 51 and the N-type well 522 of the NMOS region 52 are formed, and therefore, the doping ion concentrations of the P-type well 521 and the N-type well 522 are small, the ion doping concentration of the P-type well 521 is smaller than the doping ion concentration of the P-type drain formed later, and the ion doping concentration of the N-type well 522 is smaller than the doping ion concentration of the N-type drain formed later.

It is understood that the doped ions In P-type well 521 are P-type ions, such As B-ions, ga-ions, or In-ions, and the doped ions In N-type well 522 are N-type ions, such As P-ions, as-ions, or Sb-ions.

The P-type well 521 is located on the first side of the first isolation structure 511, and the N-type well 522 is located on the second side of the first isolation structure 511, that is, there is a space between the N-type well 522 and the P-type well 521 of the same MOS region.

It should be noted that the P-type well region 521 also has a first side and a second side, the first side of the P-type well region 521 is opposite to the first side of the first isolation structure 511, the N-type well region 522 also has a first side and a second side, the second side of the first isolation structure 511 is opposite to the second side of the N-type well region 522, and in the PMOS region and the NMOS region that are adjacently disposed, the N-type well region of the PMOS region is opposite to the P-type well region of the NMOS region, it is understood that in the PMOS region and the NMOS region that are adjacently disposed, the first side of the N-type well region 522 is opposite to the second side of the P-type well region 521.

Specifically, the deep N-well 510 in the specific region is doped by using a mask (mask) and different ion implantation processes, so as to form the P-well 521 and the N-well 522 in the deep N-well 510 of the PMOS region 51 and form the P-well 521 and the N-well 522 in the deep N-well 510 of the NMOS region 52.

The P-type well region 521 may be formed first and then the N-type well region 522 may be formed, or the N-type well region 522 may be formed first and then the P-type well region 521 may be formed.

In this embodiment, in the step of forming the P-type well region 521 and the N-type well region 522, in the PMOS region 51 and the NMOS region 52 that are disposed adjacently, the sidewall of the N-type well region 522 of the PMOS region 51 contacts the sidewall of the P-type well region 521 of the NMOS region 52.

The sidewall of the N-type well 522 of the PMOS region 51 contacts the sidewall of the P-type well 521 of the NMOS region 52, which is beneficial to reducing the area of the substrate 500 occupied by the PMOS region 51 and the NMOS region 52, thereby saving the chip area.

Accordingly, in the present embodiment, in the step of forming the P-type well 521 and the N-type well 522, the P-type well 521 and the N-type well 522 of the same MOS region are located on the side of the second isolation structure 512 facing the other MOS region.

Referring to fig. 5, gate structures 540 are formed on the P-type well regions 521 of the PMOS region 51 and the NMOS region 52, respectively, and the gate structures 540 are located on one side of the P-type well regions 521 near the N-type well regions 522 in the same MOS region.

The gate structure 540 is used to control the channel on and off.

Gate structures 540 are formed on the P-type well regions 521 of the PMOS region 51 and the NMOS region 52, respectively, so that the subsequently formed drain region and the gate structure 540 of the same MOS region are separated by a certain lateral distance, so as to improve the voltage-withstanding performance of the LDMOS transistor.

Note that the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region may be formed after the gate structure 540 is formed, or the gate structure 540 may be formed after the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region are formed.

The gate structure 540 includes a gate dielectric layer (not shown) and a gate layer (not shown) covering the gate dielectric layer. In this embodiment, the gate structure 540 is a polysilicon gate structure, the gate dielectric layer is made of silicon oxide, and the gate layer is made of polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and the material of the gate dielectric layer may be a high-k gate dielectric material, for example HfO ₂ or Al ₂O₃, and the material of the gate layer may be metal, and the metal may be copper, aluminum, tungsten, or the like.

In this embodiment, in the step of forming the gate structure 540, the gate structure 540 further extends to cover the top of the adjacent first isolation structure 511.

The gate structure 540 further extends to cover the top of the adjacent first isolation structure 511, so as to increase a process window for forming the gate structure 540, reduce difficulty in forming the gate structure 540, and further facilitate weakening the electric field strength at the bottom corner of the gate structure 540, thereby facilitating improvement of the breakdown voltage of the LDMOS transistor.

In this embodiment, after forming the gate structure 540, forming a sidewall (not shown) on the sidewall of the gate structure 540 is further included.

The sidewalls protect the sidewalls of the gate structure 540.

Referring to fig. 6, a P-type source region 531 is formed in the P-type well region 521 of the PMOS region 51 with a space between the sidewall of the P-type source region 531 and the sidewall of the P-type well region 521 where it is located, a P-type drain region 532 is formed in the N-type well region 522 of the PMOS region 51, an N-type source region 535 is formed in the P-type well region 521 of the NMOS region 52 with a space between the sidewall of the N-type source region 535 and the sidewall of the P-type well region 521 where it is located, and an N-type drain region 536 is formed in the N-type well region 522 of the NMOS region 52.

The P-type source region 531 is used as a source terminal of the PLDMOS transistor, and the P-type drain region 532 is used as a drain terminal of the PLDMOS transistor. Accordingly, the P-type source region 531 and the P-type drain region 532 have P-type ions.

The N-type source region 535 is used as the source terminal of the NLDMOS transistor and the N-type drain region 536 is used as the drain terminal of the NLDMOS transistor. Accordingly, the N-type source region 535 and the N-type drain region 536 have N-type ions.

The gate structure 540 is located on the P-well 521 of the PMOS region 51 and the NMOS region 52, respectively, so that a space is easily provided between the sidewall of the P-source 531 and the sidewall of the P-well 521 where it is located, and a space is provided between the sidewall of the N-source 535 and the sidewall of the P-well 521 where it is located.

Specifically, the P-type well 521 and the N-type well 522 of the PMOS region 51, and the P-type well 521 and the N-type well 522 of the NMOS region 52 are doped by using a photomask to form the P-type source 531, the P-type drain 532, the N-type source 535 and the N-type drain 536.

The P-type source region 531 and the P-type drain region 532 may be formed first, and then the N-type source region 535 and the N-type drain region 536 may be formed, or the N-type source region 535 and the N-type drain region 536 may be formed first, and then the P-type source region 531 and the P-type drain region 532 may be formed.

In this embodiment, in the step of forming the P-type source region 531 and the P-type drain region, a body region 533 is formed in the deep N-type well region 510, and the body region 533 surrounds the outermost peripheries of the P-type well region and the N-type well region.

The deep N-well 510 is externally connected through a body 533. The body 533 has the same ion doping type as the substrate 500. Thus, as an example, the body 533 is doped with P-type ions. And, the doping ion concentration of the body 533 is greater than that of the deep N-type well 510, so that the resistance of the body 533 is smaller.

Correspondingly, the deep N-well 510 is doped by ion implantation using a photomask to form the body 533.

In other embodiments, body region 533 may also be formed by a separate step.

Accordingly, in the present embodiment, in the step of forming the P-type drain region 532, the P-type source region 531, the N-type drain region 536, the N-type source region 535 and the body region 533, the P-type drain region 532 and the P-type source region 531 are located at one side of the second isolation structure 512 of the PMOS region 51 facing the NMOS region 52, the body region 533 of the PMOS region 51 is located at the other side of the second isolation structure 512 of the PMOS region 51, the N-type drain region 536 and the N-type source region 535 are located at one side of the second isolation structure 512 of the NMOS region 52 facing the PMOS region 51, and the body region 533 of the NMOS region 52 is located at the other side of the second isolation structure 512 of the NMOS region 52.

In this embodiment, after forming the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536, the forming method further includes forming an interconnection structure (not shown) electrically connected to and applying an electrical signal to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536, respectively.

The interconnect structure is electrically connected to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536, respectively, so that electrical signals are applied to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region, respectively, by the interconnect structure.

Note that the interconnect structure electrically connected to the P-type drain region 532 is used to apply a negative potential, the interconnect structure electrically connected to the N-type drain region 536 is used to apply a positive potential, and the interconnect structures electrically connected to the gate structure 540, the P-type source region 531, and the N-type source region 535 are used to apply a zero potential.

That is, the interconnect structure electrically connecting the P-type source region 531 serves as the anode of the PMOS region 51, the interconnect structure electrically connecting the P-type drain region 532 serves as the cathode of the PMOS region 51, the interconnect structure electrically connecting the N-type drain region 536 serves as the anode of the NMOS region 52, and the interconnect structure electrically connecting the N-type source region 535 serves as the cathode of the NMOS region 52.

Depending on the application, a zero potential may be applied to the gate structures 540 of the PMOS region 51 and NMOS region 52, or a non-zero potential may be applied to the gate structures 540 of the PMOS region 51 and NMOS region 52.

It should be further noted that, in the step of forming the interconnection structure, the interconnection structure electrically connecting the gate structure 540, the P-type source region 531, and the N-type source region 535 is shorted.

The interconnection structure electrically connecting the gate structure 540, the P-type source region 531 and the N-type source region 535 is short-circuited, so that a process window of the interconnection structure electrically connecting the gate structure 540, the P-type source region 531 and the N-type source region 535 is easily increased, and the process difficulty is reduced.

In this embodiment, after the gate structure 540 is formed, before the forming of the interconnection structure, plugs (not shown) electrically connected to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536 respectively are further formed, and each interconnection structure is electrically connected to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536 respectively through each plug.

It should be noted that the electrostatic protection structure may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. For a specific description of the electrostatic protection structure according to this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. An electrostatic protection structure, comprising:

The substrate comprises a PMOS region and an NMOS region which are adjacently arranged, and deep N-type well regions are formed in the substrate of the PMOS region and the NMOS region;

The first isolation structures are respectively positioned in the deep N-type well regions of the PMOS region and the NMOS region and are arranged at intervals;

the P-type well region is respectively positioned in the PMOS region and the NMOS region and is positioned in the deep N-type well region at the first side of the first isolation structure, and the P-type well regions in the PMOS region and the NMOS region are arranged at intervals;

The N-type well region is respectively positioned in the PMOS region and the NMOS region and is positioned in the deep N-type well region at the second side of the first isolation structure, and in the PMOS region and the NMOS region which are adjacently arranged, the N-type well region of the PMOS region and the P-type well region of the NMOS region are oppositely arranged;

the grid structure is respectively positioned on the P-type well regions of the PMOS region and the NMOS region and is positioned at one side of the P-type well region, which is close to the N-type well region of the same MOS region;

the P-type source region is positioned in the P-type well region of the PMOS region and is positioned at one side of the grid structure, which is opposite to the N-type well region of the PMOS region;

the P-type drain region is positioned in the N-type well region of the PMOS region;

the N-type source region is positioned in the P-type well region of the NMOS region and is positioned at one side of the grid structure, which is back to the N-type well region of the NMOS region;

And the N-type drain region is positioned in the N-type well region of the NMOS region.

2. The electrostatic protection structure according to claim 1, wherein in the PMOS region and the NMOS region that are adjacently disposed, an N-type well region sidewall of the PMOS region is in contact with a P-type well region sidewall of the NMOS region.

3. The electrostatic protection structure according to claim 1 or 2, wherein the gate structure further extends to cover a top of an adjacent first isolation structure.

4. The electrostatic protection structure according to claim 1, further comprising a body region located in the deep N-well region and surrounding outermost peripheries of the P-well region and the N-well region.

5. The electrostatic protection structure of claim 4, further comprising a second isolation structure located in the deep N-well region between the body region and an adjacent well region.

6. The electrostatic protection structure according to claim 1, wherein the material of the first isolation structure comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.

7. The electrostatic protection structure according to claim 1, further comprising an interconnect structure electrically connected to and applying an electrical signal to the gate structure, the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region, respectively.

8. The electrostatic protection structure according to claim 7, wherein an interconnect structure electrically connected to the P-type drain region is used to apply a negative potential, an interconnect structure electrically connected to the N-type drain region is used to apply a positive potential, and an interconnect structure electrically connected to the gate structure, the P-type source region, and the N-type source region is used to apply a zero potential.

9. The electrostatic protection structure according to claim 8, wherein an interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.

10. A method of forming an electrostatic protection structure, comprising:

Providing a substrate, wherein the substrate comprises a PMOS region and an NMOS region which are adjacently arranged, and deep N-type well regions are formed in the substrate of the PMOS region and the NMOS region;

Forming first isolation structures arranged at intervals in the deep N-type well regions of the PMOS region and the NMOS region;

Forming a P-type well region in the deep N-type well region at the first side of the first isolation structure, wherein the P-type well regions in the PMOS region and the NMOS region are arranged at intervals;

Forming an N-type well region in a deep N-type well region at the second side of the first isolation structure, wherein the N-type well region of the PMOS region and the P-type well region of the NMOS region are arranged opposite to each other in the PMOS region and the NMOS region which are adjacently arranged;

Forming gate structures on the P-type well regions of the PMOS region and the NMOS region respectively, wherein the gate structures are positioned on one side of the P-type well region, which is close to the N-type well region in the same MOS region;

Forming a P-type source region in the P-type well region of the PMOS region, wherein a space is reserved between the side wall of the P-type source region and the side wall of the P-type well region where the P-type source region is positioned, and a P-type drain region is formed in the N-type well region of the PMOS region;

forming an N-type source region in the P-type well region of the NMOS region, wherein a space is reserved between the side wall of the N-type source region and the side wall of the P-type well region where the N-type source region is positioned, and an N-type drain region is formed in the N-type well region of the NMOS region;

the P-type source region and the P-type drain region are positioned on two sides of the grid structure in the PMOS region, and the N-type source region and the N-type drain region are positioned on two sides of the grid structure in the NMOS region.

11. The method of claim 10, wherein in the step of forming the P-type well region and the N-type well region, an N-type well region sidewall of the PMOS region is in contact with a P-type well region sidewall of the NMOS region in the PMOS region and the NMOS region disposed adjacently.

12. The method of claim 10, wherein in the step of forming the gate structure, the gate structure further extends to cover a top of the adjacent first isolation structure.

13. The method of claim 10, wherein in the step of forming the P-type source region and the P-type drain region, a body region is formed in the deep N-type well region, and the body region surrounds outermost peripheries of the P-type well region and the N-type well region.

14. The method of forming an electrostatic protection structure according to claim 13, wherein in the step of forming the first isolation structure, a second isolation structure having a space from the first isolation structure of the same MOS region is formed in the deep N-type well region of the PMOS region and the NMOS region, respectively, the second isolation structure being located on a side of the first isolation structure facing away from the other MOS region in the same MOS region;

In the step of forming the P-type well region and the N-type well region, the P-type well region and the N-type well region of the same MOS region are both positioned at one side of the second isolation structure facing the other MOS region;

In the step of forming the P-type drain region, the P-type source region, the N-type drain region, the N-type source region and the body region, the P-type drain region and the P-type source region are both located at one side of the second isolation structure of the PMOS region facing the NMOS region, the body region of the PMOS region is located at the other side of the second isolation structure of the PMOS region, the N-type drain region and the N-type source region are both located at one side of the second isolation structure of the NMOS region facing the PMOS region, and the body region of the NMOS region is located at the other side of the second isolation structure of the NMOS region.

15. The method of claim 10, further comprising forming an interconnect structure electrically connected to and applying an electrical signal to the gate structure, the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region, respectively.

16. The method of claim 15, wherein in the step of forming the interconnect structure, the interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.