CN119828367B - Composite waveguide structure and preparation method thereof - Google Patents
Composite waveguide structure and preparation method thereofInfo
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- CN119828367B CN119828367B CN202510124229.4A CN202510124229A CN119828367B CN 119828367 B CN119828367 B CN 119828367B CN 202510124229 A CN202510124229 A CN 202510124229A CN 119828367 B CN119828367 B CN 119828367B
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Abstract
The application provides a composite waveguide structure and a preparation method thereof, belonging to the technical field of electro-optic modulators, wherein the composite waveguide structure comprises a first waveguide wafer and a waveguide film, the first waveguide wafer comprises a first substrate, a passivation layer, a first waveguide structure in the passivation layer and a metal electrode, the metal electrodes are arranged on two sides of the first waveguide structure, a first waveguide cladding layer is covered on the upper side of the first waveguide structure, and a first bonding pad hole is arranged on the upper side of the metal electrode; the waveguide film comprises a second substrate, an oxygen burying layer arranged on the second substrate and a second waveguide structure arranged on the upper side of the oxygen burying layer, second bonding pad holes are formed in two sides of the second waveguide structure, a second waveguide cladding layer is covered on the upper side of the second waveguide structure, the second waveguide cladding layer is bonded with the first waveguide cladding layer, the position of the second waveguide structure corresponds to the position of the first waveguide structure, and the position of the second bonding pad holes corresponds to the position of the first bonding pad holes. The application improves the compatibility of the W2W heterogeneous integration mode and the CMOS process.
Description
Technical Field
The application relates to the technical field of electro-optical modulators, in particular to a composite waveguide structure and a preparation method thereof.
Background
Devices using optical devices, such as optical communications, radio frequency photonic systems, millimeter wave meters, etc., have increasingly high bandwidth requirements. In the semiconductor photon modulator, the limitation of electron carrier transmission time fundamentally affects the high frequency operation characteristics of the diode-based Electro-optical modulator (EOM), so that there is great interest in the study of materials having the high frequency Electro-optical modulation characteristics. While lithium niobate LiNbO 3 (lithium niobate, LN) has received widespread attention in integrated optics due to its superior electro-optic and nonlinear optical properties, mach-zehnder electro-optic modulators (Mach-Zehnder modulators, MZM) that are heterogeneously integrated with silicon or silicon nitride waveguides have proven to achieve very high modulation bandwidths, supporting high frequency modulation well beyond 100 GHz.
The electro-optic modulator is preferably fabricated in a manner compatible with conventional CMOS processes used in silicon photonics for higher performance, lower cost, and better fabrication scalability. For electro-optical modulation (composite waveguide) structures composed of thin film lithium niobate and silicon nitride, chip-to-Wafer (D2W) or Wafer-to-Wafer (W2W) bonding is typically used.
In the process of machining the LN-SiNx composite waveguide in a W2W bonding mode, the front-path processes such as photoetching, film preparation and the like are usually carried out on LN and metal electrodes, so that the LN-SiNx composite waveguide is incompatible with a CMOS process, the LN machining process depends on the machining process of a SiNx waveguide chip, the machining flexibility of the LN process is limited, and the process efficiency is reduced. In fact, the buried electrode structure is formed by making a metal electrode (Al) under the SiNx, then the single chip formed by cutting and dicing LN is combined with the SiNx waveguide wafer or the single SiNx waveguide chip through D2W or D2D bonding, so that the problem of incompatibility of the CMOS process can be solved, but the Si substrate removal process of LN is subject to great risks and challenges, such as the risk of LN chip falling off when ① Si is ground in the D2W mode, the risk of damage to the SiNx waveguide device caused by etching liquid when residual Si is etched in the wet mode after ② is ground, and the like, and the Si substrate is removed in the dry mode in the D2D mode, which is also incompatible with the CMOS process and is not suitable for batch processing.
Disclosure of Invention
In view of the above, embodiments of the present application provide a composite waveguide structure and a method for manufacturing the same, which at least partially solve the problems of incompatibility with the CMOS process and low process efficiency in the process flow in the prior art.
In a first aspect, an embodiment of the present application provides a composite waveguide structure, including a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, where the first waveguide wafer includes a first substrate, a passivation layer disposed on the first substrate, a first waveguide structure disposed in the passivation layer, and a metal electrode disposed on two sides of the first waveguide structure, where a first waveguide cladding layer is disposed on an upper side of the first waveguide structure, a first pad hole is disposed on an upper side of the metal electrode, and the waveguide film includes a second substrate, an oxygen-buried layer disposed on the second substrate, and a second waveguide structure disposed on an upper side of the oxygen-buried layer, where two sides of the second waveguide structure are disposed with second pad holes, and where a second waveguide cladding layer is disposed on an upper side of the second waveguide structure, where the second waveguide cladding layer is bonded to the first waveguide cladding layer, and where a position of the second waveguide structure corresponds to a position of the first waveguide structure, and where a position of the second pad hole corresponds to a position of the first pad hole.
In a second aspect, an embodiment of the present application further provides a method for preparing a composite waveguide structure, which is used for preparing the composite waveguide structure according to the first aspect, and the method includes:
Sequentially preparing a metal electrode and a first waveguide structure on a passivation layer of a first substrate, wherein the metal electrode is arranged on two sides of the first waveguide structure;
preparing and flattening a first waveguide cladding layer of the first waveguide structure;
forming a first bonding pad hole by punching above the metal electrode so as to obtain a first waveguide wafer;
Preparing an electro-optic material substrate wafer, wherein the electro-optic material substrate wafer comprises a second substrate, an oxygen burying layer and an electro-optic material film which are arranged in a laminated manner;
Patterning the electro-optic material film to form a second waveguide structure, and enabling the position of the second waveguide structure to correspond to the position of the first waveguide structure through layout design;
Preparing and flattening a second waveguide cladding layer of the second waveguide structure;
Opening the second waveguide cladding layer and the oxygen-buried layer to form a second bonding pad hole, and enabling the position of the second bonding pad hole to correspond to the position of the first bonding pad hole through layout design to obtain a second waveguide wafer;
Bonding the first waveguide wafer and the second waveguide wafer through the first waveguide cladding and the second waveguide cladding;
and removing the second substrate.
According to a specific implementation manner of the embodiment of the present application, the sequentially preparing the metal electrode and the first waveguide structure on the passivation layer of the first substrate includes:
Depositing a first passivation layer on the first substrate;
depositing a metal film on the first passivation layer;
patterning the metal film through a patterning process to form the metal electrode;
Depositing a second passivation layer and flattening, and depositing a Si Nx film on the second passivation layer;
And processing the Si Nx film through a patterning process to form the first waveguide structure.
According to a specific implementation manner of the embodiment of the present application, the preparing and planarizing the first waveguide cladding layer of the first waveguide structure includes:
Depositing the first waveguide cladding based on a CVD process;
And carrying out planarization treatment through a chemical mechanical polishing process to reduce the thickness of the first waveguide cladding above the first waveguide structure to a first preset thickness.
According to a specific implementation manner of the embodiment of the present application, the forming a first pad hole by forming an opening above the metal electrode includes:
and forming the first pad hole by carrying out dry etching on the second passivation layer and the first waveguide cladding layer above the metal electrode.
According to a specific implementation manner of the embodiment of the present application, the patterning the electro-optic material film to form a second waveguide structure includes:
And patterning the electro-optic material film by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure.
According to a specific implementation manner of the embodiment of the present application, the preparing and planarizing the second waveguide cladding layer of the second waveguide structure includes:
depositing the second waveguide cladding based on a CVD process;
and carrying out planarization treatment through a chemical mechanical polishing process to reduce the thickness of the second waveguide cladding above the second waveguide structure to a second preset thickness.
According to a specific implementation manner of the embodiment of the present application, a sum of the first preset thickness and the second preset thickness is smaller than 150nm.
According to a specific implementation manner of the embodiment of the present application, the bonding the first waveguide wafer and the second waveguide wafer includes:
cleaning and activating plasmas are sequentially carried out on the first waveguide wafer and the second waveguide wafer;
aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonding device;
and annealing the pre-bonding device to complete the bonding.
According to a specific implementation manner of the embodiment of the present application, the removing the second substrate includes:
the second substrate is removed by grinding or chemical mechanical polishing processes.
The beneficial effects are that:
According to the composite waveguide structure and the preparation method thereof, according to the W2W bonding alignment relation, pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, front process processing such as photoetching and film preparation is not needed after W2W is achieved, compatibility of a W2W heterogeneous integration mode and a CMOS process is improved, flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer is fully utilized, compatibility of process structures of bonding areas and non-bonding areas is improved, and for example, waveguide cladding thickness between LN-Si layers of the bonding areas and Si Nx waveguide cladding thickness of the non-bonding areas can be differentiated according to design requirements.
In addition, compared with a D2W bonding mode, the method reduces the drop risk of the LN chip in the process of removing the LN Si substrate, can directly remove the Si substrate by a chemical mechanical polishing mode, avoids the problems of low processing efficiency, damage of SiNx waveguide devices and the like caused by wet etching, simplifies the process flow, and has smaller LN chip size and improves the integration level of the optical chip compared with the D2W bonding mode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a composite waveguide structure according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a composite waveguide structure according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of preparing a first passivation layer according to an embodiment of the present invention;
FIG. 4 is a schematic illustration of a metal electrode prepared according to an embodiment of the invention;
FIG. 5 is a schematic illustration of preparing a second passivation layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure for fabricating a Si Nx waveguide according to an embodiment of the present invention;
FIG. 7 is a schematic illustration of preparing a first waveguide cladding layer according to one embodiment of the present invention;
FIG. 8 is a schematic illustration of preparing a first bond pad hole in accordance with an embodiment of the present invention;
FIG. 9 is a schematic diagram of a wafer for preparing an electro-optic material substrate according to one embodiment of the present invention;
FIG. 10 is a schematic illustration of a fabricated LN waveguide structure in accordance with one embodiment of the invention;
FIG. 11 is a schematic illustration of preparing a second waveguide cladding layer according to one embodiment of the present invention;
FIG. 12 is a schematic illustration of preparing a second bond pad hole in accordance with an embodiment of the present invention;
Fig. 13 is a schematic diagram of bonding a first waveguide wafer and a second waveguide wafer according to an embodiment of the present invention.
In the figure, 1, a first substrate, 2, a silicon dioxide film, 3, a metal electrode, 4, a first waveguide structure, 5, a first bonding pad hole, 6, an electro-optic material film, 7, a second substrate, 8, an oxygen buried layer, 9, a second waveguide structure and 10, a second bonding pad hole.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the illustrations, not according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
In a first aspect, referring to fig. 1, an embodiment of the present application provides a composite waveguide structure, where the composite waveguide structure includes a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, the first waveguide wafer includes a first substrate 1, a passivation layer disposed on the first substrate 1, a first waveguide structure 4 and a metal electrode 3 disposed in the passivation layer, the metal electrode 3 is disposed on two sides of the first waveguide structure 4, a first waveguide cladding layer is covered on an upper side of the first waveguide structure 4, a first pad hole 5 is disposed on an upper side of the metal electrode 3, the waveguide film includes a second substrate 7, an oxygen-buried layer 8 disposed on the second substrate 7, and a second waveguide structure 9 disposed on an upper side of the oxygen-buried layer 8, second pad holes 10 are disposed on two sides of the second waveguide structure 9, the second waveguide cladding layer is bonded to the first waveguide cladding layer, and a position of the second waveguide structure 9 corresponds to a position of the first waveguide pad hole 10.
In an implementation, the waveguide film bonded to the first waveguide wafer may be a film formed by removing the second substrate from the second waveguide wafer. For the first waveguide wafer, for example, an S i Nx waveguide wafer may be provided, and for the second waveguide wafer, for example, an LN waveguide wafer may be provided.
In the embodiment, the upper and lower bonding pad holes are correspondingly arranged, and in actual preparation, indirect alignment can be performed through photoetching layout design, so that front-path process processing such as photoetching and film preparation is not needed after W2W, and the compatibility of a W2W heterogeneous integration mode and a CMOS process is improved.
In a second aspect, referring to fig. 2, an embodiment of the present application further provides a method for preparing a composite waveguide structure according to the first aspect, the method including the steps of:
Step S101, sequentially preparing a metal electrode 3 and a first waveguide structure 4 on a passivation layer of a first substrate 1, wherein the metal electrode 3 is arranged on two sides of the first waveguide structure 4;
step S102, preparing and flattening a first waveguide cladding layer of the first waveguide structure 4;
step S103, punching holes above the metal electrode 3 to form a first bonding pad hole 5 so as to obtain a first waveguide wafer;
step S104, preparing an electro-optic material substrate wafer, wherein the electro-optic material substrate wafer comprises a second substrate 7, an oxygen burying layer 8 and an electro-optic material film 6 which are arranged in a laminated manner;
Step 105, patterning the electro-optic material film 6 to form a second waveguide structure 9, and enabling the position of the second waveguide structure 9 to correspond to the position of the first waveguide structure 4 through layout design;
step S106, preparing and flattening a second waveguide cladding layer of the second waveguide structure 9;
Step S107, perforating the second waveguide cladding layer and the buried oxide layer 8 to form a second bonding pad hole 10, and enabling the position of the second bonding pad hole 10 to correspond to the position of the first bonding pad hole 5 through layout design to obtain a second waveguide wafer;
Step S108, bonding the first waveguide wafer and the second waveguide wafer, and bonding the first waveguide cladding layer and the second waveguide cladding layer;
step S109, removing the second substrate 7.
In the implementation, the structure of the second waveguide wafer after the second substrate 7 is removed is the waveguide film bonded with the first waveguide wafer. In practical applications, the first waveguide wafer may be, for example, a SiNx waveguide wafer, where the first waveguide structure is a SiNx waveguide structure, and the second waveguide wafer may be, for example, an LN waveguide wafer, where the second waveguide structure is an LN waveguide structure.
In the embodiment, according to the W2W bonding alignment relationship, pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, so that front process processing such as photoetching, film preparation and the like is not needed after W2W is realized, compatibility of a W2W heterogeneous integration mode and a CMOS (complementary metal oxide semiconductor) process is improved, the advantage of flexibility of independent processing of the first waveguide wafer and the second waveguide wafer is fully utilized, process structure compatibility of a bonding area and a non-bonding area is improved, and for example, waveguide cladding thickness between LN-SiNx layers of the bonding area and SiNx waveguide cladding thickness of the non-bonding area can be differentiated according to design requirements.
In addition, compared with a D2W bonding mode, the method reduces the drop risk of the LN chip in the process of removing the LN Si substrate, can directly remove the Si substrate by a chemical mechanical polishing mode, avoids the problems of low processing efficiency, damage of SiNx waveguide devices and the like caused by wet etching, simplifies the process flow, and has smaller LN chip size and improves the integration level of the optical chip compared with the D2W bonding mode.
In particular, the first substrate 1 and the second substrate 7 may be provided as silicon bases.
In one embodiment, referring to fig. 3 to 6, the preparing the metal electrode 3 and the first waveguide structure 4 sequentially on the passivation layer of the first substrate 1 includes:
Depositing a first passivation layer on the first substrate 1, as shown in fig. 3;
depositing a metal film on the first passivation layer;
processing the metal film through a patterning process to form the metal electrode 3, as shown in fig. 4;
depositing a second passivation layer and flattening, as shown in fig. 5, depositing a SiNx film on the second passivation layer;
The SiNx film is processed by a patterning process to form the first waveguide structure 4, as shown in fig. 6.
In specific implementation, the patterning process may use photolithography, etching, and other processes.
In practice, the first passivation layer and the second passivation layer may be provided as the silicon dioxide film 2, respectively. The specific preparation process of the metal electrode 3 and the first waveguide structure 4 comprises:
Firstly, preparing a silicon dioxide film 2 on a silicon substrate, wherein the silicon dioxide film 2 with the thickness of 1-8 mu m is prepared on the Si substrate by a CVD or thermal oxidation growth mode;
the preparation of the metal electrode 3 specifically comprises PVD depositing a metal film with the thickness of 0.5-1.5 μm, and then forming a lead electrode structure by patterning processes such as photoetching;
preparing and flattening a second passivation layer, namely depositing silicon dioxide by CVD, and flattening the silicon dioxide by CMP until the thickness of the silicon dioxide film 2 above the metal electrode 3 is 200-500 nm;
And preparing and waveguide patterning the SiNx film, namely depositing the SiNx film with the thickness of 100-500 nm and the refractive index of 1.9-2.2 by CVD, and then manufacturing and forming the first waveguide structure 4 by patterning processes such as photoetching and the like.
In one embodiment, the first waveguide cladding layer preparation and planarization of the first waveguide structure 4 includes:
Depositing the first waveguide cladding based on a CVD process;
and carrying out planarization treatment through a chemical mechanical polishing process to reduce the thickness of the first waveguide cladding above the first waveguide structure 4 to a first preset thickness h1.
In practice, the first waveguide cladding layer is provided as the silica film 2, i.e. the first passivation layer, the second passivation layer and the first waveguide cladding layer may all be provided as the silica film 2.
In one embodiment, the forming the first pad hole 5 by forming the hole above the metal electrode 3 includes:
The second passivation layer and the first waveguide cladding layer above the metal electrode 3 are opened by dry etching to form the first pad hole 5.
In a specific implementation, the operation of opening the hole above the metal electrode 3 is pad windowing, and the metal pad can be exposed through silicon dioxide dry etching. At least two first pad holes 5 are generally provided, for example, as shown in fig. 8, in which two first pad holes 5 are provided. In a practical process, the number of the openings can be adjusted according to requirements.
In specific implementation, the processing process of the first waveguide wafer in the above embodiment is compatible with the CMOS process, so that the CMOS process compatibility of the W2W heterogeneous integration mode is improved.
The processing of the second waveguide wafer is described in detail below, and the processing of the second waveguide wafer may be performed by a dedicated line outside the CMOS processing environment, see in particular the following examples.
In specific implementation, the electro-optic material substrate wafer is set to be a film LN substrate wafer, which is a commercially mature film LN substrate, wherein the electro-optic material film 6 is an LN film, and the thickness of the electro-optic material film is 100 nm-500 nm. The preparation is carried out by adopting a Smart-cut process, which is a process technology that a damaged layer is formed by ion implantation of a bulk LN and cleavage and shedding occur along the damaged layer after annealing at 200-300 ℃, the second substrate 7 is a Si base, wherein the thickness of the oxygen-buried layer 8 is 0.1-2 mu m, the oxygen-buried layer 8 is a SiO 2 film prepared by adopting a thermal oxidation growth mode, and the specific structure of the wafer of the thin film LN substrate is shown in figure 9.
In one embodiment, referring to fig. 10, the patterning of the electro-optic material film 6 to form the second waveguide structure 9 includes:
the second waveguide structure 9 is formed by patterning the thin film 6 of electro-optic material by a dry etching process of inductively coupled plasma-reactive ion etching.
In practice, the film 6 of electro-optic material is etched by inductively coupled plasma-reactive ion etching to form a second waveguide structure 9. It should be noted that, in the patterning of the photolithography layout for this step, the position of the second waveguide structure 9 needs to be determined according to the subsequent flip alignment relationship of W2W bonding with the first waveguide wafer, so as to achieve indirect alignment of the second waveguide structure 9 and the first waveguide structure 4 on the layout.
In one embodiment, referring to fig. 11, the second waveguide cladding layer preparation and planarization of the second waveguide structure 9 includes:
depositing the second waveguide cladding based on a CVD process;
And carrying out planarization treatment through a chemical mechanical polishing process to reduce the thickness of the second waveguide cladding above the second waveguide structure 9 to a second preset thickness.
In specific implementation, the second waveguide cladding layer may be configured as a SiO 2 film, a SiO 2 film is deposited by CVD, and a planarization treatment is performed by CMP until the thickness of the SiO 2 film above the second waveguide structure 9 reaches a second preset thickness h2, and h1+h2<150nm is satisfied, where h1 is a first preset thickness of the first waveguide cladding layer above the first waveguide structure 4 after the first waveguide cladding layer is planarized.
In one embodiment, the sum of the first predetermined thickness and the second predetermined thickness is less than 150nm.
In one embodiment, for the formation of the second pad hole 10, referring to fig. 12, the second waveguide cladding layer and the buried oxide layer 8 are dry etched onto the Si substrate, and in this step, the second pad hole 10 is designed to be indirectly aligned with the pad window on the first waveguide wafer according to the W2W bonding alignment relationship.
In the embodiment, the second waveguide wafer is processed, and the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through the layout design according to the W2W bonding alignment relationship, so that the front process processing such as photoetching and film preparation is not needed after W2W, and the compatibility of a W2W heterogeneous integration mode and a CMOS process is improved.
The following describes the processing procedure of the LN-Si Nx composite waveguide in detail, including the following.
In one embodiment, referring to fig. 13, bonding the first waveguide wafer to the second waveguide wafer includes:
cleaning and activating plasmas are sequentially carried out on the first waveguide wafer and the second waveguide wafer;
aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonding device;
and annealing the pre-bonding device to complete the bonding.
In particular, the bonding strength may be improved by annealing, and the temperature during annealing may be set to be less than 250 ℃, so that the second waveguide wafer and the first waveguide wafer are bonded together, and referring to fig. 13, the positions of the first pad holes 5 above the metal electrode 3 and the second pad holes 10 on both sides of the second waveguide structure 9 correspond to each other, and the second waveguide structure 9 corresponds to the first waveguide structure 4 of the bonding region.
In one embodiment, the removing the second substrate 7 includes:
The second substrate 7 is removed by grinding or chemical mechanical polishing, and the structure after the second substrate 7 is removed is shown with reference to fig. 1.
In this embodiment, compared with the D2W bonding method, in the process of removing the Si substrate of the second waveguide wafer, the risk of dropping the LN chip is reduced, and the Si substrate can be directly removed by the CMP method, so that the problems of low processing efficiency, damage to the Si Nx waveguide device, and the like caused by wet etching are avoided, and meanwhile, the process flow is simplified. In addition, compared with a D2W bonding mode, the LN chip size can be smaller, and the integration level of the optical chip is improved.
According to the embodiment of the invention, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design according to the W2W bonding alignment relation, so that the front process processing such as photoetching, film preparation and the like is not needed after W2W is realized, the compatibility of a W2W heterogeneous integration mode and a CMOS (complementary metal oxide semiconductor) process is improved, the advantage of flexibility of independent processing of the first waveguide wafer and the second waveguide wafer is fully utilized, the process structure compatibility of a bonding area and a non-bonding area is improved, and for example, the thickness of a waveguide cladding between LN-Si Nx layers of the bonding area and the thickness of a Si Nx waveguide cladding of the non-bonding area can be differentiated according to design requirements.
In addition, compared with a D2W bonding mode, the method reduces the drop risk of the LN chip in the process of removing the LN substrate, can directly remove the Si substrate by a chemical mechanical polishing mode, avoids the problems of low processing efficiency, damage of the Si Nx waveguide device and the like caused by wet etching, simplifies the process flow, and has smaller LN chip size and improves the integration level of the optical chip compared with the D2W bonding mode.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
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| CN105655417A (en) * | 2016-02-29 | 2016-06-08 | 华为技术有限公司 | Optical waveguide detector and optical module |
| CN111480236A (en) * | 2017-12-15 | 2020-07-31 | 伊文萨思粘合技术公司 | Directly bonded optoelectronic interconnects for high density integrated photonic devices |
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| CN105655417A (en) * | 2016-02-29 | 2016-06-08 | 华为技术有限公司 | Optical waveguide detector and optical module |
| CN111480236A (en) * | 2017-12-15 | 2020-07-31 | 伊文萨思粘合技术公司 | Directly bonded optoelectronic interconnects for high density integrated photonic devices |
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