CN119717973A - LDO circuit, LDO chip, LDO and electronic equipment of low dropout linear regulator - Google Patents
LDO circuit, LDO chip, LDO and electronic equipment of low dropout linear regulator Download PDFInfo
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Abstract
本发明公开了一种低压差线性稳压器LDO电路、LDO芯片、LDO及电子设备，所述电路包括：功率器件；反馈单元适于根据LDO电路的输出电压生成反馈电压；比较单元，比较单元的第一输入端适于连接参考电压，比较单元的第二输入端与反馈单元的输出端相连，比较单元的输出端与功率器件的控制端相连，适于将反馈电压与参考电压进行比较，输出比较信号，比较信号用于控制功率器件的开通或关断；负载电容和分流控制单元，负载电容和分流控制单元分别对应LDO电路的输出端设置，分流控制单元适于对通过负载电容的电流进行分流控制。该电路通过分流控制单元对通过负载电容的电流进行分流，在保持LDO性能的前提下，降低了对负载电容的电容值需求，减小了LDO电路的面积。
The present invention discloses a low-dropout linear regulator LDO circuit, an LDO chip, an LDO and an electronic device, wherein the circuit comprises: a power device; a feedback unit adapted to generate a feedback voltage according to the output voltage of the LDO circuit; a comparison unit, wherein the first input end of the comparison unit is adapted to be connected to a reference voltage, the second input end of the comparison unit is connected to the output end of the feedback unit, the output end of the comparison unit is connected to the control end of the power device, and is adapted to compare the feedback voltage with the reference voltage, and output a comparison signal, wherein the comparison signal is used to control the on or off of the power device; a load capacitor and a shunt control unit, wherein the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit is adapted to shunt control the current passing through the load capacitor. The circuit shunts the current passing through the load capacitor through the shunt control unit, and reduces the capacitance value requirement of the load capacitor and the area of the LDO circuit while maintaining the LDO performance.
Description
Technical Field
The invention relates to the technical field of electronic equipment, in particular to a low dropout linear regulator (LDO) circuit, an LDO chip, an LDO and electronic equipment.
Background
In the related art, for the design of the off-chip capacitor of the LDO, the area is mostly on the load capacitor, and in order to keep the performance of the load capacitor comparable to that of the external capacitor, an internal load capacitor with a larger capacitance value is generally placed, so as to meet the performance requirements of the power supply ripple rejection ratio, the load transient response, and the like. However, the application of an internal load capacitor with a larger capacitance value also increases the module area of the LDO.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first objective of the present invention is to provide a LDO circuit of a low dropout linear regulator, which shunts the current through a load capacitor by a shunt control unit, and reduces the capacitance requirement of the load capacitor on the premise of maintaining the performance of the LDO, thereby reducing the application area of the LDO circuit.
A second object of the present invention is to provide an LDO chip.
A third object of the present invention is to propose an LDO.
A fourth object of the present invention is to propose an electronic device.
In order to achieve the above purpose, an embodiment of the first aspect of the present invention provides a LDO circuit of a low dropout linear regulator, which comprises a power device, a feedback unit, a comparison unit, a control unit and a shunt control unit, wherein a first end of the power device is suitable for being connected with a first reference power supply, a second end of the power device is suitable for being connected with an output end of the LDO circuit, the feedback unit is connected with a second end of the power device and is suitable for generating a feedback voltage according to an output voltage of the LDO circuit, a first input end of the comparison unit is suitable for being connected with a reference voltage, a second input end of the comparison unit is connected with an output end of the feedback unit, an output end of the comparison unit is connected with a control end of the power device and is suitable for comparing the feedback voltage with the reference voltage, the comparison signal is used for controlling the power device to be turned on or off, the load capacitor and the shunt control unit are respectively arranged corresponding to the output ends of the LDO circuit, and the shunt control unit is suitable for carrying out shunt control on current passing through the load capacitor.
According to the LDO circuit of the low dropout linear regulator, the first end of the power device is suitable for being connected with a first reference power supply, the second end of the power device is suitable for being connected with the output end of the LDO circuit, the feedback unit is connected with the second end of the power device, the feedback unit generates feedback voltage according to the output voltage of the LDO circuit, the first input end of the comparison unit is suitable for being connected with the reference voltage, the second input end of the comparison unit is connected with the output end of the feedback unit, the output end of the comparison unit is connected with the control end of the power device, the comparison unit compares the feedback voltage with the reference voltage and outputs a comparison signal, the comparison signal is used for controlling the on or off of the power device, the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit carries out shunt control on current passing through the load capacitor. Therefore, the circuit shunts the current passing through the load capacitor through the shunt control unit, and reduces the capacitance value requirement on the load capacitor on the premise of maintaining the performance of the LDO, thereby reducing the application area of the LDO circuit.
In addition, the LDO circuit of the low dropout linear regulator according to the above embodiment of the present invention may further have the following additional technical features:
according to one embodiment of the invention, the shunt control unit comprises a voltage dividing resistor, a V-I converter and a current mirror, wherein one end of the voltage dividing resistor is connected with the output end of the LDO circuit, the other end of the voltage dividing resistor is connected with one end of a load capacitor, the other end of the load capacitor is grounded, the V-I converter is suitable for converting the pressure difference on the voltage dividing resistor into shunt current, and the current mirror is suitable for mirroring the shunt current to pump the shunt current away.
According to one embodiment of the invention, the current mirror ratio of the current mirror is adjustable.
According to one embodiment of the invention, the V-I converter comprises a first comparator, a pull-up resistor and a first switching tube, wherein the negative input end of the first comparator is connected with one end of a voltage dividing resistor, the positive input end of the first comparator is connected with the other end of the voltage dividing resistor, one end of the pull-up resistor is suitable for being connected with a second reference power supply, the control end of the first switching tube is connected with the output end of the first comparator, the first end of the first switching tube is connected with the other end of the pull-up resistor, and the second end of the first switching tube is suitable for providing control current for a current mirror.
According to one embodiment of the present invention, the first switching tube is a PMOS (P-Metal-Oxide-Semiconductor) tube.
According to one embodiment of the invention, the current mirror comprises a second switching tube, a third switching tube and a third switching tube, wherein the first end of the second switching tube is connected with the other end of the voltage dividing resistor, the second end of the second switching tube is grounded, the control end of the third switching tube is connected with the control end of the second switching tube, the first end of the third switching tube is respectively connected with the control end of the third switching tube and the second end of the first switching tube, and the second end of the third switching tube is grounded.
According to one embodiment of the invention, the number of second switching tubes is determined according to the current mirror ratio of the current mirror.
According to one embodiment of the present invention, the second switching tube and the third switching tube are NMOS (N-Metal-Oxide-Semiconductor) tubes, respectively.
According to one embodiment of the invention, the power device is an NMOS transistor.
According to an embodiment of the invention, the comparing unit comprises a second comparator, the positive input of which is adapted to be connected to the reference voltage, the negative input of which is connected to the output of the feedback unit, and the output of which is connected to the control terminal of the power device.
According to one embodiment of the invention, the feedback unit comprises a first resistor, one end of the first resistor is connected with the second end of the power device, one end of the second resistor is connected with the other end of the first resistor and is provided with a first node, the other end of the second resistor is grounded, and the first node serves as an output end of the feedback unit.
In order to achieve the above objective, an embodiment of the present invention provides an LDO chip, which includes the LDO circuit described above.
According to the LDO chip provided by the embodiment of the invention, based on the LDO circuit of the low dropout linear regulator, the chip area of the LDO is reduced on the premise of keeping the performance of the LDO chip.
In order to achieve the above objective, an embodiment of the present invention provides an LDO chip including the above LDO chip.
According to the LDO of the embodiment of the invention, based on the LDO chip, the area of the LDO is reduced and the application cost is reduced on the premise of maintaining the performance of the LDO.
To achieve the above objective, an embodiment of a fourth aspect of the present invention provides an electronic device, including the LDO described above.
According to the electronic equipment provided by the embodiment of the invention, based on the LDO, the area of the electronic equipment is reduced and the equipment cost is reduced on the premise of keeping the performance of the electronic equipment.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram illustrating the connection of LDO circuits of a LDO according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a capacitor multiplier according to one embodiment of the present invention;
FIG. 3 is a circuit diagram of a LDO circuit of a low dropout linear regulator in the related art;
FIG. 4 is a circuit diagram of a LDO circuit of a low dropout linear regulator according to one embodiment of the present invention;
FIG. 5 is a schematic diagram of a startup simulation according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a simulation of a ripple rejection ratio of a power supply according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a load transient response simulation in accordance with one embodiment of the invention;
FIG. 8 is a block diagram of an LDO chip according to an embodiment of the present invention;
FIG. 9 is a block schematic diagram of an LDO according to an embodiment of the present invention;
fig. 10 is a block schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The low dropout linear regulator LDO circuit, LDO chip, LDO and electronic device according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of connection of an LDO circuit of a low dropout linear regulator according to an embodiment of the invention.
As shown in fig. 1, the LDO circuit of the low dropout linear regulator according to the embodiment of the present invention may include a power device Q, a feedback unit 10, a comparison unit 20, a load capacitor C, and a shunt control unit 30.
The first end of the power device Q is adapted to be connected to the first reference power VCC1, and the second end of the power device Q is adapted to be connected to the output end of the LDO circuit. The feedback unit 10 is connected to the second terminal of the power device Q, and the feedback unit 10 is adapted to generate a feedback voltage V0 according to the output voltage Vout of the LDO circuit. The first input end of the comparing unit 20 is suitable for being connected with the reference voltage Vref, the second input end of the comparing unit 20 is connected with the output end of the feedback unit 10, the output end of the comparing unit 20 is connected with the control end of the power device Q, the comparing unit 20 is suitable for comparing the feedback voltage V0 with the reference voltage Vref and outputting a comparison signal, and the comparison signal is used for controlling the power device Q to be turned on or off. The load capacitor C and the shunt control unit 30 are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit 30 is suitable for carrying out shunt control on the current passing through the load capacitor C.
Specifically, the feedback unit 10 collects the output voltage Vout at the output terminal of the LDO circuit, and generates the feedback voltage V0 and sends the feedback voltage V0 to the comparison unit 20. The comparison unit 20 compares the feedback voltage V0 with the reference voltage Vref, and the comparison unit 20 generates a corresponding comparison signal according to the comparison result to control the power device Q to be turned on or off. If the feedback voltage V0 is greater than the reference voltage Vref, the comparison signal output by the comparison unit 20 may control the power device Q to be turned on, and the first reference power VCC1 is connected to the output terminal of the LDO circuit through the turned-on power device Q, and at this time, the output voltage Vout of the LDO circuit is the first reference power VCC1 minus the on voltage of the power device Q.
When the power device Q is turned on, the output voltage Vout of the LDO circuit charges the load capacitor C, and the current flowing into the load capacitor C is shunt-controlled by the shunt control unit 30. Referring to fig. 2, a resistor R is connected in series to the upper end of the load capacitor C, wherein the sink current means that the resistor R receives a current, the pump current means that a part of the current is pumped from the lower side of the resistor R, and the pumped part of the current, i.e., the pump current, does not pass through the load capacitor C, so as to satisfy the following formula:
Q=CV=IT
C=IT/V
wherein Q is the charge amount of the load capacitor, T is the charge-discharge time of the load capacitor, I is the current passing through the load capacitor, V is the voltage difference between two ends of the load capacitor, and C is the capacitance value of the load capacitor.
As can be seen from the above formula, if the current through the load capacitor C becomes smaller, the corresponding capacitance value becomes smaller. Assuming that the sink current is 5x and the pump current is not 4x, the current passing through the load capacitor C can be reduced by 5 times as long as x is the capacitance value of the corresponding load capacitor C. Meanwhile, the current flowing into the resistor R still remains unchanged, so that the effective capacitance value corresponding to the output of the LDO circuit also remains unchanged.
Therefore, the present application is based on the concept of the capacitor multiplier shown in fig. 2, and the current flowing into the load capacitor C is controlled by the shunt control unit 30, so as to achieve the effect of reducing the current flowing into the load capacitor C, and reduce the capacitance requirement of the load capacitor C under the condition of ensuring that the effective capacitance corresponding to the output of the LDO circuit is unchanged. That is, on the premise of ensuring the working performance of the LDO circuit, compared with fig. 3, the application can adopt the load capacitor C with smaller capacitance value to reduce the area of the LDO circuit, and further, if adopting the load capacitor C with the same capacitance value, the application can make the performance of the LDO circuit better, such as the power supply ripple rejection ratio and the load transient response.
It should be noted that the above power device Q may be applied according to practical situations, for example, in one embodiment of the present invention, the power device Q is an NMOS transistor. It is understood that the power device Q may be a PMOS transistor, which is not limited herein.
In addition, the feedback unit 10 generates the feedback voltage V0 based on the output voltage Vout, specifically, the voltage dividing circuit may be used to divide the received output voltage Vout in real time to obtain the divided voltage as the feedback voltage V0, or may output the corresponding feedback voltage V0 according to the output voltage Vout after the output voltage Vout exceeds the preset voltage threshold or is less than the preset voltage threshold, which is not limited herein.
The LDO circuit of the low dropout linear regulator of the present application is illustrated below by taking the power device Q without NMOS transistor as an example.
Referring to fig. 4, in one embodiment of the present invention, the feedback unit 10 includes a first resistor R1, one end of the first resistor R1 is connected to the second end of the power device Q, and a second resistor R2, one end of the second resistor R2 is connected to the other end of the first resistor R1, and has a first node a, the other end of the second resistor R2 is grounded, and the first node a is used as an output end of the feedback unit 10.
That is, the output voltage Vout is divided by a voltage dividing circuit constituted by the first resistor R1 and the second resistor R2, and the divided voltage is output as the feedback voltage V0 to the comparing unit 20 through the first node a. Wherein the feedback voltage V0 satisfies the formulaWherein, R1 is the resistance value of the first resistor R2, R2 is the resistance value of the second resistor R2, and Vout is the output voltage of the LDO circuit.
In one embodiment of the present invention, the comparing unit 20 includes a second comparator A2, the positive input terminal of the second comparator A2 is adapted to be connected to the reference voltage Vref, the negative input terminal of the second comparator A2 is connected to the output terminal of the feedback unit 10, and the output terminal of the second comparator A2 is connected to the control terminal of the power device Q.
In the case that the power device Q is an NMOS transistor, the turn-on voltage is a voltage difference between the gate g and the drain d of the NMOS transistor.
Specifically, in the comparing unit 20, the feedback voltage V0 is compared with the reference voltage Vref, and then amplified in the second comparator A2, and then a comparison signal is outputted to control the gate g of the NMOS transistor, so as to control the on or off of the NMOS transistor.
In one embodiment of the present invention, the shunt control unit 30 includes a voltage dividing resistor R3 and a V-I converter 31 and a current mirror 32. One end of the voltage dividing resistor R3 is connected with the output end of the LDO circuit, the other end of the voltage dividing resistor R3 is connected with one end of the load capacitor C, and the other end of the load capacitor C is grounded. The V-I converter 31 is adapted to convert the voltage difference across the voltage dividing resistor R3 into a divided current. The current mirror 32 is adapted to mirror the shunt current to pump away the shunt current.
Specifically, as shown in fig. 2, when the LDO circuit is started, the load capacitor C is charged, and since the voltage difference is generated between the two poles of the voltage dividing resistor R3 when the current passes through the voltage dividing resistor R3, the voltage difference of the voltage dividing resistor R3 forms a split current through the V-I converter 31, and the split current is mirrored through the current mirror 32 and a part of the current is drawn, so as to form a drawn current shown in fig. 2, so as to reduce the current flowing through the load capacitor C.
In one embodiment of the invention, the current mirror ratio of current mirror 32 is adjustable. For example, the current mirror 32 may be adjusted by a register to vary the magnitude of the current drawn to accommodate load capacitances of different capacitance values.
In one embodiment of the present invention, the V-I converter 31 includes a first comparator A1, wherein a negative input end of the first comparator A1 is connected to one end of a voltage dividing resistor R3, a positive input end of the first comparator A1 is connected to the other end of the voltage dividing resistor R3, a pull-up resistor R4, one end of the pull-up resistor R4 is suitable for being connected to a second reference power supply VCC2, a first switching tube Q1, a control end of the first switching tube Q1 is connected to an output end of the first comparator A1, a first end of the first switching tube Q1 is connected to the other end of the pull-up resistor R4, and a second end of the first switching tube Q1 is suitable for providing a control current to a current mirror 32. The second reference power VCC2 may be set at the same potential as the first reference power VCC1, i.e., the second reference power VCC2 and the first reference power VCC are the same reference power.
In one embodiment of the present invention, the first switching tube Q1 is a PMOS tube.
Specifically, when the LDO circuit starts to operate, the output terminal of the LDO circuit outputs the voltage Vout, the voltage dividing resistor R3 charges the load capacitor C, the voltage difference generated by the two poles of the voltage dividing resistor R3 is positive, that is, the voltage at the upper end (the end far away from the load capacitor C) of the voltage dividing resistor R3 is greater than the voltage at the lower end (the end connected to the load capacitor C) of the voltage dividing resistor R3, that is, the voltage at the positive input terminal of the first comparator A1 is less than the voltage at the negative input terminal, at this time, the first comparator A1 generates a comparison signal based on the comparison result and controls the PMOS transistor, that is, the first switching transistor Q1 to be turned on, and the second reference power VCC2 and the pull-up resistor R4 are connected to the current mirror 32 through the turned on first switching transistor Q1 to provide the control current to the current mirror 32.
In the process of supplying the control current to the current mirror 32, if the voltage difference generated between the two poles of the voltage dividing resistor R3 is large, that is, the current flowing through the voltage dividing resistor R3 is large, at this time, the voltage difference between the positive input end and the negative input end of the first comparator A1 is large, the output signal of the first comparator A1 becomes strong, and the on voltage of the PMOS tube, that is, the voltage drop becomes small, the output control current increases.
In one embodiment of the invention, the current mirror 32 comprises a second switching tube Q2, a third switching tube Q3, a control end of the third switching tube Q3 and a control end of the third switching tube Q2, wherein a first end of the second switching tube Q2 is connected with the other end of the voltage dividing resistor R3, a second end of the second switching tube Q2 is grounded, a first end of the third switching tube Q3 is connected with the control end of the third switching tube Q3 and a second end of the first switching tube Q2, and a second end of the third switching tube Q3 is grounded.
In one embodiment of the invention, the number of second switching transistors Q2 is determined according to the current mirror ratio of current mirror 32. The proportion of the current is controlled by adjusting the proportion of the current mirror image, for example, 4:5,9:10 and the like, so that the proportion of the current flowing into the load capacitor is adjusted, and the capacitance value requirement of the load capacitor is further adjusted. Thus, the reduced area of the LDO circuit is not limited, and can be achieved by adjusting the current mirror ratio.
In one embodiment of the present invention, the second switching transistor Q2 and the third switching transistor Q3 are NMOS transistors, respectively.
Specifically, the control current output by the V-I converter 31 flows into the second switching tube Q2 and is mirrored to the third switching tube Q3 through mirroring, so that the current flowing through the third switching tube Q3 is the mirrored current of the control current and changes along with the change of the control current, and the current flowing through the third switching tube Q3 is the pumping current, thereby realizing the shunt control of the load capacitor C.
Further, the circuit performance of the present application will be described below with simulation output for three embodiments based on simulation results. In the first embodiment, the capacitance value of the load capacitor C is 50pF as shown in fig. 3, and the large capacitance occupies about 70 percent of the whole circuit area, in the second embodiment, the capacitance value of the load capacitor C is 10pF as shown in fig. 3, and the circuit area is the smallest, in the third embodiment, the capacitance value of the load capacitor C is 10pF as shown in fig. 4, and the circuit is designed based on a capacitance multiplier, and the circuit area is slightly larger than that of the second embodiment, but is much smaller than that of the first embodiment.
The magnitude of the effective capacitance of the LDO circuit affects the transient current I when the LDO circuit is started. As shown in fig. 5, the simulated waveform of the starting current of the first embodiment is close to or even coincides with that of the third embodiment, and the starting current of the first embodiment and the third embodiment is about 5 times greater than that of the second embodiment on the premise that the starting voltage is the same as that of the second embodiment.
The magnitude of the effective capacitance of the LDO circuit affects the power supply ripple rejection ratio at high frequencies. The comparative simulation of the power ripple suppression ratio of the three embodiments is shown in fig. 6, wherein the simulated waveform diagrams of the first embodiment and the third embodiment are close to or even coincide, and take the power ripple suppression ratio at 10MHz as an example, the first embodiment and the third embodiment are smaller than the second embodiment by about 10 dB. In addition, the effective capacitance values of the first embodiment and the third embodiment are also the same.
FIG. 7 is a comparative simulation diagram of load transient response, wherein when the load current outputted by the LDO circuit is changed, the output voltage of the LDO circuit has ripple, and the larger the effective capacitance value is, the smaller the ripple is, and the better the output voltage quality of the LDO circuit is. Fig. 7 illustrates a load current varying in the range of 0-12mA, in which the simulated waveforms of the first embodiment and the third embodiment are close to or even coincide, and it can be seen from the ripple simulation result that the first embodiment and the third embodiment shake at 20mV, and the second embodiment has a ripple of about 70mV because of the small effective capacitance value.
Therefore, through the simulation verification of the three aspects of fig. 5, 6 and 7, based on the simulation results of the first embodiment and the third embodiment, the low dropout linear regulator LDO circuit provided by the application can keep the effective capacitance and performance, and simultaneously, the capacitance of the load capacitor is made smaller, so that the circuit area is saved. Based on the simulation results of the second embodiment and the third embodiment, it can be seen that the low dropout linear regulator LDO circuit provided by the application has better performance, such as lower power supply ripple rejection ratio, better load transient response and smaller ripple, under the condition of maintaining the same capacitance value.
According to the LDO circuit of the low dropout linear regulator, on the premise of reducing the occupied area of the load capacitor C, the current flowing into the load capacitor C is subjected to shunt control by the shunt control unit 30, so that the characteristics of the same large capacitor can be kept, and the important indexes of the LDO, namely the load stability, the power supply ripple rejection ratio and the load transient response, of the three off-chip capacitor LDOs are kept.
In summary, according to the LDO circuit of the low dropout linear regulator of the embodiment of the application, the first end of the power device is adapted to be connected to the first reference power supply, the second end of the power device is adapted to be connected to the output end of the LDO circuit, the feedback unit is connected to the second end of the power device, the feedback unit generates a feedback voltage according to the output voltage of the LDO circuit, the first input end of the comparison unit is adapted to be connected to the reference voltage, the second input end of the comparison unit is connected to the output end of the feedback unit, the output end of the comparison unit is connected to the control end of the power device, the comparison unit compares the feedback voltage with the reference voltage and outputs a comparison signal, wherein the comparison signal is used to control the turn-on or turn-off of the power device, the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit performs shunt control on the current passing through the load capacitor. Therefore, the circuit shunts the current passing through the load capacitor through the shunt control unit, and reduces the capacitance value requirement on the load capacitor on the premise of maintaining the performance of the LDO, thereby reducing the application area of the LDO circuit. In addition, the technical scheme provided by the application not only can reduce the size of the capacitance area, but also can achieve better LDO performance effects including power supply ripple rejection ratio and load transient response under the condition of keeping the capacitance area unchanged.
Corresponding to the embodiment, the invention also provides an LDO chip.
As shown in fig. 8, the LDO chip 100 according to an embodiment of the invention includes the LDO circuit 110 described above.
According to the LDO chip provided by the embodiment of the invention, based on the LDO circuit of the low dropout linear regulator, the chip area of the LDO is reduced on the premise of keeping the performance of the LDO chip.
Corresponding to the embodiment, the invention also provides an LDO.
As shown in fig. 9, the LDO200 according to an embodiment of the present invention includes the LDO chip 100 described above.
According to the LDO of the embodiment of the invention, based on the LDO chip, the area of the LDO is reduced and the application cost is reduced on the premise of maintaining the performance of the LDO.
Corresponding to the embodiment, the invention also provides electronic equipment.
As shown in fig. 10, the electronic device 300 according to the embodiment of the present invention includes the LDO200 described above. The electronic device 300 is an electric device, and the LDO200 may be suitable for an electric field scenario of a digital circuit and a low-voltage analog circuit in the electric device, and may specifically perform circuit arrangement according to practical situations, which is not limited herein.
According to the electronic equipment provided by the embodiment of the invention, based on the LDO, the area of the electronic equipment is reduced and the equipment cost is reduced on the premise of keeping the performance of the electronic equipment.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed, mechanically connected, electrically connected, directly connected, indirectly connected through an intervening medium, or in communication between two elements or in an interaction relationship between two elements, unless otherwise explicitly specified. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (14)
1. A low dropout linear regulator LDO circuit, comprising:
the first end of the power device is suitable for being connected with a first reference power supply, and the second end of the power device is suitable for being connected with the output end of the LDO circuit;
the feedback unit is connected with the second end of the power device and is suitable for generating feedback voltage according to the output voltage of the LDO circuit;
the first input end of the comparison unit is suitable for being connected with a reference voltage, the second input end of the comparison unit is connected with the output end of the feedback unit, the output end of the comparison unit is connected with the control end of the power device and is suitable for comparing the feedback voltage with the reference voltage and outputting a comparison signal, and the comparison signal is used for controlling the power device to be turned on or turned off;
The LDO circuit comprises a load capacitor and a shunt control unit, wherein the load capacitor and the shunt control unit are respectively arranged corresponding to the output end of the LDO circuit, and the shunt control unit is suitable for carrying out shunt control on current passing through the load capacitor.
2. The LDO circuit of claim 1, wherein the shunt control unit comprises:
One end of the divider resistor is connected with the output end of the LDO circuit, the other end of the divider resistor is connected with one end of the load capacitor, and the other end of the load capacitor is grounded;
a V-I converter adapted to convert a voltage difference across the voltage dividing resistor into a divided current;
and a current mirror adapted to mirror the shunt current to pump the shunt current away.
3. The LDO circuit of claim 2, wherein a current mirror ratio of the current mirror is adjustable.
4. The LDO circuit of claim 2, wherein the V-I converter comprises:
the negative input end of the first comparator is connected with one end of the voltage dividing resistor, and the positive input end of the first comparator is connected with the other end of the voltage dividing resistor;
One end of the pull-up resistor is suitable for being connected with a second reference power supply;
The control end of the first switching tube is connected with the output end of the first comparator, the first end of the first switching tube is connected with the other end of the pull-up resistor, and the second end of the first switching tube is suitable for providing control current for the current mirror.
5. The LDO circuit of claim 4, wherein the first switching tube is a PMOS tube.
6. The LDO circuit of claim 4, wherein the current mirror comprises:
The first end of the second switching tube is connected with the other end of the voltage dividing resistor, and the second end of the second switching tube is grounded;
The control end of the third switching tube is connected with the control end of the second switching tube, the first end of the third switching tube is respectively connected with the control end of the third switching tube and the second end of the first switching tube, and the second end of the third switching tube is grounded.
7. The LDO circuit of claim 6, wherein the number of second switching transistors is determined based on a current mirror ratio of the current mirror.
8. The LDO circuit of claim 6, wherein the second and third switching transistors are each NMOS transistors.
9. The LDO circuit of any of claims 1-8, wherein the power device is an NMOS transistor.
10. The LDO circuit of claim 9, wherein the comparing unit comprises a second comparator, a positive input of the second comparator being adapted to be connected to the reference voltage, a negative input of the second comparator being connected to an output of the feedback unit, an output of the second comparator being connected to a control terminal of the power device.
11. The LDO circuit of any of claims 1-8, wherein the feedback unit comprises:
one end of the first resistor is connected with the second end of the power device;
And one end of the second resistor is connected with the other end of the first resistor and is provided with a first node, the other end of the second resistor is grounded, and the first node is used as the output end of the feedback unit.
12. LDO chip, characterized by comprising an LDO circuit according to any of claims 1-11.
13. LDO chip according to claim 12, characterized in that it comprises an LDO chip.
14. An electronic device comprising the LDO of claim 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311273078.6A CN119717973A (en) | 2023-09-27 | 2023-09-27 | LDO circuit, LDO chip, LDO and electronic equipment of low dropout linear regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311273078.6A CN119717973A (en) | 2023-09-27 | 2023-09-27 | LDO circuit, LDO chip, LDO and electronic equipment of low dropout linear regulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119717973A true CN119717973A (en) | 2025-03-28 |
Family
ID=95075581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311273078.6A Pending CN119717973A (en) | 2023-09-27 | 2023-09-27 | LDO circuit, LDO chip, LDO and electronic equipment of low dropout linear regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119717973A (en) |
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2023
- 2023-09-27 CN CN202311273078.6A patent/CN119717973A/en active Pending
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