CN119673924A

CN119673924A - Semiconductor structure and method of forming the same

Info

Publication number: CN119673924A
Application number: CN202311212634.9A
Authority: CN
Inventors: 尹悦; 神兆旭; 吕晶晶
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2023-09-19
Filing date: 2023-09-19
Publication date: 2025-03-21

Abstract

A semiconductor structure and a method for forming the same, the semiconductor structure comprising a substrate; a first electrode layer located on the substrate, an electrode protrusion formed on the first electrode layer; a first dielectric layer covering the top and sidewalls of the electrode protrusion and the first electrode layer on the side of the electrode protrusion; a second electrode layer covering the first dielectric layer, a first opening of the first dielectric layer exposing the top of the electrode protrusion formed in the second electrode layer; a second dielectric layer covering the second electrode layer and the first dielectric layer exposed by the first opening; a third electrode layer covering the second dielectric layer, a second opening exposing the top of the second dielectric layer formed in the third electrode layer, the second opening and the first opening having projections on the substrate at different positions; a first through-hole interconnection structure at the first opening, the first electrode layer and the third electrode layer being electrically connected via the first through-hole interconnection structure; a second through-hole interconnection structure at the second opening, the second electrode layer being electrically connected to the second through-hole interconnection structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced a rapid growth. Technological advances in materials and design in the integrated circuit industry have produced one generation of yet another integrated circuit. Each generation has smaller and more complex circuitry than the previous generation. These advances, however, increase the complexity of processing and manufacturing integrated circuits and similar developments in integrated circuit processing and manufacturing are needed to achieve these advances. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has gradually increased, while the geometry (i.e., the smallest component that can be manufactured by a manufacturing process) has gradually decreased.

One type of capacitor is a metal-insulator-metal (Metal Insulator Metal, MIM) capacitor, commonly used in mixed signal devices and logic devices such as embedded memories and radio frequency devices, etc. MIM capacitors are commonly used to store charge in a variety of semiconductor devices. In order to meet the performance requirements of the devices, the capacitance density of MIM capacitors is also increasing.

However, the equivalent capacitance density of the MIM capacitor still needs to be improved.

Disclosure of Invention

The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the semiconductor structure.

In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a first electrode layer, a first dielectric layer, a second electrode layer, a first through hole interconnection structure, a second dielectric layer, a third electrode layer, a second through hole interconnection structure, a first through hole interconnection structure and a second through hole interconnection structure, wherein the first electrode layer is positioned on the substrate, the electrode convex part is formed on the first electrode layer, the first dielectric layer is covered on the top and the side wall of the electrode convex part, and the first electrode layer is covered on the side wall of the electrode convex part, the second electrode layer is covered on the first electrode layer, the first opening is covered on the side wall of the electrode convex part, the first dielectric layer is covered on the first electrode layer, the first dielectric layer is covered on the second electrode layer, the first through hole interconnection structure is positioned in the second electrode layer, the first dielectric layer is exposed on the top of the electrode convex part, the second dielectric layer is covered on the second electrode layer, the third electrode layer is covered on the second dielectric layer, the second opening is exposed on the top of the second dielectric layer, the second electrode layer is exposed on the top of the second dielectric layer, the second opening is positioned at different positions, the projection of the second opening on the substrate, the first electrode layer is positioned at different positions, the first through hole interconnection structure is positioned at the first position, the first through hole interconnection structure is exposed through the second electrode layer, the second electrode layer through the first through hole interconnection structure, the second electrode layer and the second electrode layer is connected with the first through the first electrode layer.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a first electrode layer on the substrate, forming an electrode convex part on the first electrode layer, forming a first dielectric layer which covers the top and the side wall of the electrode convex part and the first electrode layer at the side part of the electrode convex part, forming a second electrode layer which covers the first dielectric layer, forming a first opening in the second electrode layer, the first opening exposing the first dielectric layer at the top of the electrode convex part, forming a second dielectric layer which covers the second electrode layer, the second dielectric layer also covers the first dielectric layer exposed by the first opening, forming a third electrode layer which covers the second dielectric layer, forming a second opening which exposes the top of the second dielectric layer in the third electrode layer, wherein the projection of the second opening on the substrate and the projection of the first opening on the substrate are positioned at different positions, forming a second dielectric layer penetrating through the third electrode layer, the second electrode layer and the second dielectric layer, and the second interconnection structure at the position of the first electrode layer, and the second interconnection structure at the position of the second electrode layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

The semiconductor structure provided by the embodiment of the invention comprises the first electrode layer with the electrode convex part; the first through hole interconnection structure is positioned at the position of the first opening and penetrates through the third electrode layer, the second dielectric layer and the first dielectric layer, the first electrode layer and the third electrode layer are electrically connected through the first through hole interconnection structure, and a second via interconnection structure located at a position of the second opening and penetrating through the second dielectric layer, wherein the second electrode layer is electrically connected with the second via interconnection structure; because the electrode convex part is formed on the first electrode layer, the vertical distance between the first electrode layer positioned at the top of the electrode convex part and the third electrode layer is smaller, and accordingly, the distance between the first electrode layer and the third electrode layer which are respectively and electrically connected with the first through hole interconnection structure is reduced, namely, the height of the first through hole interconnection structure is reduced, so that the second through hole interconnection structure does not need to penetrate through the first electrode layer, an opening for forming the second through hole interconnection structure is not required to be reserved in the first electrode layer, namely, the area of the first electrode layer is increased, the opposite areas of the first electrode layer and the second electrode layer are correspondingly increased, and therefore, the capacitance density of metal-insulator-metal (MIM) capacitors formed by the first electrode layer, the second electrode layer and the third electrode layer is increased, and further, the performance of the semiconductor structure is improved.

In the method for forming the semiconductor structure provided by the embodiment of the invention, the electrode convex part is formed on the first electrode layer, the first through hole interconnection structure penetrating through the third electrode layer, the second dielectric layer and the first dielectric layer is formed at the position of the first opening, the first electrode layer and the third electrode layer are electrically connected through the first through hole interconnection structure, the second through hole interconnection structure penetrating through the second dielectric layer is formed at the position of the second opening, the second electrode layer is electrically connected with the second through hole interconnection structure, and the electrode convex part is formed on the first electrode layer, so that the vertical distance between the first electrode layer and the third electrode layer at the top of the electrode convex part is smaller, the first electrode layer and the third electrode layer which are respectively electrically connected with the first through hole interconnection structure are correspondingly reduced, namely the height of the first through hole interconnection structure is reduced, the second through hole interconnection structure does not need to penetrate through the second electrode layer, the second electrode layer is not required to be formed, the second electrode layer is also enlarged, namely the capacitance of the second electrode layer is enlarged, the corresponding to the second electrode layer is enlarged, the capacitance of the second electrode is enlarged, the area of the second electrode is enlarged, and the corresponding capacitance of the second electrode structure is enlarged, and the area of the second electrode structure is enlarged, and the corresponding capacitance of the second electrode structure is enlarged, and the capacitance area is enlarged.

Drawings

Fig. 1 to 3 are schematic structural views of a semiconductor structure;

FIGS. 4-8 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;

fig. 9 to 32 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

Currently, the performance of semiconductor structures is still to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a semiconductor structure.

Fig. 1 to 3 are schematic structural views of a semiconductor structure, wherein fig. 1 is a top view, fig. 2 is a sectional view of fig. 1 at a BB1 position, and fig. 3 is a sectional view of fig. 1 at an AA1 position.

Referring to fig. 1 to 3, the semiconductor structure includes a substrate 10, the substrate 10 including a first location 11 and a second location 12; the first electrode layer 13 is located on the substrate 10, a first opening (not labeled) is formed in the first electrode layer 13 above the second positioning 12, the first opening exposes the top of the substrate 10, the first dielectric layer 14 is covered on the first electrode layer 13 and is covered on the substrate 10 exposed by the first opening, the second electrode layer 15 is covered on the first dielectric layer 14, a second opening (not labeled) exposing the top of the first dielectric layer 14 is formed in the second electrode layer 15 above the first positioning 11, the second dielectric layer 16 is covered on the second electrode layer 15 and is covered on the first dielectric layer 14 exposed by the second opening, the third electrode layer 17 is covered on the second dielectric layer 16, a third opening (not labeled) above the first opening is also formed in the third electrode layer 17 above the second positioning 12, the third opening is exposed by the third electrode layer 15, the second electrode layer 16 is exposed by the third opening, the second electrode layer 21 is connected with the second electrode layer 16 and the second electrode layer 17, the second electrode layer 21 is connected with the first electrode layer 14, the second electrode layer 17 and the top dielectric layer 14, the second electrode layer 21 is connected with the second electrode layer 17, the first electrode layer 21 and the top dielectric layer 14, the second interconnection structure layer 17 is connected with the first electrode layer 14, the second interconnection structure layer 22.

It has been found that in order to make the first via interconnection structure 21 contact only the first electrode layer 13 and the third electrode layer 17, but not the second electrode layer 15, the second via interconnection structure 22 contacts only the second electrode layer 15, but not the first electrode layer 13 and the third electrode layer 17, it is necessary to form a first opening in the first electrode layer 13 above the second location 12 exposing the top of the substrate 10, a third opening in the third electrode layer 17 above the second location 12 exposing the top of the second dielectric layer 16, and a second opening in the second electrode layer 15 above the first location 11 exposing the top of the first dielectric layer 14, thereby reducing the facing area between adjacent first electrode layer 13 and second electrode layer 15, and between the second electrode layer 15 and the third electrode layer 17, and correspondingly reducing the density of metal-insulator-metal capacitance formed by the first electrode layer 13, the second electrode layer 15, and the third electrode layer 17, thereby affecting the performance of the semiconductor structure.

In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate; a first electrode layer on the substrate, wherein an electrode protrusion is formed on the first electrode layer; the electrode comprises an electrode protrusion, a first dielectric layer, a second electrode layer, a second dielectric layer, a third electrode layer, a first through hole interconnection structure, a second through hole interconnection structure and a second through hole interconnection structure, wherein the electrode protrusion is arranged on the electrode protrusion, the first dielectric layer covers the top and the side wall of the electrode protrusion, and covers the side wall of the electrode protrusion, the first electrode layer covers the side wall of the electrode protrusion, the second electrode layer covers the side wall of the electrode protrusion, a first opening is formed in the second electrode layer and exposes the first dielectric layer at the first opening, the second dielectric layer covers the second electrode layer and covers the first dielectric layer exposed at the first opening, a second electrode layer covers the second dielectric layer, a second opening exposing the top of the second dielectric layer is formed in the third electrode layer, the projection of the second opening on the substrate and the projection of the first opening on the substrate are located at different positions, the first through hole interconnection structure is located at the position of the first opening and penetrates through the third electrode layer, the second dielectric layer and the first electrode layer is electrically connected with the third electrode layer through the first through hole interconnection structure, and the second through hole interconnection structure is located at the second opening and the second through hole interconnection structure.

The semiconductor structure comprises a first electrode layer with an electrode convex part, a first through hole interconnection structure which is arranged at the position of the first opening and penetrates through the third electrode layer, a second dielectric layer and the first dielectric layer, the first electrode layer and the third electrode layer are electrically connected through the first through hole interconnection structure, and a second through hole interconnection structure which is arranged at the position of the second opening and penetrates through the second dielectric layer, the second electrode layer is electrically connected with the second through hole interconnection structure, and the vertical distance between the first electrode layer and the third electrode layer at the top of the electrode convex part is smaller, so that the distance between the first electrode layer and the third electrode layer which are electrically connected with the first through hole interconnection structure is correspondingly reduced, namely the height of the first through hole interconnection structure is reduced, the second through hole interconnection structure does not need to penetrate through the first electrode layer, the second electrode layer is not required to be formed, the second electrode layer is enlarged, the area of the second electrode layer is enlarged, namely the second electrode layer is enlarged, the capacitance of the second electrode structure is enlarged, and the area of the second electrode structure is enlarged, and the capacitance of the second electrode structure is enlarged, and the corresponding electrode structure is formed in the second electrode layer is enlarged, and the capacitance area of the second electrode structure is enlarged, and the capacitance of the second electrode structure is enlarged, and the area of the corresponding electrode structure is enlarged.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings.

Fig. 4-8 are schematic structural views of an embodiment of a semiconductor structure according to the present invention.

Referring to fig. 4 to 8, in this embodiment, the semiconductor structure includes a substrate 100, a first electrode layer 110 disposed on the substrate 100, an electrode protrusion 115 formed on the first electrode layer 110, a first dielectric layer 120 covering the top and the sidewall of the electrode protrusion 115 and covering the first electrode layer 110 on the side of the electrode protrusion 115, a second electrode layer 130 covering the first dielectric layer 120, a first opening 135 (as shown in fig. 7) formed in the second electrode layer 130, the first opening 135 exposing the first dielectric layer 120 on the top of the electrode protrusion 115, a second dielectric layer 140 covering the second electrode layer 130 and covering the first dielectric layer 120 exposed by the first opening 135, a third electrode layer 150 covering the second dielectric layer 140, a second opening 155 (as shown in fig. 8) formed in the third electrode layer 150 and exposing the top of the second dielectric layer 140, the second opening 155 and the second electrode layer 135 on the substrate 100, a second interconnect layer 220 at a position different from the first opening and the second electrode layer 140, and a second interconnect layer 220 at a position of the second electrode layer 150, and a position of the second interconnect layer 220 at the second interconnect structure, and a position of the second interconnect layer 220 at the second electrode layer 150.

Fig. 4 is a plan view, fig. 5 is a cross-sectional view of fig. 4 at a BB1 position, fig. 6 is a cross-sectional view of fig. 4 at an AA1 position, fig. 7 is a cross-sectional view of a second opening corresponding to fig. 5, and fig. 8 is a cross-sectional view of a first opening corresponding to fig. 6.

In fig. 7, the fourth dielectric layer and the second via interconnection structure are omitted, and in fig. 8, the second dielectric layer, the third electrode layer, the fourth dielectric layer and the first via interconnection structure are omitted for clarity of the semiconductor structure.

The substrate 100 is used to provide a process platform for forming a capacitor.

In this embodiment, the substrate 100 is used to form a MIM capacitor.

Specifically, the first electrode layer 110, the second electrode layer 130, and the third electrode layer 150 constitute a metal-insulator-metal capacitance.

In other embodiments, the substrate may also be used to form MOS (metal-oxide-semiconductor) capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, MOM (metal-oxide-metal) capacitors, and the like.

In this embodiment, the base 100 includes a substrate 101, which is a silicon substrate. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

Other structures (not shown), such as MOS transistors, resistors, inductors, dielectric layers, metal interconnect structures, etc., may also be formed on the substrate 101.

In this embodiment, the substrate 100 has an initial protrusion 105 formed thereon, the first electrode layer 110 further covers the initial protrusion 105, and a portion located on the initial protrusion 105 serves as the electrode protrusion 115.

The initial protrusion 105 is generally formed on the substrate 100, so that in the step of forming the first electrode layer 110, the first electrode layer 110 also covers the initial protrusion 105, so that the first electrode layer 110 can obtain the electrode protrusion 115 following the shape of the initial protrusion 105, that is, in the step of forming the first electrode layer 110, the electrode protrusion 115 is formed on the first electrode layer 110 without patterning the first electrode layer 110, thereby reducing the damage probability of the patterning process to the first electrode layer 110, further being beneficial to improving the quality of the first electrode layer 110, correspondingly improving the performance of the semiconductor structure, and further reducing the difficulty of forming the electrode protrusion 115.

Specifically, the base 100 includes a substrate 101 and a third dielectric layer 102 on the substrate 101, where an initial protrusion 105 is provided on top of the third dielectric layer 102.

On the one hand, the third dielectric layer 102 is used to isolate the structure (e.g., MOS transistor, etc.) already formed above the substrate 101 from the first electrode layer 110, and on the other hand, the raised initial protruding portion 105 may be formed on the third dielectric layer 102 with the remaining thickness by patterning the third dielectric layer 102, so as to reduce the complexity of the process for obtaining the initial protruding portion 105.

Moreover, patterning the third dielectric layer 102 to form the raised initial protrusions 105 on the third dielectric layer 102 with the remaining thickness is also beneficial to reducing the probability of damage to the substrate 101 and the probability of damage to other structures located between the substrate 101 and the third dielectric layer 102, thereby improving the performance of the semiconductor structure.

It should be noted that other structures (not shown), such as MOS transistors, resistors, inductors, dielectric layers, metal interconnection structures, etc., may also be formed on the substrate 101, and accordingly, other structures are located between the substrate 101 and the third dielectric layer 102.

In this embodiment, the material of the third dielectric layer 102 is silicon oxide. In other embodiments, the material of the third dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.

The width w of the initial protruding portion is preferably not too small or too large in the direction perpendicular to the side wall of the initial protruding portion 105. Since the first opening 135 is located above the initial protruding portion 105, if the width w of the initial protruding portion 105 is too small, the difficulty of forming the first opening 135 is easily increased, and accordingly, the difficulty of forming the first via interconnection structure 210 at the location of the first opening 135 is easily increased, and if the width w of the initial protruding portion 105 is too large, the occupation area of the MIM capacitor is easily increased while the number of electrode protruding portions 115 is ensured, thereby being disadvantageous in terms of process node reduction. In this embodiment, the width w of the initial protruding portion 105 is in the range of 1 micron to 5 microns along the direction perpendicular to the sidewall of the initial protruding portion 105.

The first electrode layer 110 is used as an electrode plate of the MIM capacitor.

In this embodiment, the material of the first electrode layer 110 is a conductive material. As one example, the material of the first electrode layer 110 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

The electrode convex portion 115 is formed on the first electrode layer 110, so that the vertical distance between the first electrode layer 110 and the third electrode layer 150 at the top of the electrode convex portion 115 is smaller, and accordingly, the distance between the first electrode layer 110 and the third electrode layer 150 connected in the first via interconnection structure 210 is reduced, that is, the height of the first via interconnection structure 210 is reduced, so that the second via interconnection structure 220 does not need to penetrate through the first electrode layer 110, and therefore, an opening for forming the second via interconnection structure 220 does not need to be reserved in the first electrode layer 110, that is, the area of the first electrode layer 110 is increased, and accordingly, the facing areas of the first electrode layer 110 and the second electrode layer 130 are also increased, which is beneficial to increasing the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 110, the second electrode layer 130 and the third electrode layer 150, and further improving the performance of the semiconductor structure.

In this embodiment, the electrode protrusions 115 are arranged in a matrix.

The electrode convex portions 115 are arranged in a matrix, so that the first openings 135 of the first dielectric layer 120 exposing the top of the electrode convex portions 115 are also arranged in a matrix, and accordingly, the first via interconnection structures 210 located at the positions of the first openings 135 are also arranged in a matrix, and the electrode convex portions 115 are arranged in a matrix, so that the projections of the second openings 155 on the substrate 100 are also arranged between the projections of adjacent electrode convex portions 115 on the substrate 100.

The first dielectric layer 120 serves as an insulating layer in forming the MIM capacitor for isolating the first electrode layer 110 and the second electrode layer 130.

In this embodiment, the material of the first dielectric layer 120 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. And the high-k dielectric material is selected, so that the capacitance value of the MIM capacitor is improved, and the capacitance density is correspondingly improved.

Specifically, the first dielectric layer 120 is a high-k dielectric layer formed by stacking, i.e., the first dielectric layer 120 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the first dielectric layer 120 can meet the process requirement and has better formation quality at the same time. To this end, the high-k dielectric material includes one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

In this embodiment, the first dielectric layer 120 is ZAZ layers. Wherein, ZAZ layers include a first ZrO ₂ layer, an Al ₂O₃ layer and a second ZrO ₂ layer formed in a stacked manner. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.

The second electrode layer 130 is used as an electrode plate of the MIM capacitor.

In this embodiment, the material of the second electrode layer 130 is a conductive material. As one example, the material of the second electrode layer 130 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

The second electrode layer 130 has a first opening 135 formed therein, and the first opening 135 exposes the first dielectric layer 120 on top of the electrode protrusion 115, so that a first via interconnection structure 210 is formed at the location of the first opening 135, which is in contact with only the first electrode layer 110 and the third electrode layer 150, but not the second electrode layer 130.

The ratio of the height h1 of the electrode convex portion 115 to the thickness h2 of the second electrode layer 130 at the side portion thereof in the normal direction of the substrate 100 is preferably not too small or too large. If the ratio of the height h1 of the electrode protrusion 115 to the thickness h2 of the second electrode layer 130 at the side thereof is too small or too large, the difference between the height of the first via interconnection structure 210 formed at the position of the first opening 135 and the height of the second via interconnection structure 220 formed at the position of the second opening 155 is easily caused to be too large, thereby easily increasing the difficulty of the process of forming the first via interconnection structure 210 and the second via interconnection structure 220. In this embodiment, the height h1 of the electrode protrusion 115 is 80% to 95% of the thickness h2 of the second electrode layer 130 at the side along the normal direction of the top surface of the substrate 100.

The second dielectric layer 140 serves as an insulating layer in forming the MIM capacitor for isolating the second electrode layer 130 and the third electrode layer 150.

In this embodiment, the material of the second dielectric layer 140 is a high-k dielectric material, and the reason for selecting the high-k dielectric material as the material of the second dielectric layer 140 is similar to that of the first dielectric layer 120, and therefore will not be described herein.

Specifically, the second dielectric layer 140 is a high-k dielectric layer formed by stacking, i.e., the second dielectric layer 140 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the second dielectric layer 140 can meet the process requirement and has better formation quality at the same time. To this end, the high-k dielectric material includes one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

As an example, the second dielectric layer 140 is ZAZ layers. Wherein the ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed in a stack. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.

The third electrode layer 150 is used as an electrode plate of the MIM capacitor.

In this embodiment, the material of the third electrode layer 150 is a conductive material. As one example, the material of the second electrode layer 130 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

In this embodiment, the second openings 155 are arranged in a matrix, and along a column direction of the matrix, projections of the electrode convex portions 115 on the substrate 100 and projections of the second openings 155 on the substrate 100 are alternately arranged, and along a row direction of the matrix, projections of the electrode convex portions 115 on the substrate 100 and projections of the second openings 155 on the substrate 100 are staggered. Here, the column direction and the row direction are perpendicular.

Along the column direction of the matrix, the projections of the electrode protrusions 115 on the substrate 100 and the projections of the second openings 155 on the substrate 100 are alternately arranged, and along the row direction of the matrix, the projections of the electrode protrusions 115 on the substrate 100 and the projections of the second openings 155 on the substrate 100 are staggered, that is, along the diagonal direction of the matrix, the electrode protrusions 115 and the second openings 155 are alternately arranged, so that the first via interconnection structures 210 corresponding to the electrode protrusions 115 and the second via interconnection structures 220 corresponding to the second openings 155 are alternately arranged along the diagonal direction of the matrix.

In this embodiment, the semiconductor structure further includes a fourth dielectric layer 160 covering the third electrode layer 150 and the second dielectric layer 140 exposed by the second opening 155, and the first via interconnection structure 210 and the second via interconnection structure 220 are both located in the fourth dielectric layer 160.

The fourth dielectric layer 160 is used to provide a process basis for forming the first via interconnect structure 210 and the second via interconnect structure 220, and is also used to achieve electrical isolation between the first via interconnect structure 210 and the second via interconnect structure 220.

Specifically, the material of the fourth dielectric layer 160 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The first via interconnection structure 210 is used to electrically connect the first electrode layer 110 and the third electrode layer 150, thereby loading the first electrode layer 110 and the third electrode layer 150 with a first electrical signal. The second via interconnection structure 220 is used to electrically connect the second electrode layer 130, thereby loading the second electrode layer 130 with a second electrical signal.

Because the electrode convex portion 115 is formed on the first electrode layer 110, the vertical distance between the first electrode layer 110 and the third electrode layer 150 at the top of the electrode convex portion 115 is smaller, and accordingly, the distance between the first electrode layer 110 and the third electrode layer 150, which are electrically connected with the first via interconnection structure 210, is reduced, that is, the height of the first via interconnection structure 210 is reduced, so that the second via interconnection structure 220 does not need to penetrate through the first electrode layer 110, and therefore, an opening for forming the second via interconnection structure 220 does not need to be reserved in the first electrode layer 110, that is, the area of the first electrode layer 110 is increased, and accordingly, the facing areas of the first electrode layer 110 and the second electrode layer 130 are also increased, which is beneficial to increasing the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 110, the second electrode layer 130 and the third electrode layer 150, and further improving the performance of the semiconductor structure.

It should be noted that, the first electrical signal is applied to the first electrode layer 110 and the third electrode layer 150 through the first via interconnection structure 210, and the second electrical signal is applied to the second electrode layer 130 through the second via interconnection structure 220, so that a potential difference exists between the first electrode layer 110 and the second electrode layer 130, and a potential difference exists between the second electrode layer 130 and the third electrode layer 150, so that the first electrode layer 110, the second electrode layer 130 and the third electrode layer 150 form a MIM capacitor.

Specifically, the material of the first via interconnect structure 210 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride. The material of the second via interconnect structure 220 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.

In this embodiment, the second openings 155 are arranged in a matrix, and along a column direction of the matrix, projections of the electrode convex portions 115 on the substrate 100 and projections of the second openings 155 on the substrate 100 are alternately arranged, and along a row direction of the matrix, projections of the electrode convex portions 115 on the substrate 100 and projections of the second openings 155 on the substrate 100 are staggered. Accordingly, the first via interconnect structures 210 and the second via interconnect structures 220 are alternately arranged in a direction along a diagonal line of the matrix.

The first and second via interconnection structures 210 and 220 are alternately arranged in a direction along a diagonal line of the matrix so that the comb-tooth parts of the first rewiring structure and the comb-tooth parts of the second rewiring structure are disposed to cross.

In this embodiment, the first via interconnection structure 210 is further located in the first electrode layer 110 with a first partial thickness.

The first via interconnection structure 210 is further located in the first electrode layer 110 with a first partial thickness, which is advantageous in ensuring a contact effect of the first via interconnection structure 210 with the first electrode layer 110, thereby ensuring an electrical connection performance of the first via interconnection structure 210 and the first electrode layer 110.

It should be noted that, along the normal direction of the top surface of the substrate 100, the ratio of the first portion thickness to the thickness of the first electrode layer 110 is not too small, but not too large. If the ratio is too small, it is easy to make sure that the contact effect of the first via interconnection structure 210 with the first electrode layer 110 is poor, and if the ratio is too large, it is easy to increase the probability of over-etching the first electrode layer 110, i.e., the probability of the first via interconnection structure 210 penetrating through the first electrode layer 110, thereby increasing the probability of the first via interconnection structure 210 being electrically connected with the structure thereof. In this embodiment, the first portion of the thickness is 50% to 70% of the thickness of the first electrode layer along the normal direction of the top surface of the substrate 100.

In this embodiment, the second via interconnection structure 220 is further located in the first electrode layer with the second partial thickness.

The second via interconnection structure 220 is further located in the second electrode layer 130 having the second partial thickness, which is advantageous in ensuring the contact effect of the second via interconnection structure 220 with the second electrode layer 130, thereby ensuring the electrical connection performance in the second via interconnection structure 220 and the second electrode layer 130.

It should be noted that, along the normal direction of the top surface of the substrate 100, the ratio of the second portion thickness to the thickness of the second electrode layer 130 is not too small, but not too large. If the ratio is too small, it is easy to ensure that the contact effect between the second via interconnection structure 220 and the second electrode layer 130 is poor, and if the ratio is too large, it is easy to increase the probability of over-etching the second electrode layer 130, i.e., the probability of the second via interconnection structure 220 penetrating through the second electrode layer 130, thereby increasing the probability of the second via interconnection structure 220 electrically connecting the first electrode layer 110. In this embodiment, the second portion of the thickness is 50% to 70% of the thickness of the second electrode layer 130 along the normal direction of the top surface of the substrate 100.

In the present embodiment, the semiconductor structure further includes a rewiring structure 170 located above the first via interconnection structure 210 and the second via interconnection structure 220, the rewiring structure 170 includes a first rewiring structure 171 and a second rewiring structure 172, the first rewiring structure 171 and the second rewiring structure 172 each include a comb handle portion 175 and a comb tooth portion 176 connected to the comb handle portion 175, the comb tooth portion 176 of the first rewiring structure 171 and the comb tooth portion 176 of the second rewiring structure 172 are disposed to intersect, and the first rewiring structure 171 is connected to the first via interconnection structure 210, and the second rewiring structure 172 is connected to the second via interconnection structure 220.

The rewiring structure 170 is capable of functioning as a rewiring for the first via interconnect structure 210 and the second via interconnect structure 220, and also facilitates loading a first electrical signal through the first rewiring structure 171, loading a first electrical signal through the first electrode layer 110 and the third electrode layer 150, and loading a second electrical signal through the second rewiring structure 172, loading a second electrical signal through the second electrode layer 130.

The first rewiring structure 171 and the second rewiring structure 172 each include a comb handle portion 175 and a comb tooth portion 176 connected to the comb handle portion 175, and the comb tooth portions 176 of the first rewiring structure 171 and the comb tooth portions 176 of the second rewiring structure 172 are disposed in a crossing manner, so that electrical signals can be loaded on the first via interconnection structure 210 or the second via interconnection structure 220 electrically connected with the first rewiring structure or the second via interconnection structure 220 through the comb handle portion 175 at the same time, and the areas of the first rewiring structure 171 and the second rewiring structure 172 are saved, and the area of the rewiring structure 170 is correspondingly saved, so that the process cost is reduced.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 9 to 32 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 9 to 11, a substrate 500 is provided.

Fig. 9 is a plan view, fig. 10 is a cross-sectional view of fig. 9 at a BB1 position, and fig. 11 is a cross-sectional view of fig. 9 at an AA1 position.

The substrate 500 is used to provide a process platform for forming a capacitor.

In this embodiment, the substrate 500 is used to form a MIM capacitor.

Specifically, the subsequently formed first electrode layer, second electrode layer, and third electrode layer constitute a metal-insulator-metal capacitor.

In this embodiment, the base 500 includes a substrate 501, which is a silicon substrate. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

Other structures (not shown), such as MOS transistors, resistors, inductors, dielectric layers, metal interconnect structures, etc., may also be formed on the substrate 501.

In this embodiment, in the step of providing the substrate 500, the substrate 500 is formed with an initial protrusion 505 thereon.

The initial protrusion 505 is formed on the substrate 500, so that the first electrode layer covers the initial protrusion 505 in the subsequent step of forming the first electrode layer, and the first electrode layer located on the initial protrusion 505 is used as an electrode protrusion, that is, in the step of forming the first electrode layer, the first electrode layer is not required to be patterned, so that the electrode protrusion is formed on the first electrode layer, thereby reducing the damage probability of the patterning process to the first electrode layer, further being beneficial to improving the quality of the first electrode layer, correspondingly improving the performance of the semiconductor structure, and further reducing the difficulty of forming the electrode protrusion.

Specifically, in the step of providing the base 500, the base 500 includes a substrate 501 and a third dielectric layer 502 on the substrate 501, and before forming the first electrode layer on the base 500, the third dielectric layer 502 is patterned to form a raised initial protrusion 505 on the third dielectric layer 502 of the remaining thickness.

On the one hand, the third dielectric layer 502 is used to isolate the structure (e.g., MOS transistor, etc.) already formed above the substrate 501 from the first electrode layer, and on the other hand, the process complexity of obtaining the initial protrusion 105 can be reduced by patterning the third dielectric layer 502 to form a raised initial protrusion 505 on the third dielectric layer 502 with a residual thickness.

Moreover, patterning the third dielectric layer 502 to form the raised initial protrusions 505 on the third dielectric layer 502 of the remaining thickness is also beneficial to reducing the probability of damage to the substrate 501 and the probability of damage to other structures located between the substrate 501 and the third dielectric layer 502, thereby facilitating improved performance of the semiconductor structure.

It should be noted that other structures (not shown), such as MOS transistors, resistors, inductors, dielectric layers, metal interconnection structures, etc., may also be formed on the substrate 501, and accordingly, other structures are located between the substrate 501 and the third dielectric layer 502.

In this embodiment, the material of the third dielectric layer 502 is silicon oxide. In other embodiments, the material of the third dielectric layer may be another dielectric material such as silicon nitride or silicon oxynitride.

The width W of the initial protruding portion is preferably not too small or too large in the direction perpendicular to the side wall of the initial protruding portion 505. Since the subsequent first opening is located above the initial protruding portion 505, if the width W of the initial protruding portion 505 is too small, the difficulty of forming the subsequent first opening is easily increased, and the difficulty of forming the first via interconnection structure at the position of the first opening is easily increased correspondingly, and if the width W of the initial protruding portion 505 is too large, the occupation area of the MIM capacitor is easily caused to be too large under the condition of ensuring the number of electrode protruding portions, so that the process node is not beneficial to being reduced. In this embodiment, the width W of the initial protrusion 505 is in the range of 1 micron to 5 microns along the direction perpendicular to the sidewall of the initial protrusion 505.

Referring to fig. 12 to 13, a first electrode layer 510 is formed on the substrate 500, and an electrode protrusion 515 is formed on the first electrode layer 510.

Fig. 12 is a schematic structural view of fig. 10 after forming the first electrode layer, and fig. 13 is a schematic structural view of fig. 11 after forming the first electrode layer.

The first electrode layer 510 is used as an electrode plate of the MIM capacitor.

In this embodiment, the material of the first electrode layer 510 is a conductive material. As one example, the material of the first electrode layer 510 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

The electrode protrusion 515 is formed on the first electrode layer 510, so that the vertical distance between the first electrode layer 510 located at the top of the electrode protrusion 515 and the subsequently formed third electrode layer is smaller, and accordingly, the distance between the first electrode layer 510 and the third electrode layer in the first through hole interconnection structure is reduced, that is, the height of the subsequently formed first through hole interconnection structure is reduced, so that the subsequently formed second through hole interconnection structure does not need to penetrate through the second electrode layer, an opening for forming the second through hole interconnection structure is not needed to be reserved in the first electrode layer 510, that is, the area of the first electrode layer 510 is increased, and the facing area of the first electrode layer 510 and the subsequently formed second electrode layer is correspondingly increased, so that the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 510, the second electrode layer and the third electrode layer is advantageously increased, and further, the performance of the semiconductor structure is improved.

Accordingly, in the present embodiment, in the step of forming the first electrode layer 510, the first electrode layer 510 also covers the initial protruding portion 505, and a portion located on the initial protruding portion 505 serves as the electrode protruding portion 515.

In this embodiment, in the step of forming the first electrode layer 510, the electrode protrusions 515 are arranged in a matrix.

In the step of forming the first electrode layer 510, the electrode protrusions 515 are arranged in a matrix, so that the first openings formed according to the electrode protrusions 515 in the following step are arranged in a matrix, and accordingly, the first through hole interconnection structures formed at the positions of the first openings are arranged in a matrix, and the electrode protrusions 515 are arranged in a matrix, so that the projections of the second openings on the substrate 500 are positioned between the projections of the adjacent electrode protrusions 515 on the substrate 500.

Referring to fig. 14 to 15, a first dielectric layer 520 is formed to cover the top and side walls of the electrode protrusion 515 and the first electrode layer 510 at the side of the electrode protrusion 515.

Fig. 14 is a schematic structural diagram of fig. 12 after the first dielectric layer is formed, and fig. 15 is a schematic structural diagram of fig. 13 after the first dielectric layer is formed.

The first dielectric layer 520 serves as an insulating layer in forming the MIM capacitor to isolate the first electrode layer 510 from a subsequently formed second electrode layer.

In this embodiment, the material of the first dielectric layer 520 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. And the high-k dielectric material is selected, so that the capacitance value of the MIM capacitor is improved, and the capacitance density is correspondingly improved.

Specifically, the first dielectric layer 520 is a high-k dielectric layer formed by stacking, i.e., the first dielectric layer 520 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the first dielectric layer 520 can meet the process requirement and has better formation quality. To this end, the high-k dielectric material includes one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

In this embodiment, the first dielectric layer 520 is ZAZ layers. Wherein, ZAZ layers include a first ZrO ₂ layer, an Al ₂O₃ layer and a second ZrO ₂ layer formed in a stacked manner. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.

Referring to fig. 16 and 17, a second electrode layer 530 is formed to cover the first dielectric layer 520, and a first opening 535 is formed in the second electrode layer 530, and the first opening 535 exposes the first dielectric layer 520 on top of the electrode protrusion 515.

Fig. 16 is a schematic structural view of fig. 14 after forming the second electrode layer, and fig. 17 is a schematic structural view of fig. 15 after forming the second electrode layer.

The second electrode layer 530 is used as an electrode plate of the MIM capacitor.

In this embodiment, the material of the second electrode layer 530 is a conductive material. As an example, the material of the second electrode layer 530 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

The second electrode layer 530 has a first opening 535 formed therein, so that a first via interconnection structure is formed at a position of the first opening 535 to be in contact with only the first electrode layer and the third electrode layer, but not the second electrode layer 530.

In this embodiment, the step of forming the second electrode layer 530 includes forming a second electrode material layer (not shown) covering the first dielectric layer 520, patterning the second electrode material layer, forming a first opening 535 exposing the first dielectric layer 520 at the position of the electrode protrusion 515, and using the remaining second electrode material layer as the second electrode layer 530.

The ratio of the height H1 of the electrode convex portion 515 to the thickness H2 of the second electrode layer 530 on the side portion thereof in the normal direction of the substrate 500 is preferably not too small or too large. If the ratio of the height H1 of the electrode protrusion 515 to the thickness H2 of the second electrode layer 530 at the side portion thereof is too small or too large, the difference between the height of the first via interconnection structure formed at the position of the first opening 535 and the height of the second via interconnection structure formed at the position of the second opening is too large, which tends to increase the difficulty of the subsequent processes for forming the first via interconnection structure and the second via interconnection structure. In this embodiment, the height H1 of the electrode protrusion 515 is 80% to 95% of the thickness H2 of the second electrode layer 530 at the side along the normal direction of the top surface of the substrate 500.

Referring to fig. 18 and 19, a second dielectric layer 540 is formed to cover the second electrode layer 530, and the second dielectric layer 540 further covers the first dielectric layer 520 exposed by the first opening 535.

Fig. 18 is a schematic structural diagram of fig. 16 after the second dielectric layer is formed, and fig. 19 is a schematic structural diagram of fig. 17 after the second dielectric layer is formed.

The second dielectric layer 540 serves as an insulating layer in forming the MIM capacitor to isolate the second electrode layer 530 from a subsequently formed third electrode layer.

In the embodiment, the material of the second dielectric layer 540 is a high-k dielectric material, and the reason for selecting the high-k dielectric material as the material of the second dielectric layer 540 is similar to that of the first dielectric layer 520, and thus will not be described herein.

Specifically, the second dielectric layer 540 is a high-k dielectric layer formed by stacking, i.e., the second dielectric layer 540 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the second dielectric layer 540 can meet the process requirement and has better formation quality. To this end, the high-k dielectric material includes one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

As an example, the second dielectric layer 540 is ZAZ layers. Wherein the ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed in a stack. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.

Referring to fig. 20 to 21, a third electrode layer 550 is formed to cover the second dielectric layer 540, and a second opening 555 exposing the top of the second dielectric layer 540 is formed in the third electrode layer 550, and the projection of the second opening 555 on the substrate 500 and the projection of the first opening 535 on the substrate 500 are located at different positions. Here, the column direction and the row direction are perpendicular.

Fig. 20 is a schematic structural view of fig. 18 after the third electrode layer is formed, and fig. 21 is a schematic structural view of fig. 19 after the third electrode layer is formed.

The third electrode layer 550 is used as an electrode plate of the MIM capacitor.

In this embodiment, the material of the third electrode layer 550 is a conductive material. As one example, the material of the second electrode layer 130 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

In this embodiment, in the step of forming the third electrode layer 550, the second openings 555 are arranged in a matrix, and along a column direction of the matrix, projections of the electrode protrusions 515 on the substrate 500 and projections of the second openings 555 on the substrate 500 are alternately arranged, and along a row direction of the matrix, projections of the electrode protrusions 515 on the substrate 500 and projections of the second openings 555 on the substrate 500 are staggered.

Along the column direction of the matrix, the projections of the electrode protrusions 515 on the substrate 500 and the projections of the second openings 555 on the substrate 500 are alternately arranged, and along the row direction of the matrix, the projections of the electrode protrusions 515 on the substrate 500 and the projections of the second openings 555 on the substrate 500 are staggered, that is, along the diagonal direction of the matrix, the electrode protrusions 515 and the second openings 555 are alternately arranged, so that the first through hole interconnection structures corresponding to the electrode protrusions 515 and the second through hole interconnection structures corresponding to the second openings 555 formed later are alternately arranged along the diagonal direction of the matrix.

Referring to fig. 22 to 23, in this embodiment, after the third electrode layer 550 is formed, before the first via interconnection structure and the second via interconnection structure are formed, the forming method further includes forming a fourth dielectric layer 560 that covers the third electrode layer 550, and the fourth dielectric layer 560 further covers the second dielectric layer 540 exposed by the second opening 555.

Fig. 22 is a schematic structural diagram of fig. 20 after forming the fourth dielectric layer, and fig. 23 is a schematic structural diagram of fig. 21 after forming the fourth dielectric layer.

The fourth dielectric layer 560 is used to provide a process basis for the subsequent formation of the first via interconnect structure and the second via interconnect structure, and is also used to achieve electrical isolation between the first via interconnect structure and the second via interconnect structure.

Specifically, the material of the fourth dielectric layer 560 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Referring to fig. 24 to 31, at the position of the first opening 535, a first via interconnection structure 610 penetrating the third electrode layer 550, the second dielectric layer 540 and the first dielectric layer 520 is formed, the first electrode layer 510 and the third electrode layer 550 are electrically connected through the first via interconnection structure 610, and at the position of the second opening 555, a second via interconnection structure 620 penetrating the second dielectric layer 540 is formed, and the second electrode layer 530 is electrically connected with the second via interconnection structure 620.

Fig. 24 is a schematic structural view of fig. 22 after forming a second initial via hole, fig. 25 is a schematic structural view of fig. 23 after forming a first initial via hole, fig. 26 is a schematic structural view of fig. 24 after forming a second via hole, fig. 27 is a schematic structural view of fig. 25 after forming a first via hole, fig. 28 is a schematic structural view of fig. 26 after removing a second electrode layer with a second partial thickness, fig. 29 is a schematic structural view of fig. 27 after removing a first electrode layer with a first partial thickness, fig. 30 is a schematic structural view of fig. 28 after forming a second via hole interconnection structure, and fig. 31 is a schematic structural view of fig. 29 after forming a first via hole interconnection structure.

The first via interconnection structure 610 is used to electrically connect the first electrode layer 510 and the third electrode layer 550, thereby loading the first electrode layer 510 and the third electrode layer 550 with a first electrical signal. The second via interconnect structure 620 is used to electrically connect the second electrode layer 530, thereby loading the second electrode layer 530 with a second electrical signal.

Because the electrode protrusion 515 is formed on the first electrode layer 510, the vertical distance between the first electrode layer 510 and the third electrode layer 550 at the top of the electrode protrusion 515 is smaller, and accordingly, the distance between the first electrode layer 510 and the third electrode layer 550, which are electrically connected with the first via interconnection structure 610, is reduced, that is, the height of the first via interconnection structure 610 is reduced, so that the second via interconnection structure 620 does not need to penetrate through the second electrode layer 530, and therefore, an opening for forming the second via interconnection structure 620 does not need to be reserved in the first electrode layer 510, that is, the area of the first electrode layer 510 is increased, and the facing areas of the first electrode layer 510 and the second electrode layer 530 are correspondingly increased, which is beneficial to increasing the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 510, the second electrode layer 530 and the third electrode layer 550, and further improving the performance of the semiconductor structure.

It should be noted that, the first electrical signal is applied to the first electrode layer 510 and the third electrode layer 550 through the first via interconnection structure 610, and the second electrical signal is applied to the second electrode layer 530 through the second via interconnection structure 620, so that a potential difference exists between the first electrode layer 510 and the second electrode layer 530, and a potential difference exists between the second electrode layer 530 and the third electrode layer 550, so that the first electrode layer 510, the second electrode layer 530 and the third electrode layer 550 form a MIM capacitor.

Specifically, the material of the first via interconnect structure 610 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride. The material of the second via interconnect structure 620 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.

In this embodiment, along the column direction of the matrix, the projections of the electrode protrusions 515 on the substrate 500 and the projections of the second openings 555 on the substrate 500 are alternately arranged, and along the row direction of the matrix, the projections of the electrode protrusions 515 on the substrate 500 and the projections of the second openings 555 on the substrate 500 are staggered. Accordingly, the first via interconnection structures 610 and the second via interconnection structures 620 are alternately arranged in a direction along a diagonal line of the matrix.

The first and second via interconnection structures 610 and 620 are alternately arranged in a direction along a diagonal line of the matrix so that the comb-tooth parts of the first rewiring structure and the comb-tooth parts of the second rewiring structure are disposed to cross.

In this embodiment, the step of forming the first via interconnection structure 610 and the second via interconnection structure 620 includes forming a first via 611 penetrating the fourth dielectric layer 560, the third electrode layer 550, the second dielectric layer 540, and the first dielectric layer 520 at the first opening 535, forming a second via 621 penetrating the fourth dielectric layer 560 and the second dielectric layer 540 at the second opening 555, filling the first via 611, forming the first via interconnection structure 610 (as shown in fig. 31), filling the second via 621, and forming the second via interconnection structure 620 (as shown in fig. 30).

First through holes 611 penetrating through the fourth dielectric layer 560, the third electrode layer 550, the second dielectric layer 540 and the first dielectric layer 520, and second through holes 621 penetrating through the fourth dielectric layer 560 and the second dielectric layer 540 are formed first, the first through holes 611 are refilled to form the first through hole interconnection structures 610, and the second through holes 621 are filled to form the second through hole interconnection structures 620, which is beneficial to reducing the difficulty of forming the first through hole interconnection structures 610 and the second through hole interconnection structures 620, and therefore the quality of the first through hole interconnection structures 610 and the second through hole interconnection structures 620 is improved.

Since in this embodiment, before forming the first via interconnection structure 610 and the second via interconnection structure 620, a fourth dielectric layer is formed to cover the third electrode layer, and the fourth dielectric layer also covers the second dielectric layer exposed by the second opening. Accordingly, in the step of forming the first via 611 and the second via 621, the first via 611 and the second via 621 each need to penetrate the fourth dielectric layer 560.

In this embodiment, the step of forming the first via 611 and the second via 621 includes forming a first initial via 615 (shown in fig. 25) penetrating the fourth dielectric layer 560 and the third electrode layer 550 at the first opening 535, forming a second initial via 625 (shown in fig. 24) penetrating the fourth dielectric layer 560 at the second opening 555, removing the second dielectric layer 540 and the first dielectric layer 520 at the bottom of the first initial via 615 at the first electrode layer 510 at the stop, forming the first via 611 (shown in fig. 27), and removing the second dielectric layer 540 at the bottom of the second initial via 625 at the second electrode layer 530 at the stop, thereby forming the second via 621 (shown in fig. 26).

The first initial via 615 and the second initial via 625 are formed first, and then the first via 611 and the second via 621 are formed, which is beneficial to reducing the difficulty of forming the first via 611 and the second via 621, thereby improving the quality of the first via 611 and the second via 621, and correspondingly improving the quality of the first via interconnection structure 610 and the second via interconnection structure 620.

The first initial via 615 and the second initial via 625 are formed with the second dielectric layer 540 as a stop position, so that the first initial via 615 and the second initial via 625 are formed in the same step, thereby facilitating the reduction of the process steps of forming the first initial via 615 and the second initial via 625 and saving the process cost.

The first through hole 611 is located at the first opening 535 at the top of the electrode protrusion 515, that is, the vertical distance from the bottom of the first initial through hole 615 to the first electrode layer 510 is less different from the vertical distance from the bottom of the second initial through hole 625 to the second electrode layer 530, so that the first through hole 611 and the second through hole 621 are conveniently formed in the same step, which is correspondingly beneficial to reducing the process steps and saving the process cost. Moreover, since the materials of the first electrode layer 510 and the second electrode layer 530 are both conductive materials, and the materials of the first dielectric layer 520 and the second dielectric layer 540 are both high-k dielectric materials, the difference between the etching selectivity of the first dielectric layer 520 and the first electrode layer 510 and the etching selectivity of the second dielectric layer 540 and the second electrode layer 530 is small, so that the first through hole 611 and the second through hole 621 are further facilitated to be formed in the same step.

The etching selectivity of the third electrode layer 550 to the second dielectric layer 540 and the etching selectivity of the fourth dielectric layer 560 to the second dielectric layer 540 should not be too small. If the etching selectivity of the third electrode layer 550 to the second dielectric layer 540 and the etching selectivity of the fourth dielectric layer 560 to the second dielectric layer 540 are too small, it is not easy to control the etching depth of the first initial via 615 and the second initial via 625, so that the sizes and the morphologies of the first initial via 615 and the second initial via 625 are easily bad, and correspondingly, the sizes and the morphologies of the first via 611 and the second via 621 are bad. Therefore, in the present embodiment, in the step of forming the first initial via 615 and the second initial via 625, the etching selectivity of the third electrode layer 550 and the second dielectric layer 540 is greater than 800, and the etching selectivity of the fourth dielectric layer 560 and the second dielectric layer 540 is greater than 800.

It should be noted that the etching selectivity of the first dielectric layer 520 to the first electrode layer 510 and the etching selectivity of the second dielectric layer 540 to the second electrode layer 530 are not too small. If the etching selectivity of the first dielectric layer 520 to the first electrode layer 510 and the etching selectivity of the second dielectric layer 540 to the second electrode layer 530 are too small, it is not easy to control the etching depth of the first through hole 611 and the second through hole 621, so that the sizes and the morphologies of the first through hole 611 and the second through hole 621 are easily poor. Therefore, in the step of forming the first through hole 611 and the second through hole 621, the etching selectivity of the first dielectric layer 520 to the first electrode layer 510 is greater than 800, and the etching selectivity of the second dielectric layer 540 to the second electrode layer 530 is greater than 800.

In this embodiment, the process of forming the first and second preliminary vias 615 and 625 includes an anisotropic etching process, and the process of forming the first and second vias 611 and 621 includes an anisotropic etching process.

The anisotropic etching process has the characteristic of anisotropic etching, has directivity in etching, has higher etching precision and better controllability on the profile, and is beneficial to improving the dimensional precision and the morphology precision of the formed first initial through hole 615, second initial through hole 625, first through hole 611 and second through hole 621 in the process of etching the first initial through hole 615, second initial through hole 625, first through hole 611 and second through hole 621.

As an example, the first and second preliminary via holes are formed using an anisotropic dry etching process, and the first and second via holes are formed using an anisotropic dry etching process.

In this embodiment, the first and second initial vias 615 and 625 are formed using an anisotropic dry etching process.

In the step of forming the first initial via 615 and the second initial via 625 by using the anisotropic dry etching process, the process time should not be too short or too long. If the process time is too short, the first initial via 615 or the bottom of the second initial via 625 is easy to have the residue of the fourth dielectric layer 560, and if the process time is too long, the problem of over etching is easy to occur, so that the effect of improving the dimensional accuracy and the morphology accuracy of the first initial via 615 and the second initial via 625 is not good. In this embodiment, the process time ranges from 30 seconds to 45 seconds.

In this embodiment, the first via 611 and the second via 621 are formed using an anisotropic dry etching process.

In the step of forming the first through hole 611 and the second through hole 621 by using the anisotropic dry etching process, the process time is not too short or too long. If the process time is too short, the first dielectric layer 520 is easily remained at the bottom of the first through hole 611 or the second dielectric layer 540 is easily remained at the bottom of the second through hole 621, and if the process time is too long, the problem of over etching is easily generated, so that the effect of improving the dimensional accuracy and the morphology accuracy of the first through hole 611 and the second through hole 621 is not good. In this embodiment, the process time ranges from 30 seconds to 45 seconds.

In this embodiment, the first electrode layer 510 (shown in fig. 29) is also removed in a first portion of thickness during the formation of the first via hole 611, and the second electrode layer 530 (shown in fig. 28) is also removed in a second portion of thickness during the formation of the second via hole 621.

The first electrode layer 510 having a first partial thickness is also removed during the formation of the first via 611, and the second electrode layer 530 having a second partial thickness is also removed during the formation of the second via 621, which is advantageous in ensuring the contact effect of the first via 611 with the first electrode layer 510, i.e., the contact effect of the first via interconnection structure 610 with the first electrode layer 510, and the contact effect of the second via 621 with the second electrode layer 530, i.e., the contact effect of the second via interconnection structure 620 with the second electrode layer 530, thereby ensuring the electrical connection performance of the first via interconnection structure 610 and the first electrode layer 510, and the electrical connection performance of the second via interconnection structure 620 and the second electrode layer 530.

Correspondingly, in the step of forming the first via interconnection structure 610, the first via interconnection structure 610 is further located in a first electrode layer of a first partial thickness, and in the step of forming the second via interconnection structure 620, the second via interconnection structure 620 is further located in a first electrode layer of a second partial thickness.

Specifically, the process of removing the first electrode layer 510 of the first partial thickness and the second electrode layer 530 of the second partial thickness includes an anisotropic etching process.

The anisotropic etching process has higher etching precision, thereby being beneficial to controlling the etching depth and reducing the probability of over etching.

As an example, an anisotropic dry etching process is used to remove the first electrode layer of the first partial thickness and to remove the second electrode layer of the second partial thickness.

In this embodiment, an anisotropic dry etching process is used, and in the step of removing the first electrode layer with the first partial thickness and the second electrode layer with the second partial thickness, the process time is not too short or too long. If the process time is too short, the effect of ensuring the surfaces of the first electrode layer 510 and the second electrode layer 530 to be exposed is easily poor, and if the process time is too long, the effect of reducing the occurrence of the over-etching problem is easily poor. In this embodiment, the process time ranges from 30 seconds to 45 seconds.

In this embodiment, the ratio of the thickness of the first portion to the thickness of the first electrode layer 510 along the normal direction of the top surface of the substrate 500 is not too small, but too large. If the ratio is too small, it is easy to make sure that the contact effect of the first via interconnection structure 610 with the first electrode layer 510 is poor, and if the ratio is too large, it is easy to increase the probability of over-etching the first electrode layer 510, that is, the probability of the first via 611 penetrating through the first electrode layer 510, and also the probability of the first via interconnection structure 610 penetrating through the first electrode layer 510, thereby increasing the probability of the first via interconnection structure 610 being electrically connected with the structure thereof. In this embodiment, the first portion of the thickness is 50% to 70% of the thickness of the first electrode layer 510 along the normal direction of the top surface of the substrate 500, and accordingly, in the step of forming the first via interconnection structure 610, the first via interconnection structure 610 is further located in the first electrode layer 510 with a thickness of 50% to 70%.

In this embodiment, the ratio of the second portion thickness to the second electrode layer 530 is not too large or too small along the normal direction of the top surface of the substrate 500. If the ratio is too small, it is easy to make sure that the contact effect of the second via interconnection structure 620 with the second electrode layer 530 is poor, and if the ratio is too large, it is easy to increase the probability of over etching the second electrode layer 530, that is, the probability of the second via 621 penetrating the second electrode layer 530, and also the probability of the second via interconnection structure 620 penetrating the second electrode layer 530, thereby increasing the probability of the second via interconnection structure 620 electrically connecting the first electrode layer 110. So that the effect of reducing the occurrence of the over-etching problem is poor. In this embodiment, the second portion of the thickness is 50% to 70% of the thickness of the second electrode layer 530 along the normal direction of the top surface of the substrate 500. Accordingly, in the step of forming the second via interconnection structure 620, the second via interconnection structure 620 is further located in the second electrode layer 530 having a thickness of 50% to 70%.

Referring to fig. 32, fig. 32 is a top view, in this embodiment, after the first via interconnection structure 610 and the second via interconnection structure 620 are formed, the forming method further includes forming a rewiring structure 570 above the first via interconnection structure 610 and the second via interconnection structure 620, where the rewiring structure 570 includes a first rewiring structure 571 and a second rewiring structure 572, each of the first rewiring structure 571 and the second rewiring structure 572 includes a comb handle portion (not labeled) and a comb tooth portion (not labeled) connected to the comb handle portion, the comb tooth portion of the first rewiring structure 571 and the comb tooth portion of the second rewiring structure 572 are disposed to intersect, and the first rewiring structure 571 is connected to the first via interconnection structure 610, and the second rewiring structure 572 is connected to the second via interconnection structure 620.

The rewiring structure 570 is capable of functioning as a rewiring for the first via interconnect structure 610 and the second via interconnect structure 620, and also facilitates loading a first electrical signal through the first rewiring structure 571, loading a first electrical signal through the first electrode layer 510 and the third electrode layer 550, and loading a second electrical signal through the second rewiring structure 572, loading a second electrical signal through the second electrode layer 530.

The first rewiring structure 571 and the second rewiring structure 572 each include a comb handle portion 575 and a comb tooth portion 576 connected to the comb handle portion 575, and the comb tooth portions 576 of the first rewiring structure 571 and the comb tooth portions 576 of the second rewiring structure 572 are disposed in a crossing manner, so that electrical signals can be loaded on the first via interconnection structure 610 or the second via interconnection structure 620 electrically connected thereto through the comb handle portion 575 at the same time, and the areas of the first rewiring structure 571 and the second rewiring structure 572 are saved, and the area of the rewiring structure 570 is correspondingly saved, thereby being beneficial to reducing the process cost.

Note that the semiconductor structure may be formed by using the forming method described in the foregoing embodiment, or may be formed by using other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

substrate;

A first electrode layer is located on the substrate, and an electrode protrusion is formed on the first electrode layer;

A first dielectric layer covering the top and side walls of the electrode protrusion and the first electrode layer covering the side of the electrode protrusion;

a second electrode layer covering the first dielectric layer, wherein a first opening is formed in the second electrode layer, and the first opening exposes the first dielectric layer on the top of the electrode protrusion;

a second dielectric layer covering the second electrode layer and the first dielectric layer exposed by the first opening;

a third electrode layer, covering the second dielectric layer, wherein a second opening is formed in the third electrode layer to expose the top of the second dielectric layer, and a projection of the second opening on the substrate and a projection of the first opening on the substrate are located at different positions;

a first through-hole interconnection structure, located at the position of the first opening and penetrating the third electrode layer, the second dielectric layer and the first dielectric layer, wherein the first electrode layer and the third electrode layer are electrically connected via the first through-hole interconnection structure;

The second through-hole interconnection structure is located at the position of the second opening and penetrates the second dielectric layer. The second electrode layer is electrically connected to the second through-hole interconnection structure.

2. The semiconductor structure as claimed in claim 1, characterized in that an initial protrusion is formed on the substrate, the first electrode layer also covers the initial protrusion, and a portion located on the initial protrusion serves as the electrode protrusion.

3 . The semiconductor structure according to claim 2 , wherein a width of the initial protrusion along a direction perpendicular to a sidewall of the initial protrusion ranges from 1 micron to 5 microns.

4 . The semiconductor structure according to claim 2 , wherein the base comprises a substrate and a third dielectric layer located on the substrate, and a top of the third dielectric layer has an initial protrusion.

5 . The semiconductor structure according to claim 1 , wherein along the normal direction of the top surface of the substrate, the height of the electrode protrusion accounts for 80% to 95% of the thickness of the second electrode layer on its side.

6. The semiconductor structure according to claim 1, characterized in that the semiconductor structure further comprises: a fourth dielectric layer covering the third electrode layer and the second dielectric layer exposed by the second opening;

The first through-hole interconnect structure and the second through-hole interconnect structure are both located in the fourth dielectric layer.

7. The semiconductor structure according to claim 1 or 6, wherein the electrode protrusions are arranged in a matrix;

The second openings are arranged in a matrix, and along the column direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are arranged alternately, and along the row direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are staggered;

The semiconductor structure also includes: a rewiring structure, located above the first through-hole interconnection structure and the second through-hole interconnection structure, the rewiring structure includes a first rewiring structure and a second rewiring structure, the first rewiring structure and the second rewiring structure both include a comb handle and a comb tooth portion connected to the comb handle; the comb tooth portion of the first rewiring structure and the comb tooth portion of the second rewiring structure are cross-arranged; and the first rewiring structure is connected to the first through-hole interconnection structure, and the second rewiring structure is connected to the second through-hole interconnection structure.

8. The semiconductor structure according to claim 1, wherein the first through-hole interconnect structure is also located in a first portion of the thickness of the first electrode layer, and along the normal direction of the top surface of the substrate, the first portion of the thickness accounts for 50% to 70% of the thickness of the second electrode layer;

The second through hole interconnection structure is also located in a second portion of the thickness of the second electrode layer, and along the normal direction of the top surface of the substrate, the second portion of the thickness accounts for 50% to 70% of the thickness of the second electrode layer.

9. A method for forming a semiconductor structure, comprising:

providing a substrate;

forming a first electrode layer on the substrate, wherein an electrode protrusion is formed on the first electrode layer;

forming a first dielectric layer of the first electrode layer covering the top and side walls of the electrode protrusion and the side of the electrode protrusion;

forming a second electrode layer covering the first dielectric layer, wherein a first opening is formed in the second electrode layer, and the first opening exposes the first dielectric layer on the top of the electrode protrusion;

forming a second dielectric layer covering the second electrode layer, wherein the second dielectric layer also covers the first dielectric layer exposed by the first opening;

forming a third electrode layer covering the second dielectric layer, wherein a second opening is formed in the third electrode layer to expose the top of the second dielectric layer, and a projection of the second opening on the substrate and a projection of the first opening on the substrate are located at different positions;

At the position of the first opening, a first through-hole interconnection structure is formed that penetrates the third electrode layer, the second dielectric layer and the first dielectric layer, and the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure;

A second through-hole interconnection structure penetrating the second dielectric layer is formed at the position of the second opening, and the second electrode layer is electrically connected to the second through-hole interconnection structure.

10. The method for forming a semiconductor structure according to claim 9, wherein in the step of providing the substrate, an initial protrusion is formed on the substrate;

In the step of forming the first electrode layer, the first electrode layer also covers the initial protrusion, and a portion of the first electrode layer located on the initial protrusion serves as the electrode protrusion.

11. The method for forming a semiconductor structure according to claim 10, wherein in the step of providing the substrate, the substrate comprises a substrate and a third dielectric layer located on the substrate;

Before forming the first electrode layer on the substrate, the third dielectric layer is patterned to form a raised initial protrusion on the remaining thickness of the third dielectric layer.

12. The method for forming a semiconductor structure according to claim 9, wherein in the step of forming the first electrode layer, the electrode protrusions are arranged in a matrix;

In the step of forming the third electrode layer, the second openings are arranged in a matrix, and along the column direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are arranged alternately, and along the row direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are staggered;

After forming the first through-hole interconnection structure and the second through-hole interconnection structure, the forming method further includes: forming a rewiring structure above the first through-hole interconnection structure and the second through-hole interconnection structure, the rewiring structure including the first rewiring structure and the second rewiring structure, the first rewiring structure and the second rewiring structure both including a comb handle portion and a comb tooth portion connected to the comb handle portion; the comb tooth portion of the first rewiring structure and the comb tooth portion of the second rewiring structure are cross-arranged; and the first rewiring structure is connected to the first through-hole interconnection structure, and the second rewiring structure is connected to the second through-hole interconnection structure.

13. The method for forming a semiconductor structure according to claim 9 or 12, characterized in that after forming the third electrode layer and before forming the first through-hole interconnection structure and the second through-hole interconnection structure, the method further comprises: forming a fourth dielectric layer covering the third electrode layer, the fourth dielectric layer also covering the second dielectric layer exposed by the second opening;

The steps of forming the first through-hole interconnection structure and the second through-hole interconnection structure include: forming a first through-hole penetrating the fourth dielectric layer, the third electrode layer, the second dielectric layer and the first dielectric layer at the first opening position, and forming a second through-hole penetrating the fourth dielectric layer and the second dielectric layer at the second opening position;

The first through hole is filled to form the first through hole interconnection structure, and the second through hole is filled to form the second through hole interconnection structure.

14. The method for forming a semiconductor structure according to claim 13, wherein:

The steps of forming the first through hole and the second through hole include: taking the second dielectric layer as the stop position, forming a first initial through hole penetrating the fourth dielectric layer and the third electrode layer at the first opening position; forming a second initial through hole penetrating the fourth dielectric layer at the second opening position;

With the first electrode layer as the stop position, the second dielectric layer and the first dielectric layer at the bottom of the first initial through hole are removed to form the first through hole; with the second electrode layer as the stop position, the second dielectric layer at the bottom of the second initial through hole is removed to form the second through hole.

15. The method for forming a semiconductor structure according to claim 14, characterized in that in the step of forming the first initial through hole and the second initial through hole, an etching selectivity ratio of the third electrode layer to the second dielectric layer is greater than 800, and an etching selectivity ratio of the fourth dielectric layer to the second dielectric layer is greater than 800;

In the step of forming the first through hole and the second through hole, an etching selectivity ratio of the first dielectric layer to the first electrode layer is greater than 800, and an etching selectivity ratio of the second dielectric layer to the second electrode layer is greater than 800.

16. The method for forming a semiconductor structure according to claim 14, wherein:

The process of forming the first preliminary through hole and the second preliminary through hole includes an anisotropic etching process, and the process of forming the first through hole and the second through hole includes an anisotropic etching process.

17. The method for forming a semiconductor structure according to claim 13, wherein in the process of forming the first through hole, a first portion of the thickness of the first electrode layer is also removed;

During the process of forming the second through hole, a second portion of the thickness of the second electrode layer is also removed.

18 . The method for forming a semiconductor structure according to claim 17 , wherein the process of removing the first portion of the thickness of the first electrode layer and the process of removing the second portion of the thickness of the second electrode layer comprise an anisotropic etching process.