CN119601569A

CN119601569A - Chip packaging structure, storage system and electronic equipment

Info

Publication number: CN119601569A
Application number: CN202311154706.9A
Authority: CN
Inventors: 方语萱; 范冬宇; 刘磊; 夏志良; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2023-09-07
Filing date: 2023-09-07
Publication date: 2025-03-11

Abstract

The disclosure provides a chip packaging structure, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problems of transmission power loss and signal crosstalk between metal wires caused by continuous reduction of widths and intervals of the metal wires when signal transmission is carried out between different chips through the metal wires. The chip packaging structure comprises a substrate, a first chip, a second chip, a first photoelectric component, a second photoelectric component and an optical waveguide. The first chip and the second chip are arranged on the substrate at intervals, the first photoelectric component and the second photoelectric component both comprise a photon circuit and an electronic circuit, the electronic circuit of the first photoelectric component is connected with the first chip, the electronic circuit of the second photoelectric component is connected with the second chip, and the optical waveguide is used for connecting the photon circuit of the first photoelectric component and the photon circuit of the second photoelectric component. The chip packaging structure can be applied to a storage system to realize data reading and writing.

Description

Chip packaging structure, storage system and electronic equipment

Technical Field

The disclosure relates to the technical field of semiconductor chips, and in particular relates to a chip packaging structure, a storage system and electronic equipment.

Background

This section provides merely background information related to the present disclosure and is not necessarily prior art.

With the development of electronic integrated circuits, the integration level is continuously improved, and the width and the distance between the metal wires for signal transmission between different chips are continuously reduced, so that the problem of signal crosstalk between the metal wires is aggravated.

Disclosure of Invention

The embodiment of the disclosure provides a chip packaging structure, a storage system and electronic equipment, and aims to solve the problem that transmission power loss and signal crosstalk between metal wires are aggravated during signal transmission when the widths and the distances of the metal wires for signal transmission between different chips are continuously reduced.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

In one aspect, a chip package structure is provided. The chip packaging structure comprises a substrate, a first chip, a second chip, a first photoelectric component, a second photoelectric component and an optical waveguide. The first chip and the second chip are arranged on the substrate at intervals, the first photoelectric component and the second photoelectric component both comprise a photon circuit and an electronic circuit, the electronic circuit of the first photoelectric component is connected with the first chip, the electronic circuit of the second photoelectric component is connected with the second chip, and the optical waveguide is used for connecting the photon circuit of the first photoelectric component and the photon circuit of the second photoelectric component.

The chip packaging structure provided by the embodiment of the disclosure realizes signal transmission between the first chip and the second chip through the first photoelectric component, the second photoelectric component and the optical waveguide, the optical waveguide has the characteristics of wide frequency band, small attenuation, electromagnetic interference resistance and the like, the power loss in the signal transmission process between the first chip and the second chip can be effectively reduced, the optical waveguide can realize multi-bit transmission, the number of wires required by signal transmission can be effectively reduced, the wire density is reduced, the wiring is simplified, and the crosstalk between signals is reduced.

In some embodiments, the optical waveguide is disposed on a surface of the substrate.

In some embodiments, the substrate comprises a packaging substrate and a transfer layer stacked on the packaging substrate, the first chip and the second chip are arranged on one side surface of the transfer layer away from the packaging substrate, and the optical waveguide is arranged on one side surface of the transfer layer away from the packaging substrate.

In some embodiments, the optical waveguide is disposed inside the substrate.

In some embodiments, the substrate comprises a packaging substrate and a transfer layer stacked on the packaging substrate, the first chip and the second chip are arranged on one side surface of the transfer layer far away from the packaging substrate, the substrate further comprises a bridge substrate embedded in the transfer layer, and the optical waveguide is arranged in the bridge substrate.

In some embodiments, the optical waveguide is disposed on a side of the substrate where the first chip and the second chip are disposed, and is disposed independent of the substrate.

In some embodiments, the substrate comprises a packaging substrate and a transfer layer stacked on the packaging substrate, the first chip and the second chip are arranged on the surface of one side of the transfer layer away from the packaging substrate, and the optical waveguide is arranged on one side of the transfer layer away from the packaging substrate and is mutually independent from the transfer layer.

In some embodiments, the substrate comprises a packaging substrate, the first chip and the second chip are arranged on the surface of the packaging substrate, and the optical waveguide is arranged on one side of the packaging substrate and is independent from the packaging substrate.

In some embodiments, the photonic and electronic circuits of the first optoelectronic component are integrally configured as a first optoelectronic chip and the photonic and electronic circuits of the second optoelectronic component are integrally configured as a second optoelectronic chip, the first optoelectronic chip being integrally disposed with the first chip and the second optoelectronic chip being integrally disposed with the second chip.

In some embodiments, the photonic circuit and the electronic circuit of the first optoelectronic component are integrally configured as a first optoelectronic chip, the photonic circuit and the electronic circuit of the second optoelectronic component are integrally configured as a second optoelectronic chip, the first optoelectronic chip and the first chip are disposed independently of each other, the second optoelectronic chip and the second chip are disposed independently of each other, and the first optoelectronic chip and the second optoelectronic chip are disposed on the substrate.

In some embodiments, the photonic circuit of the first optoelectronic component is configured as a first optical chip, the electronic circuit of the first optoelectronic component is configured as a first electrical chip, the photonic circuit of the second optoelectronic component is configured as a second optical chip, the electronic circuit of the second optoelectronic component is configured as a second electrical chip, the first electrical chip is integrally disposed with the first chip, the first optical chip is disposed on a substrate, the second electrical chip is integrally disposed with the second chip, and the second optical chip is disposed on the substrate.

In some embodiments, the substrate includes a first wire for connecting the first chip and the first optical chip and a second wire for connecting the second chip and the second optical chip.

In some embodiments, the photonic circuit of the first optoelectronic component is configured as a first optical chip, the electronic circuit of the first optoelectronic component is configured as a first electrical chip, the photonic circuit of the second optoelectronic component is configured as a second optical chip, the electronic circuit of the second optoelectronic component is configured as a second electrical chip, the first electrical chip is integrally disposed with the first chip, the first optical chip is stacked on the first chip, the second electrical chip is integrally disposed with the second chip, and the second optical chip is stacked on the second chip.

In some embodiments, the first chip is a controller chip and the second chip is a memory chip, wherein the memory chip includes a plurality of memory array die and peripheral circuit die arranged in a stack.

In another aspect, a memory system is provided that includes a chip package structure and a package layer as described above, the package layer being disposed over the first chip and the second chip.

In yet another aspect, an electronic device is provided that includes a processor and a memory system as described above, the processor being coupled to the memory system, or a printed circuit board and a chip package structure as described above disposed on and electrically connected to the printed circuit board.

It can be appreciated that, the beneficial effects of the memory system and the electronic device provided in the foregoing embodiments of the present disclosure may refer to the beneficial effects of the chip package structure described above, and will not be described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

Fig. 1 is a structural view of a chip package structure provided according to the related art;

FIG. 2 is a block diagram of an electronic device provided in accordance with some embodiments;

FIG. 3 is another block diagram of an electronic device provided in accordance with some embodiments;

FIG. 4 is a block diagram of a storage system provided in accordance with some embodiments;

FIG. 5 is a block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 6 is another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 7 is yet another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 8 is yet another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 9 is yet another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 10 is yet another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 11 is yet another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 12 is yet another block diagram of a chip package structure provided in accordance with some embodiments;

FIG. 13 is a block diagram of a interposer provided in accordance with some embodiments;

Fig. 14 is another block diagram of a interposer provided in accordance with some embodiments.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

In the description of the present disclosure, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

In the present disclosure, "above," "over," and "over" should be interpreted in the broadest sense such that "on" means not only "directly on" but also includes the meaning of "on" something with an intermediate feature or layer therebetween, and "over" or "over" means not only "over" or "over" something, but also includes the meaning of "over" or "over" something (i.e., directly on) without an intermediate feature or layer therebetween.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

It should be noted that, for example, 51/5 appearing in the drawings of the present disclosure indicates that the component 51 belongs to the component 5, and that other similar reference numerals appearing in the drawings also follow the above description.

As shown in fig. 2 and 3, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include a mobile phone (mobile phone), a tablet (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) device, an augmented reality (augmented reality, AR), etc. device. The embodiment of the present application is not particularly limited to the specific form of the electronic device 1000 described above.

In some embodiments, as shown in fig. 2, the electronic device 1000 may include a chip package structure 10 and a printed circuit board (printed circuit board, PCB) 11. The chip package structure 10 is electrically connected to the printed circuit board 11 through the electrical connection structure 12, so that the chip package structure 10 can realize signal transmission with other chips on the printed circuit board 11.

Illustratively, one or more chip package structures 10 may be disposed on the printed circuit board 11. In the case where a plurality of chip package structures 10 are provided on the printed circuit board 11, these chip package structures 10 may realize the same or different functions, and for example, these chip package structures 10 may include a chip package structure 10 for logic operation, a chip package structure 10 having a memory function, a chip package structure 10 having both a logic operation function and a memory function or other functions, and the like.

Illustratively, the electrical connection structure 12 may be a ball grid array (ball GRID ARRAY, BGA). In an alternative embodiment, if the size of the chip package structure 10 is relatively large. In order to ensure the reliability of the electrical connection between the chip package structure 10 and the printed circuit board 11, the electrical connection structure 12 may also employ a connection terminal (socket) with a socket-type fixing structure, which may also be referred to as a connector, or the like.

For example, components such as capacitance, resistance, inductance, and the like may be further provided on the printed circuit board 11. The resistor can control the current through the resistance value to enable the current to be properly regulated in the circuit, the capacitor can store charges and release the charges when needed, has the functions of smoothing power supply voltage and stabilizing the current, can complete the filtering function of an electric signal under certain conditions, and the inductor has the characteristics of storing and releasing energy and can complete the energy conversion and distribution of the circuit.

In other embodiments, as shown in fig. 3, the electronic device 1000 may further include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

The processor 200 may be, for example, a central processing unit (Central Processing Unit, CPU for short), but may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

As shown in fig. 4, the memory system 100 may include a chip package structure 10 and a package layer 13. The encapsulation layer 13 encapsulates the outside of the chip disposed within the chip package structure 10. On the one hand, the encapsulation layer 13 may increase the strength of the chip encapsulation structure 10, and on the other hand, the encapsulation layer 13 may also protect the chip in the chip encapsulation structure 10. Illustratively, the encapsulation layer 13 may include an epoxy, an expansion monomer, and a curing agent.

The memory system 100 described above may be integrated into a memory card. The memory Card includes, for example, any one of a PC Card (Personal Computer Memory Card International Association, PCMCIA, personal computer memory Card international association), compact Flash (CF) Card, smart media (SMART MEDIA, SM) Card, memory stick, multimedia Card (MMC), secure digital (Secure Digital Memory Card, SD) Card, UFS.

The storage system 100 described above may also be integrated into various types of storage devices, for example, included in the same package (e.g., universal flash storage (Universal Flash Storage, UFS) package or Embedded multimedia card (eMMC) package). That is, the storage system 100 may be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, notebook computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual Reality (VR) devices, augmented Reality (Augmented Reality, AR) devices, or any other suitable electronic device having a memory therein.

The storage system 100 may also be integrated into a Solid state disk (Solid STATE DRIVES, SSD for short).

The structure of the chip package structure 10 is described in detail below.

As shown in fig. 1, fig. 1 is a schematic diagram of a chip package structure 10' in the related art, in which a first chip 21 and a second chip 22 are both fixed on a substrate 5, and the first chip 21 and the second chip 22 are connected by a metal wire 6 in the substrate 5.

With the development of electronic integrated circuits, the integration level is continuously improved, and the width and the distance between metal wires for signal transmission between different chips are continuously reduced, which results in the increase of the resistance of the metal wires and the capacitance between the metal wires, and aggravates the problems of transmission power loss and signal crosstalk between the metal wires during signal transmission.

Based on this, as shown in fig. 5 to 12, fig. 5 to 12 are block diagrams of the chip package structure 10 according to some embodiments. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first chip 21 of the first photoelectric component 31 is electrically connected, the second photoelectric component 32 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first photoelectric component 31 and the second photoelectric component 32.

The first and second optoelectronic components 31 and 32 can transmit and receive optical signals through the optical waveguide 4, and thus, the optical signals can be transmitted to the first or second optoelectronic components 31 and 32 through the optical waveguide 4. The first chip 21 may transmit an electrical signal to the first photoelectric component 31, the first photoelectric component 31 converts the input electrical signal into an optical signal, and transmits the optical signal to the second photoelectric component 32 through the optical waveguide 4, the second photoelectric component 32 converts the input optical signal into an electrical signal, and the electrical signal is transmitted to the second chip 22, and performs arithmetic operation or logic operation on the electrical signal through the second chip 22. Conversely, the second chip 22 may also transmit an electrical signal to the second optoelectronic component 32, the second optoelectronic component 32 converts the input electrical signal into an optical signal, and transmits the optical signal to the first optoelectronic component 31 through the optical waveguide 4, the first optoelectronic component 31 converts the input optical signal into an electrical signal, and the electrical signal is then transmitted to the first chip 21, and performs arithmetic operation or logic operation on the electrical signal through the first chip 21.

The first and second photovoltaic modules 31 and 32 may each include a Photonic IC (PIC), and the optical waveguide 4 connects the Photonic circuit in the first photovoltaic module 31 and the Photonic circuit in the second photovoltaic module 32. In alternative embodiments, further processing, e.g., conversion, amplification, etc., of the electrical signals after the conversion of the optical circuits may be required, such that the first and second opto-electronic assemblies 31 and 32 may also each include electronic circuitry (ELECTRICAL IC, EIC), with the electronic circuitry within the first opto-electronic assembly 31 being electrically connected to the first chip 21 and the electronic circuitry within the second opto-electronic assembly 32 being electrically connected to the second chip 22.

The photonic circuit of the first optoelectronic component 31 may be configured as a first optical chip 312, the electronic circuit of the first optoelectronic component 31 may be configured as a first electrical chip 311, the photonic circuit of the second optoelectronic component 32 may be configured as a second optical chip 322, and the electronic circuit of the second optoelectronic component 32 may be configured as a second electrical chip 321.

The first chip 21 is used for processing the electrical signal after photoelectric conversion of the first photoelectric component 31 or transmitting the processed electrical signal to the first photoelectric component 31, and the second chip 22 is used for processing the electrical signal after photoelectric conversion of the second photoelectric component 32 or transmitting the processed electrical signal to the second photoelectric component 32. For example, the first chip 21 may be a memory chip, a controller chip, or the like, and the second chip 22 may be a memory chip, a controller chip, or the like. The above-described memory chip may include a plurality of memory array die 221 and peripheral circuit die 222, which are stacked.

The signal transmission between the first chip 21 and the second chip 22 is realized through the first photoelectric component 31, the second photoelectric component 32 and the optical waveguide 4, compared with the connection between the first chip 21 and the second chip 22 through metal wires in the related art, the optical waveguide 4 has the characteristics of wide frequency band, small attenuation, electromagnetic interference resistance and the like, the power loss in the signal transmission process between the first chip 21 and the second chip 22 can be effectively reduced, the optical waveguide 4 can realize multi-bit transmission, the number of wires required by the signal transmission can be effectively reduced, the density of the wires is reduced, the wiring is simplified, and the crosstalk between signals is reduced.

Illustratively, the optical waveguide 4 may be Silicon dioxide, SOI (Silicon-on-Insulator) or a polymer material, which is less expensive to manufacture than a metal wire.

SOI refers to a thin silicon single crystal layer that is formed over an insulator made of silicon dioxide or glass. The SOI substrate may be composed of a thin monocrystalline silicon top layer, a relatively thin insulating silicon dioxide middle layer, and a very thick silicon substrate layer. The primary function of the silicon substrate layer is to provide mechanical support for the monocrystalline silicon top layer and the insulating silicon dioxide middle layer.

Hereinafter, with reference to fig. 5 to 12, embodiments of the present application will be described.

In the description of the present application and the drawings, the same elements as those described above are denoted by the same reference numerals, and detailed description thereof is appropriately omitted.

In some embodiments, as shown in fig. 5, fig. 5 is a block diagram of a chip package structure 10 provided according to some embodiments. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optical chip 312, a first electrical chip 311, a second optical chip 322, a second electrical chip 321, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first electric chip 311 is electrically connected with the first chip 21, the second electric chip 321 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first optical chip 312 and the second optical chip 322.

In this embodiment, the substrate 5 may include a package substrate 51, and a interposer 52 stacked on the package substrate 51, where the first chip 21 and the second chip 22 are disposed on a surface of the interposer 52 away from the package substrate 51.

The package substrate 51 may be connected by bumps and the interposer 52, for example.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the interposer 52 in the substrate 5 by bump or wire bonding (the first chip 21 and the second chip 22 are illustrated in fig. 5 as being electrically connected to the interposer 52 in the substrate 5 by wire bonding).

For example, as shown in fig. 5, in order to improve the reliability of the connection between the package substrate 51 and the interposer 52, a dispensing process may be used to fill an area AA between the package substrate 51 and the interposer 52 with an Underfill (Underfill).

For example, fig. 13 is a schematic structural diagram of a re-routing layer 521, where the transit layer 52 may be a re-routing layer (redistribution layer, RDL) 521 made by a re-routing process, and the re-routing layer 521 includes a plurality of metal traces 5211 and a plurality of dielectric layers 5212, and each two adjacent metal traces 5211 are separated by the dielectric layer 5212, where the dielectric layer 5212 may be made of an insulating material such as a resin material. In order to electrically connect the metal traces 5211 on the different layers, a first conductive via 5213 can be fabricated within the dielectric layer 5212 such that the metal traces 5211 on the different layers are electrically connected through the first conductive via 5213.

When the rewiring layer 521 is employed as the transit layer 52, the rewiring layer 521 may be electrically connected to the first chip 21 and the second chip 22 by bump or wire bonding, and may be electrically connected to the metal wires 6 in the package substrate 51 by the first conductive vias 5213 and bumps.

Fig. 14 is a block diagram of an Interposer 522. As shown in fig. 14, the Interposer 52 may also be an Interposer 522 including a first substrate 5221, a redistribution layer 5222 integrated on the first substrate 5221, and a second conductive via 5223 extending through the first substrate 5221, wherein the second conductive via 5223 is electrically connected to a metal trace in the redistribution layer 5222. For example, when the first substrate 5221 is a silicon substrate formed using a semiconductor material including a silicon element, the Interposer is a silicon Interposer (Si Interposer).

When the interposer 522 is used as the interposer 52, the redistribution layer 5222 is adjacent to the first chip 21 and the second chip 22 and may be electrically connected to the first chip 21 and the second chip 22 by bump or wire bonding, and the first substrate 5221 is adjacent to the package substrate 51 and may be electrically connected to the metal wires 6 in the package substrate 51 by the second conductive vias 5223 and bumps.

The optical waveguide 4 in this embodiment may be implemented in the form of a second optical waveguide 42. The second optical waveguide 42 is disposed on a surface of the adapting layer 52 away from the package substrate 51, and may be disposed in a planar manner.

The second optical waveguide 42 may be integrated on a surface of the interposer 52, which is remote from the package substrate 51, by a semiconductor thin film process, for example.

Illustratively, the second optical waveguide 42 may comprise a substrate having a refractive index n2, and be formed by coating a dielectric film having a refractive index n1 on the substrate by a microelectronic process, and adding a cladding layer having a refractive index n 3. N1> n2> n3 are typically taken to localize the light waves propagating within the dielectric film. For example, the substrate may be made of one of silicon, gallium arsenide, or glass.

In this embodiment, the first electrical chip 311 is integrated with the first chip 21, the first optical chip 312 is disposed on the substrate 5, the second electrical chip 321 is integrated with the second chip 22, and the second optical chip 322 may be disposed on the substrate 5. The substrate 5 includes a first wire 71 and a second wire 72, the first wire 71 being used to connect the first chip 21 and the first optical chip 312, and the second wire 72 being used to connect the second chip 22 and the second optical chip 322. Specifically, the first wire 71 is used to connect the electronic circuit in the first chip 21 and the first optical chip 312, and the second wire 72 is used to connect the electronic circuit in the second chip 22 and the second optical chip 322.

It should be noted that the first conductive line 71 and the second conductive line 72 may be metal traces 5211 in the interposer 52.

In some embodiments, as shown in fig. 6, fig. 6 is another block diagram of a chip package structure 10 provided in accordance with some embodiments. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first chip 21 of the first photoelectric component 31 is electrically connected, the second photoelectric component 32 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first photoelectric component 31 and the second photoelectric component 32.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the interposer 52 in the substrate 5 by bump or wire bonding (the first chip 21 and the second chip 22 are illustrated in fig. 6 as being electrically connected to the interposer 52 in the substrate 5 by wire bonding).

Illustratively, the Interposer 52 may be a rewiring layer (redistribution layer, RDL) 521 formed by a rewiring process, or an Interposer 522. The specific structure of the rewiring layer 521 and the Interposer 522 in this embodiment is substantially the same as that of the embodiment shown in fig. 5, and will not be described here again.

It should be noted that the preparation process and specific structure of the second optical waveguide 42 are substantially the same as those in the embodiment shown in fig. 5, and will not be described herein.

In this embodiment, the electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photonic circuit in the second optoelectronic component 32 may be monolithically integrated into a second optoelectronic chip 32'. The first optoelectronic chip 31 'may be integrally disposed with the first chip 21 and the second optoelectronic chip 32' may be integrally disposed with the second chip 22. The optical waveguide 4 connects the first chip 21 and the second chip 22, and specifically, the optical waveguide 4 connects a photonic circuit in the first chip 21 and a photonic circuit in the second chip 22.

The embodiment shown in fig. 6 differs from the embodiment shown in fig. 5 in that in the embodiment shown in fig. 6 the electronic circuits and the photonic circuits in the first opto-electronic component 31 are monolithically integrated as a first opto-electronic chip 31', the first opto-electronic chip 31' being provided integrally with the first chip 21, and in that the electronic circuits and the photonic circuits in the second opto-electronic component 32 are monolithically integrated as a second opto-electronic chip 32', the second opto-electronic chip 32' being provided integrally with the second chip 22. The optical waveguide 4 connects the first chip 21 and the second chip 22.

In some embodiments, as shown in fig. 7 and 8, fig. 7 and 8 are each another structural diagram of a chip package structure 10 according to some embodiments of the present application. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first chip 21 of the first photoelectric component 31 is electrically connected, the second photoelectric component 32 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first photoelectric component 31 and the second photoelectric component 32.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the interposer 52 in the substrate 5 by bump or wire bonding (in fig. 7, the first chip 21 and the second chip 22 are illustrated as being electrically connected to the interposer 52 in the substrate 5 by bump, and in fig. 8, the first chip 21 and the second chip 22 are illustrated as being electrically connected to the interposer 52 in the substrate 5 by wire bonding).

Illustratively, the Interposer 52 may be a rewiring layer (redistribution layer, RDL) 521 formed by a rewiring process, or an Interposer 522. The specific structure of the rewiring layer 521 and the Interposer 522 in this embodiment is substantially the same as that in the embodiment shown in fig. 5, and will not be described here again.

The optical waveguide 4 in this embodiment may be implemented in the form of a third optical waveguide 43. The substrate 5 includes a package substrate 51, a transfer layer 52 stacked on the package substrate 51, a bridge substrate 53 embedded in the transfer layer 52, and the third optical waveguide 43 disposed in the bridge substrate 53.

In this embodiment, the electronic circuit and the photonic circuit in the first optoelectronic component 31 may be monolithically integrated as the first optoelectronic chip 31', and the electronic circuit and the photonic circuit in the second optoelectronic component 32 may be monolithically integrated as the second optoelectronic chip 32'. The first optoelectronic chip 31 'may be integrally disposed with the first chip 21 and the second optoelectronic chip 32' may be integrally disposed with the second chip 22. The third optical waveguide 43 connects the first chip 21 and the second chip 22, specifically, the third optical waveguide 43 connects the photonic circuit in the first chip 21 and the photonic circuit in the second chip 22.

Fig. 7 and 8 show an embodiment different from that shown in fig. 5 in that:

The substrate 5 includes a package substrate 51, and a transfer layer 52 stacked on the package substrate 51, and a bridge substrate 53 embedded in the transfer layer 52.

The optical waveguide 4 is realized in the form of a third optical waveguide 43, the third optical waveguide 43 being arranged in a bridge substrate 53.

The electronic circuits and photonic circuits in the first optoelectronic component 31 may be monolithically integrated into a first optoelectronic chip 31', the first optoelectronic chip 31' may be integrally provided with the first chip 21, and the electronic circuits and photonic circuits in the second optoelectronic component 32 may be monolithically integrated into a second optoelectronic chip 32', and the second optoelectronic chip 32' may be integrally provided with the second chip 22. The third optical waveguide 43 connects the first chip 21 and the second chip 22.

In some embodiments, as shown in fig. 9, fig. 9 is a further structural diagram of a chip package structure 10 according to some embodiments of the present application. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first chip 21 of the first photoelectric component 31 is electrically connected, the second photoelectric component 32 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first photoelectric component 31 and the second photoelectric component 32.

The substrate 5 in this embodiment comprises a package substrate 51. The first chip 21 and the second chip 22 are disposed on one side surface of the package substrate 51.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the package substrate 51 in the substrate 5 by bump or wire bonding (the first chip 21 and the second chip 22 are illustrated in fig. 9 by way of example as being electrically connected to the package substrate 51 in the substrate 5 by bump).

The optical waveguide 4 in this embodiment may be implemented in the form of a first optical waveguide 41. The first optical waveguide 41 may be disposed on the side of the package substrate 51 where the first chip 21 and the second chip 22 are disposed, and may be disposed independently of the package substrate 51. For example, the first optical waveguide 41 may be suspended at one side of the package substrate 51 and not contact with the package substrate 51.

In this embodiment, the electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photonic circuit in the second optoelectronic component 32 may be monolithically integrated into a second optoelectronic chip 32'. The first optoelectronic chip 31 'may be integrally disposed with the first chip 21 and the second optoelectronic chip 32' may be integrally disposed with the second chip 22. The first optical waveguide 41 connects the first chip 21 and the second chip 22, specifically, the first optical waveguide 41 connects a photonic circuit in the first chip 21 and a photonic circuit in the second chip 22. .

The embodiment shown in fig. 9 differs from the embodiment shown in fig. 5 in that:

the substrate 5 may not include the interposer 52. The first chip 21 and the second chip 22 are disposed on one side surface of the package substrate 51.

The optical waveguide 4 is realized in the form of a first optical waveguide 41. The first optical waveguide 41 is provided on the side of the package substrate 51 where the first chip 21 and the second chip 22 are provided, and is provided independently of the package substrate 51.

The electronic circuits and photonic circuits in the first optoelectronic component 31 are monolithically integrated as a first optoelectronic chip 31', the first optoelectronic chip 31' being integrally provided with the first chip 21, and the electronic circuits and photonic circuits in the second optoelectronic component 32 are monolithically integrated as a second optoelectronic chip 32', the second optoelectronic chip 32' being integrally provided with the second chip 22. The first optical waveguide 41 connects the first chip 21 and the second chip 22.

In some embodiments, as shown in fig. 10, fig. 10 is a further structural diagram of a chip package structure 10 according to some embodiments of the present application. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optical chip 312, a first electrical chip 311, a second optical chip 322, a second electrical chip 321, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first electric chip 311 is electrically connected with the first chip 21, the second electric chip 321 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first optical chip 312 and the second optical chip 322.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the interposer 52 in the substrate 5 by bump or wire bonding (the first chip 21 and the second chip 22 are illustrated in fig. 10 as being electrically connected to the interposer 52 in the substrate 5 by bump).

The optical waveguide 4 in this embodiment may be implemented in the form of a first optical waveguide 41. The first optical waveguide 41 may be disposed on a side of the interposer 52 where the first chip 21 and the second chip 22 are disposed, and may be disposed independently of the interposer 52. For example, the first optical waveguide 41 may be suspended on one side of the interposer 52 and not contact the interposer 52.

The embodiment shown in fig. 10 differs from the embodiment shown in fig. 5 in that the optical waveguide 4 is realized in the form of a first optical waveguide 41. The first optical waveguide 41 may be disposed on a side of the interposer 52 where the first chip 21 and the second chip 22 are disposed, and may be disposed independently of the interposer 52.

In some embodiments, as shown in fig. 11, fig. 11 is a further structural diagram of a chip package structure 10 according to some embodiments of the present application. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first chip 21 of the first photoelectric component 31 is electrically connected, the second photoelectric component 32 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first photoelectric component 31 and the second photoelectric component 32.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the interposer 52 in the substrate 5 by bump or wire bonding (the first chip 21 and the second chip 22 are illustrated in fig. 11 as being electrically connected to the interposer 52 in the substrate 5 by bump).

In this embodiment, the electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photonic circuit in the second optoelectronic component 32 may be monolithically integrated into a second optoelectronic chip 32'.

The first optoelectronic chip 31 'and the first chip 21 are disposed independently of each other, the second optoelectronic chip 32' and the second chip 22 are disposed independently of each other, and the first optoelectronic chip 31 'and the second optoelectronic chip 32' are disposed on the substrate 5. The first optoelectronic chip 31 'is connected to the first chip 21 and the first optical waveguide 41, respectively, and the second optoelectronic chip 32' is connected to the second chip 22 and the first optical waveguide 41, respectively. Specifically, the first optical waveguide 41 connects the photonic circuit in the first optoelectronic chip 31 'and the photonic circuit in the second optoelectronic chip 32', the first chip 21 connects the electronic circuit in the first optoelectronic chip 31', and the second chip 22 connects the electronic circuit in the second optoelectronic chip 32'. The first chip 21 and the first optoelectronic chip 31 'and the second chip 22 and the second optoelectronic chip 32' can be electrically connected through metal wires in the switching layer 52.

Illustratively, the first and second optoelectronic chips 31 'and 32' may be electrically connected to the interposer 52 by bump or wire bonding (illustrated in fig. 11 as the first and second optoelectronic chips 31 'and 32' being electrically connected to the interposer 52 within the substrate 5 by bumps).

The embodiment shown in fig. 11 differs from the embodiment shown in fig. 5 in that:

the optical waveguide 4 is realized in the form of a first optical waveguide 41. The first optical waveguide 41 is disposed on the side of the interposer 52 where the first chip 21 and the second chip 22 are disposed, and is disposed independently of the interposer 52.

The electronic circuits and photonic circuits within the first optoelectronic package 31 may be monolithically integrated as a first optoelectronic chip 31 'and the electronic circuits and photonic circuits within the second optoelectronic package 32 may be monolithically integrated as a second optoelectronic chip 32'. The first optoelectronic chip 31 'and the first chip 21 are disposed independently of each other, the second optoelectronic chip 32' and the second chip 22 are disposed independently of each other, and the first optoelectronic chip 31 'and the second optoelectronic chip 32' are disposed on the substrate 5. The first optoelectronic chip 31 'is connected to the first chip 21 and the first optical waveguide 41, respectively, and the second optoelectronic chip 32' is connected to the second chip 22 and the first optical waveguide 41, respectively.

In some embodiments, as shown in fig. 12, fig. 12 is a further structural diagram of a chip package structure 10 according to some embodiments of the present application. The chip package structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optical chip 312, a first electrical chip 311, a second optical chip 322, a second electrical chip 321, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixed on the substrate 5 at intervals, the first electric chip 311 is electrically connected with the first chip 21, the second electric chip 321 is electrically connected with the second chip 22, and the optical waveguide 4 is used for connecting the first optical chip 312 and the second optical chip 322.

The first chip 21 and the second chip 22 may be electrically connected to the substrate 5 by bump or wire bonding, for example. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the package substrate 51 in the substrate 5 by bump or wire bonding (the first chip 21 and the second chip 22 are illustrated in fig. 12 by way of example as being electrically connected to the package substrate 51 in the substrate 5 by bump).

In this embodiment, the first optical chip 312 may be stacked on the first chip 21, and the second optical chip 322 may be stacked on the second chip 22. The first optical chip 312 and the first chip 21 may be connected by wire bonding, and the second optical chip 322 and the second chip 22 may be connected by wire bonding. Specifically, the first optical chip 312 is connected to the electronic circuit in the first chip 21, and the second optical chip 322 is connected to the electronic circuit in the second chip 22. Because the first optical chip 312 and the first chip 21 are stacked, the second optical chip 322 and the second chip 22 are stacked, and the interconnection path is shorter, which is beneficial to improving the signal transmission efficiency

The embodiment shown in fig. 12 differs from the embodiment shown in fig. 5 in that:

The first optical chip 312 is stacked on the first chip 21, and the second optical chip 322 is also stacked on the second chip 22.

Although some embodiments of the present application are described herein in connection with fig. 5-12, the above description is exemplary and not exhaustive, and thus is not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the embodiments described above. Any combination of the arrangement of the substrate 5, the first chip 21, the second chip 22, the first optical chip 312, the arrangement among the first electrical chip 311, the second optical chip 322 and the second electrical chip 321, and the implementation form of the optical waveguide 41 is within the scope of the present application.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip package structure, comprising:

a substrate;

The first chip and the second chip are arranged on the substrate at intervals;

the first photoelectric assembly and the second photoelectric assembly comprise a photonic circuit and an electronic circuit, the electronic circuit of the first photoelectric assembly is connected with the first chip, and the electronic circuit of the second photoelectric assembly is connected with the second chip;

and the optical waveguide is used for connecting the photonic circuit of the first photoelectric component and the photonic circuit of the second photoelectric component.

2. The chip package structure of claim 1, wherein the optical waveguide is disposed on a surface of the substrate.

3. The chip package structure according to claim 2, wherein the substrate comprises a package substrate, and a transfer layer stacked on the package substrate, the first chip and the second chip being disposed on a surface of the transfer layer away from the package substrate;

the optical waveguide is arranged on one side surface of the transfer layer, which is far away from the packaging substrate.

4. The chip package structure of claim 1, wherein the optical waveguide is disposed inside the substrate.

5. The chip package structure according to claim 4, wherein the substrate comprises a package substrate, and a transfer layer stacked on the package substrate, the first chip and the second chip being disposed on a surface of the transfer layer away from the package substrate;

The substrate further comprises a bridge substrate embedded in the transfer layer, and the optical waveguide is arranged in the bridge substrate.

6. The chip package structure according to claim 1, wherein the optical waveguide is provided on a side of the substrate where the first chip and the second chip are provided, and is provided independently of the substrate.

7. The chip package structure of claim 6, wherein the substrate comprises a package substrate, and a transfer layer stacked on the package substrate, the first chip and the second chip being disposed on a surface of the transfer layer away from the package substrate;

The optical waveguide is arranged on one side of the transfer layer far away from the packaging substrate and is mutually independent from the transfer layer.

8. The chip package structure according to claim 6, wherein the substrate comprises a package substrate, and the first chip and the second chip are disposed on a surface of the package substrate;

the optical waveguide is arranged on one side of the packaging substrate and is mutually independent from the packaging substrate.

9. The chip package structure of claim 1, wherein the photonic circuit and the electronic circuit of the first optoelectronic component are integrally configured as a first optoelectronic chip and the photonic circuit and the electronic circuit of the second optoelectronic component are integrally configured as a second optoelectronic chip;

The first photoelectric chip is integrated with the first chip, and the second photoelectric chip is integrated with the second chip.

10. The chip package structure of claim 1, wherein the photonic circuit and the electronic circuit of the first optoelectronic component are integrally configured as a first optoelectronic chip and the photonic circuit and the electronic circuit of the second optoelectronic component are integrally configured as a second optoelectronic chip;

The first photoelectric chip and the first chip are mutually independent, the second photoelectric chip and the second chip are mutually independent, and the first photoelectric chip and the second photoelectric chip are both arranged on the substrate.

11. The chip package structure of claim 1, wherein the photonic circuit of the first optoelectronic component is configured as a first optical chip and the electronic circuit of the first optoelectronic component is configured as a first electrical chip; the photonic circuit of the second optoelectronic component is configured as a second optical chip, and the electronic circuit of the second optoelectronic component is configured as a second electrical chip;

the first electric chip and the first chip are integrated, the first optical chip is arranged on the substrate, the second electric chip and the second chip are integrated, and the second optical chip is arranged on the substrate.

12. The chip package structure of claim 11, wherein the substrate includes a first wire for connecting the first chip and the first optical chip and a second wire for connecting the second chip and the second optical chip.

13. The chip package structure of claim 1, wherein the photonic circuit of the first optoelectronic component is configured as a first optical chip and the electronic circuit of the first optoelectronic component is configured as a first electrical chip; the photonic circuit of the second optoelectronic component is configured as a second optical chip, and the electronic circuit of the second optoelectronic component is configured as a second electrical chip;

the first electric chip and the first chip are integrated, the first optical chip is stacked on the first chip, the second electric chip and the second chip are integrated, and the second optical chip is stacked on the second chip.

14. The chip package structure according to any one of claims 1 to 13, wherein the first chip is a controller chip and the second chip is a memory chip;

The memory chip comprises a plurality of memory array bare chips and peripheral circuit bare chips which are stacked.

15. A storage system, comprising:

the chip package structure of any one of claims 1-14;

And the packaging layer is arranged outside the first chip and the second chip in a coating manner.

16. An electronic device comprising a processor and the storage system of claim 15, the processor coupled to the storage system, or

A printed circuit board and a chip package structure according to any one of claims 1-14, said chip package structure being disposed on and electrically connected to said printed circuit board.