CN119597129A - Reset circuit - Google Patents

Abstract

The application relates to a reset circuit which comprises a clock module, a processor and a reset control module, wherein the reset control module is used for sending a power-on reset signal to the processor in the power-on starting process of a system to which the reset circuit belongs, the power-on reset signal comprises a low level of a first preset duration and a high level of a second preset duration, the power-on reset signal is in a low level period, a power-on reset mark is cleared, the processor is used for executing power-on reset after receiving the power-on reset signal and setting the power-on reset mark to be 1 after the power-on reset execution is completed, and the reset control module is also used for detecting the power-on reset mark in the period of the power-on reset signal being in the high level period and determining that the power-on reset of the processor is completed when the power-on reset mark is detected to be 1. The embodiment of the application can improve the reliability of the reset circuit.

Description

Reset circuit

Technical Field

The present disclosure relates to electronic circuits, and particularly to a reset circuit.

Background

A reset circuit is a circuit for controlling and ensuring the correct start-up of the digital circuit, which can initialize all relevant circuits to a known state at system power-up and force the system to restart if necessary. The normal operation of the processor is not separated from the reset circuit.

In the related art, a reset IC (I NTEGRATED CI rcu it chip) chip or an RC (Res i stor-capacitor) charge-discharge circuit is used to perform power-on reset on the processor. However, the reset circuit has low flexibility and poor reliability, and in a complex circuit use environment, there is a risk that the processor cannot operate normally due to a reset failure. Therefore, a highly reliable reset circuit is demanded.

Disclosure of Invention

In view of this, a reset circuit is proposed.

In a first aspect, an embodiment of the application provides a reset circuit, which comprises a clock module, a processor and a reset control module, wherein the clock module is connected with the processor and the reset control module, the processor is connected with the reset control module, the reset control module is realized by a programmable logic device, the clock module is used for providing a first clock signal for the processor and the reset control module, the reset control module is used for sending a power-on reset signal to the processor according to the first clock signal in a power-on starting process of a system to which the reset circuit belongs, the power-on reset signal comprises a low level of a first preset duration and a high level of a second preset duration, the power-on reset signal is in a low level period, the processor is used for executing power-on reset after the power-on reset signal is received, the power-on reset mark is set to be 1 after the power-on reset execution is completed, the reset control module is also used for sending the power-on reset signal to the processor according to the first clock signal, the power-on reset signal comprises a low level of the first preset duration and a high level of a second preset duration, the power-on reset mark is detected to be completed when the power-on reset signal is detected to be 1.

In some possible implementations, the reset control module further includes a reset state machine that is in an idle state during the low level of the power-on reset signal, and that jumps to a power-on reset handshake state after the power-on reset signal goes high.

In some possible implementations, the reset control module is configured to send first information to the reset state machine when the power-on reset flag is 1 is detected, where the first information is used to indicate that the power-on reset flag is 1, and the reset state machine is configured to jump to a watchdog waiting state when the first information is received.

In some possible implementations, the reset control module is configured to resend the power-on reset signal to the processor if the power-on reset flag is detected to be always 0 during the period that the power-on reset signal is high.

In some possible implementations, the reset state machine is configured to skip to a watchdog detection state after waiting for a third preset period of time according to the first clock signal in a watchdog waiting state.

In some possible implementations, the processor is configured to continuously send a periodic square wave signal to the reset control module according to the first clock signal during running of the application program, the reset control module is configured to detect a signal value of the square wave signal and calculate a holding time period of the signal value when the reset state machine is in a watchdog detection state, send second information to the reset state machine to make the reset state machine jump to a watchdog reset state when the holding time period of the signal value is greater than or equal to a preset time period threshold, and send a watchdog reset signal to the processor to make the processor perform watchdog reset when the reset state machine is in the watchdog reset state.

In some possible implementations, the reset control module is configured to clear the holding duration when the signal value of the square wave signal changes.

In some possible implementations, the reset state machine is configured to jump to a watchdog wait state after the watchdog reset signal has ended.

In some possible implementations, the reset control module further includes a first register for storing the power-on reset flag and a second register for storing the square wave signal.

In some possible implementations, the clock module includes a crystal oscillator and a clock buffer, the crystal oscillator is connected with the clock buffer, the clock buffer is connected with the processor and the reset control module, the crystal oscillator is used for generating a second clock signal, and the clock buffer is used for receiving the second clock signal and fanning out the first clock signal according to the second clock signal.

The reset circuit of the embodiment of the application comprises a clock module, a processor and a reset control module realized by a programmable logic device, and is used for resetting the processor. In the power-on starting process of a system to which the reset circuit belongs, the reset control module sends a power-on reset signal (comprising a low level of a first preset duration and a high level of a second preset duration) to the processor and clears a power-on reset mark during the period that the power-on reset signal is in the low level, the processor executes power-on reset after receiving the power-on reset signal and sets the power-on reset mark to be 1 after the power-on reset execution is completed, and meanwhile, the reset control module detects the power-on reset mark during the period that the power-on reset signal is in the high level, and determines that the power-on reset of the processor is completed when the power-on reset mark is detected to be 1. When the power-on reset is carried out on the processor, the reset control module sends a power-on reset signal to the processor, and the power-on reset mark is set to be 1 by the processor and the power-on reset mark is detected by the reset control module, so that handshake confirmation is carried out on the power-on reset of the processor, and the reset control module is realized by the programmable logic device, so that the configuration is flexible, the use is convenient, and the reliability of the reset circuit and the robustness of a system can be improved.

These and other aspects of the application will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the application and together with the description, serve to explain the principles of the application.

FIG. 1 shows a schematic diagram of a reset circuit according to an embodiment of the application;

FIG. 2 shows a schematic diagram of a reset circuit according to an embodiment of the application;

FIG. 3 illustrates a state transition diagram of a reset state machine according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the application will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

In addition, numerous specific details are set forth in the following description in order to provide a better illustration of the application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present application.

In order to solve the technical problems, the application provides a reset circuit, which comprises a clock module, a processor and a reset control module, wherein the clock module is connected with the processor and the reset control module, the processor is connected with the reset control module, and the reset control module is realized through a programmable logic device. The clock module is used for providing a first clock signal for the processor and the reset control module. The reset control module is used for sending a power-on reset signal to the processor according to the first clock signal in the power-on starting process of a system to which the reset circuit belongs, wherein the power-on reset signal comprises a low level of a first preset duration and a high level of a second preset duration, the power-on reset signal is in a low level period, the power-on reset mark is cleared, the processor is used for executing power-on reset after receiving the power-on reset signal, setting the power-on reset mark to be 1 after the power-on reset is executed, the reset control module is further used for detecting the power-on reset mark in a high level period of the power-on reset signal, and determining that the power-on reset of the processor is completed when the power-on reset mark is detected to be 1.

The reset circuit of the embodiment of the application comprises a clock module, a processor and a reset control module realized by a programmable logic device, and is used for resetting the processor. In the power-on starting process of a system to which the reset circuit belongs, the reset control module sends a power-on reset signal (comprising a low level of a first preset duration and a high level of a second preset duration) to the processor and clears a power-on reset mark during the period that the power-on reset signal is in the low level, the processor executes power-on reset after receiving the power-on reset signal and sets the power-on reset mark to be 1 after the power-on reset execution is completed, and meanwhile, the reset control module detects the power-on reset mark during the period that the power-on reset signal is in the high level, and determines that the power-on reset of the processor is completed when the power-on reset mark is detected to be 1.

When the power-on reset is carried out on the processor, the reset control module sends a power-on reset signal to the processor, and the power-on reset mark is set to be 1 by the processor and the power-on reset mark is detected by the reset control module, so that handshake confirmation is carried out on the power-on reset of the processor, and the reset control module is realized by the programmable logic device, so that the configuration is flexible, the use is convenient, and the reliability of the reset circuit and the robustness of a system can be improved.

Fig. 1 shows a schematic diagram of a reset circuit according to an embodiment of the application. As shown in fig. 1, the reset circuit 10 includes a clock module 110, a processor 120 and a reset control module 130, the clock module 110 is connected to the processor 120 and the reset control module 130, and the processor 120 is connected to the reset control module 130. The reset circuit 10 is used for performing a reset process on the processor 120.

The clock module 110 is used as a clock source of the reset circuit 10, and is used for providing a first clock signal required by the operation of the processor 120 and the reset control module 130. The processor 120 and the reset control module 130 may perform timing, counting, etc. according to the first clock signal.

The Processor 120 is used to run an application program, and the Processor 120 may be a central processing unit (Centra l Process ing Un it, CPU), a digital signal Processor (DIGITA L SIGNA L Processor, DSP), a System on Chip (SoC), etc. the specific type of the Processor 120 is not limited by the present application.

The reset control module 130 may be configured to perform reset processing such as power-on reset, power-on startup exception reset (i.e., power-on reset is continued after a first power-on reset failure of the processor during startup), and watchdog reset (reset during operation of the processor). The reset control module 130 is implemented by a programmable logic device. For example, the reset control module 130 may be implemented by a field programmable gate array (Fie ld Programmab LE GATE ARRAY, FPGA), a complex programmable logic device (Comp lex Programmab le Logic Device, CPLD), or the like. The application is not limited to the particular type of programmable logic device.

Fig. 2 shows a schematic diagram of a reset circuit according to an embodiment of the application. As shown in fig. 2, the reset circuit 10 includes a clock module 110, a processor 120, and a reset control module 130. The reset circuit 10 is used for performing a reset process on the processor 120.

The clock module 110 includes a crystal oscillator (i.e., a crystal oscillator) and a clock buffer. The crystal oscillator is connected with a clock buffer, and the clock buffer is connected with the processor 120 and the reset control module 130. The crystal is used as a clock source for generating a second clock signal and transmitting the second clock signal to the clock buffer. The clock buffer receives the second clock signal from the crystal oscillator, and according to the second clock signal, the fan-out processor 120 and the reset control module 130 operate with the first clock signal, so that the clock signal matches with the operation requirements of the processor and the reset control module.

The reset control module 130 includes a first register, a second register, and a reset state machine. The first register is used to store a power-on reset flag, and thus, the first register may also be referred to as a power-on reset flag register. The second register is used for storing a periodic square wave signal sent by the processor to the reset control module in the process of running the application program. The periodic square wave signal may also be referred to as a dog feed signal, and thus the second register may also be referred to as a dog feed signal register.

The reset state machine is used for setting various states required by the operation of the reset circuit and completing state transition when specific conditions are met. The reset state machine includes five states, an idle state (id l e, which may also be referred to as an initial state), a power-on reset handshake state (por-hd), a watchdog wait state (wdg-wait), a watchdog detect state (wdg-chk), and a watchdog reset state (wdg-rst). The reset state machine can be realized by adopting programming such as a Very High-speed integrated circuit hardware description Language (VHDL), a hardware description Language (for example, veri log HARDWARE DESCR IPT ion Language, veri log HDL) and the like, and can also be realized by adopting a graphical input mode. Those skilled in the art may determine the particular implementation of the reset state machine based on practice, as the present application is not limited in this regard.

The process of a power-on reset of a processor is exemplarily described below.

And after the reset control module is loaded, counting or timing according to the first clock signal, and sending a power-on reset signal to the processor, wherein the power-on reset signal comprises a low level (0 value) of a first preset duration (20 ms for example) and a high level (1 value) of a second preset duration (80 ms for example) and is sent to a reset pin of the processor. And after the power-on reset signal is received by the processor, the power-on reset is immediately executed, and after the power-on reset is executed, the power-on reset mark is set to be 1 by the processor, and meanwhile, the processor enters an application program, namely, the processor starts to execute the application program. In the case of storing a power-on reset flag through the first register, the processor may write a1 into the first register through the local bus, i.e., set the power-on reset flag in the first register to 1.

In the above example, the power-on reset signal is active low (with a value of 0), i.e., the processor performs a power-on reset during a low level period of a first preset duration, and performs a power-on reset handshake with the reset control module during a high level period of a second preset duration. In some embodiments, the power-on reset signal may also be active high (1 in value), such that the power-on reset signal may include a high level for a first predetermined duration and a low level for a second predetermined duration. In the embodiment of the application, the low level of the power-on reset signal is taken as an example for explanation.

The reset control module clears the power-on reset flag, i.e., sets the power-on reset flag to 0, during the period when the power-on reset signal is low. In the case of storing a power-on reset flag by the first register, the reset control module sets the power-on reset flag in the first register to 0 during a period in which the power-on reset signal is low. Wherein, a power-on reset flag of 0 indicates that the processor does not execute power-on reset or fails to execute power-on reset, and a power-on reset flag of 1 indicates that the power-on reset execution of the processor is completed.

During the low level of the power-on reset signal, the reset state machine is in an idle (id le) state. The idle state may be considered as the initial state of the reset state machine.

The reset control module may detect a power-on reset flag in the first register during a high level of the power-on reset signal, and determine that the processor power-on reset is complete when the power-on reset flag is detected as 1. And the reset control module sends first information to the reset state machine when detecting that the power-on reset mark is 1, wherein the first information is used for indicating that the power-on reset mark is 1. And under the condition that the reset state machine receives the first information, jumping to a watchdog waiting state.

In some possible implementations, when the reset control module detects that the power-on reset flag is always 0 during the period that the power-on reset signal is high level, the reset control module may consider that the power-on reset of the processor fails to be executed, and the reset control module sends the power-on reset signal to the processor again, so that the processor re-executes the power-on reset processing until the power-on reset flag is detected to be 1, so that the power-on reset processing can be performed again after the power-on reset of the processor fails due to interference, until the power-on reset is successful, automatic reset after the power-on reset failure is realized, and reliability of a reset circuit is improved. During the process of re-executing the power-on reset by the processor, the reset state machine is still in the power-on reset handshake state.

After the power-on reset is performed on the processor in the mode, the processor enters the application program, and then the execution of the application program is started.

The following exemplarily describes a procedure of watchdog reset (reset after the application program in the processor runs out).

During the running of the application program, the processor may count or time according to the first clock signal, and continuously send a periodic square wave signal to the reset control module, where the square wave signal may be regarded as a heartbeat signal of the processor, and its period may be, for example, 10 ms. In the case where the reset control module includes a second register, the processor may continue to write the periodic square wave signal to the second register.

In some possible implementations, when the reset state machine is in the watchdog waiting state, the reset state machine may count or time according to the first clock signal, and jump to the watchdog detection state after waiting for a third preset period (e.g., 300 ms). The third time period is waited here to ensure that the processor starts running the application normally and starts writing the periodic square wave signal to the second register.

In some possible implementations, the reset control module may detect a signal value of the square wave signal in the second register and calculate a hold duration of the signal value in a case where the reset state machine is in a watchdog detection state. When the signal value of the square wave signal changes (namely, the signal edge of the square wave signal), the holding time length is cleared.

For example, assuming that the period of the square wave signal is 10ms, and the signal values of the square wave signal are 0,1,0,1 in order, then the reset control module starts to calculate the holding time length of the signal value when detecting that the signal value of the square wave signal is 0, clears the holding time length when detecting that the signal value is changed from 0 to 1, resumes to calculate the holding time length, clears the holding time length when detecting that the signal value is changed from 1 to 0, resumes to calculate the holding time length, and so on. Since the period of the square wave signal is 10ms, the holding time period of each signal value is normally 5ms.

After the reset control module calculates the holding time length of the signal value of the square wave signal, the reset control module can judge whether the holding time length is greater than or equal to a preset time length threshold (for example, 300 ms), and under the condition that the holding time length is less than the time length threshold, the application program in the processor can be considered to run normally, and the detection of the signal value of the square wave signal can be continued. In this process, the reset state machine is always in the watchdog detection state.

In some possible implementations, the reset control module considers that the processor has not sent a square wave signal (i.e., a heartbeat signal) for a long time and that an application in the processor has run away in the event that the hold time of the signal value is greater than or equal to a preset time duration threshold (e.g., 300 ms). In this case, the reset control module sends a second message to the reset state machine, where the second message is used to indicate that the signal value of the square wave signal is overtime. And under the condition that the reset state machine receives the second information, jumping to a watchdog reset state.

In the watchdog reset state, the reset control module sends a watchdog reset signal to the processor, the watchdog reset signal comprising a low level for a fourth preset duration (e.g. 20 ms). After the processor receives the watchdog reset signal, a watchdog reset is performed. A watchdog reset is a reset that is performed after an application in the processor runs off, the purpose of which is to restore the processor to an initial state.

After the watchdog reset signal is ended, the reset state machine jumps to the watchdog wait state. And in the watchdog waiting state, after waiting for a third preset time period, the reset state machine jumps to the watchdog detection state. In the watchdog detection state, the reset control module continues to detect the signal value and the holding time length of the square wave signal in the mode.

Through the mode, the reset control module can dynamically detect the periodic square wave signal sent by the processor, under the condition that the holding time of the signal value of the square wave signal is longer than or equal to the time threshold, the application program in the processor is considered to run off, and then the watchdog reset signal is sent to the processor so as to reset the watchdog of the processor, so that the automatic reset of the processor under the condition that the application program runs off is realized, the risk that the application program of the processor cannot be reset after running off can be reduced, and the reliability of the reset circuit is improved.

It should be noted that, in the foregoing embodiment, the specific values of the first preset duration, the second preset duration, the third preset duration, the fourth preset duration, and the duration threshold may be set by those skilled in the art according to actual situations, which is not limited by the present application.

FIG. 3 illustrates a state transition diagram of a reset state machine according to an embodiment of the present application. As shown in fig. 3, the reset state machine includes five states, an initial state 31, a power-on reset handshake state 32, a watchdog wait state 33, a watchdog detection state 34, and a watchdog reset state 35.

During power-up start-up of the system to which the reset circuit belongs, the reset state machine is in the idle state 31 during which the power-up reset signal is low. After the power-on reset signal goes high, the reset state machine jumps from the idle state 31 to the power-on reset handshake state 32.

The reset control module sends first information to the reset state machine when the power-on reset flag is 1, the first information being used for indicating that the power-on reset flag is 1, and the reset state machine jumps from the power-on reset handshake state 32 to the watchdog waiting state 33 when the first information is received. The reset control module, upon detecting a power-on reset flag of 0, re-sends a power-on reset signal to the processor to cause the processor to re-perform a power-on reset during which the reset state machine remains in the power-on reset handshake state 32.

In the watchdog waiting state 33, the reset state machine jumps to the watchdog detection state 34 after waiting a third preset period of time, based on the first clock signal.

In the watchdog detection state 34, the processor continuously transmits a periodic square wave signal to the reset control module according to a first clock signal in the process of running an application program, the reset control module detects the signal value of the square wave signal transmitted by the processor and calculates the holding time of the signal value, and when the holding time of the signal value is greater than or equal to a preset time threshold value, second information is transmitted to the reset state machine, the second information is used for indicating that the holding time of the signal value of the square wave signal is greater than or equal to the time threshold value, and when the second information is received, the reset state machine jumps from the watchdog detection state 34 to the watchdog reset state 35.

In the watchdog reset state 35, the reset control module sends a watchdog reset signal of a fourth preset duration to the processor to cause the processor to perform watchdog reset. After the watchdog reset signal ends, the reset state machine jumps from the watchdog reset state 35 to the watchdog wait state 33, so that the above-mentioned correlation processing continues to be performed, which is not described in detail here.

The reset circuit of the embodiment of the application supports power-on reset, power-on starting abnormal reset (namely, the power-on reset is continued after the first power-on reset failure of the processor in the starting process) and watchdog reset, so that the reset circuit can automatically reset when the power-on of the processor fails in the case of interference reset or an application program runs off, and the reliability of the reset circuit and the robustness of a system are improved.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by hardware (e.g., circuits or ASICs (application specific integrated circuits)) which perform the corresponding functions or acts, or combinations of hardware and software, such as firmware, etc.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the term "comprising" (compr i s ing) does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (10)

1. The reset circuit is characterized by comprising a clock module, a processor and a reset control module, wherein the clock module is connected with the processor and the reset control module, and the processor is connected with the reset control module;

the clock module is used for providing a first clock signal for the processor and the reset control module;

The reset control module is used for:

In the power-on starting process of a system to which the reset circuit belongs, a power-on reset signal is sent to the processor according to the first clock signal, wherein the power-on reset signal comprises a low level with a first preset duration and a high level with a second preset duration;

the processor is configured to:

after the power-on reset signal is received, executing power-on reset, and setting the power-on reset mark to be 1 after the power-on reset is executed;

the reset control module is further configured to:

and when the power-on reset mark is detected to be 1, determining that the power-on reset of the processor is completed.

2. The reset circuit of claim 1 wherein the reset control module further comprises a reset state machine that is in an idle state during a low level of the power-on reset signal, and wherein the reset state machine jumps to a power-on reset handshake state after the power-on reset signal goes high.

3. The reset circuit of claim 2 wherein the reset control module is configured to send a first message to the reset state machine indicating a power-on reset flag of 1 if the power-on reset flag of 1 is detected;

the reset state machine is used for jumping to a watchdog waiting state under the condition that the first information is received.

4. The reset circuit of claim 1 wherein the reset control module is configured to resend the power-on reset signal to the processor if the power-on reset flag is detected to have been 0 during the high level of the power-on reset signal.

5. The reset circuit of claim 3 wherein the reset state machine is configured to skip to a watchdog detection state after waiting for a third predetermined period of time based on the first clock signal in a watchdog wait state.

6. The reset circuit of claim 5 wherein the processor is configured to continuously send a periodic square wave signal to the reset control module based on the first clock signal during running of an application;

the reset control module is used for detecting the signal value of the square wave signal and calculating the holding time of the signal value under the condition that the reset state machine is in a watchdog detection state;

Sending second information to the reset state machine under the condition that the holding time length of the signal value is greater than or equal to a preset time length threshold value, so that the reset state machine jumps to a watchdog reset state;

And under the condition that the reset state machine is in a watchdog reset state, sending a watchdog reset signal to the processor so as to enable the processor to carry out watchdog reset.

7. The reset circuit of claim 6 wherein the reset control module is configured to clear the hold time period when a signal value of the square wave signal changes.

8. The reset circuit of claim 6 wherein the reset state machine is configured to jump to a watchdog wait state after the watchdog reset signal has ended.

9. The reset circuit of claim 6 wherein the reset control module further comprises a first register for storing the power-on reset flag and a second register for storing the square wave signal.

10. The reset circuit of claim 1 wherein the clock module comprises a crystal oscillator and a clock buffer, the crystal oscillator being coupled to the clock buffer, the clock buffer being coupled to the processor and the reset control module;

The crystal oscillator is used for generating a second clock signal;

The clock buffer is used for receiving the second clock signal and fanning out the first clock signal according to the second clock signal.