CN119521732A - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, on which a channel stack structure is formed, the channel stack structure comprising one or more channel stacks stacked in sequence in the longitudinal direction, the channel stack comprising a sacrificial layer and a channel layer located on the sacrificial layer, a gate structure spanning the channel stack structure is formed on the substrate, the gate structure covers part of the top and part of the sidewalls of the channel stack structure; forming a first groove in the channel stack structure and part of the substrate on both sides of the gate structure; forming an insulating layer on the exposed sidewalls of the substrate in the first groove; forming a source-drain doping layer covering the sidewalls of the insulating layer in the first groove. The insulating layer can reduce the probability of leakage current generated by the source-drain doping layer and the device gate structure formed by the subsequent process through the substrate below the channel layer, thereby improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor transistors are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor transistors, and therefore, as the element density and integration level of the semiconductor transistors are increased, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

To better accommodate the demands of transistor scaling, semiconductor processes are gradually beginning to transition from planar transistors to three-dimensional transistors with higher power, such as fin field effect transistors (finfets), gate-all-around (GAA) transistors, and the like. Wherein the fully-enclosed gate transistors include vertical fully-enclosed gate transistors and horizontal fully-enclosed gate transistors. In the fully-enclosed gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.

As device dimensions shrink further, it becomes increasingly difficult and challenging to improve the performance of fully surrounding gate structure devices.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to further improving the performance of the semiconductor structure.

In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a channel structure layer, a device grid structure, a source-drain doping layer, an insulating layer, an inner wall layer, an interlayer dielectric layer and an interlayer dielectric layer, wherein the channel structure layer is suspended at the top of the substrate and comprises one or more channel layers which are arranged at intervals in the longitudinal direction, the device grid structure is arranged on the substrate and spans across the channel structure layer, the device grid structure covers part of the top, part of the side wall and part of the bottom of the channel layer, the source-drain doping layer is arranged in the channel structure layer and part of the substrate at two sides of the device grid structure, the insulating layer is arranged between the side wall of the source-drain doping layer and the substrate, the inner wall layer is arranged between the side wall of the device grid structure and the source-drain doping layer right below the channel layer, and the interlayer dielectric layer covers the side wall of the device grid structure.

Optionally, the material of the inner wall layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

Optionally, the material of the insulating layer includes one or more of silicon oxide, silicon oxynitride, and silicon carbide nitride.

Optionally, the insulating layer has a lateral dimension of 2 nm to 6 nm, and the lateral dimension is parallel to the substrate and perpendicular to the extending direction of the gate structure.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a channel laminated structure on the substrate, forming an insulating layer on the side wall of the substrate exposed by the first groove, and forming a source-drain doping layer covering the side wall of the insulating layer in the first groove, wherein the channel laminated structure comprises one or more channel laminated layers which are sequentially stacked in the longitudinal direction, the channel laminated layer comprises a sacrificial layer and a channel layer which is arranged on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the substrate, the grid structure covers part of the top and part of the side wall of the channel laminated structure, a first groove is formed in the channel laminated structure and part of the substrate on two sides of the grid structure, and the insulating layer is formed on the side wall of the substrate exposed by the first groove.

Optionally, the step of forming the first groove comprises forming a hard mask layer on the top of the gate structure, performing patterning treatment on the channel laminated structure and part of the substrate by taking the hard mask layer as a mask, forming the first groove in the channel laminated structure and part of the substrate, and removing the hard mask layer.

Optionally, after the first groove is formed, before the modification treatment is performed, a protective layer is formed on the side wall of the channel laminated structure exposed by the first groove, and after the insulating layer is formed, before the source-drain doped layer is formed, the protective layer is removed.

Optionally, the step of forming the protective layer comprises the steps of forming a protective material layer on the side wall and the top of the gate structure and the bottom and the side wall of the first groove, removing the protective material layer on the side wall and the top of the gate structure and the bottom of the first groove, and taking the protective material layer on the side wall of the channel laminated structure exposed by the first groove as the protective layer.

Optionally, the process of removing the protective material layer on the side wall and the top of the gate structure and the bottom of the first groove includes a plasma dry etching process.

Optionally, the material of the protective layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

Optionally, a direction parallel to the substrate surface and perpendicular to the extending direction of the gate structure is a lateral direction, and the lateral dimension of the protective layer is 2nm to 4 nm.

Optionally, the step of forming the insulating layer comprises the steps of carrying out modification treatment on the substrate exposed out of the first groove to form an insulating material layer, removing the insulating material layer at the bottom of the first groove, wherein the insulating material layer positioned on the side wall of the first groove is used as a node of the insulating layer, or carrying out deposition treatment on the bottom and the side wall of the first groove to form an insulating material layer, and removing the insulating material layer at the bottom of the first groove, and the insulating material layer positioned on the side wall of the first groove is used as the insulating layer.

Optionally, the process of modifying the substrate exposed by the first groove includes a thermal oxidation process.

Optionally, the technological parameters of the thermal oxidation process comprise that the process gas comprises oxygen, nitrogen or hydrogen, the process temperature comprises 700-850 ℃, the process time comprises 10-30 min, and the gas flow comprises 0.5-10 slm.

Optionally, the process of removing the insulating material layer at the bottom of the first groove includes a dry etching process.

Optionally, after the insulating layer is formed and before the source-drain doped layer is formed, the method further comprises the steps of transversely etching a part of the sacrificial layer exposed out of the side wall of the first groove in a direction parallel to the substrate and perpendicular to the extending direction of the gate structure, forming a second groove, forming an inner wall layer in the second groove, forming an interlayer dielectric layer on the top of the source-drain doped layer after the source-drain doped layer is formed, wherein the interlayer dielectric layer covers the side wall of the gate structure, removing the gate structure, forming a gate opening in the interlayer dielectric layer, removing the sacrificial layer exposed out of the gate opening, forming a through groove communicated with the gate opening below the channel layer, and forming a device gate structure in the gate opening and the through groove, wherein the device gate structure surrounds the channel layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a first groove in a channel laminated structure and a part of a substrate on two sides of a grid structure, forming an insulating layer on the side wall of the substrate exposed out of the first groove, wherein the insulating layer has an insulating effect, and after a source-drain doped layer covering the side wall of the insulating layer is formed in the first groove, the insulating layer can reduce the probability that the source-drain doped layer and a device grid structure formed by a subsequent process generate leakage current through the substrate below the channel layer, so that the performance of the semiconductor structure is improved.

Drawings

FIG. 1 is a corresponding schematic structure diagram of a semiconductor structure;

FIG. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

Fig. 3 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

The performance of current semiconductor structures is to be improved. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.

Fig. 1 is a schematic structural diagram of a semiconductor structure.

Referring to fig. 1, a substrate 20, a channel structure layer 32 suspended on top of the substrate 20, the channel structure layer 32 including one or more channel layers 22 spaced apart in a longitudinal direction, a device gate structure 26 on the substrate 20 and crossing the channel structure layer 32, the device gate structure 26 covering a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel layer 22, a source drain doped layer 56 in the channel structure layer 32 and the substrate 20 on both sides of the device gate structure 26, an interlayer dielectric layer 36 on top of the source drain doped layer 56, and the interlayer dielectric layer 36 covering the sidewalls of the device gate structure 26.

It has been found that the insulating effect of the inner wall layer is less pronounced and that the source drain doped layer 56 and the device gate structure 26 can generate leakage currents through the substrate under the channel structure layer 32, thereby affecting the electrical properties of the semiconductor structure.

In order to solve the technical problems, the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a channel laminated structure on the substrate, forming an insulating layer on the side walls of the substrate exposed by the first groove, and forming a source-drain doping layer in the first groove, wherein the channel laminated structure comprises one or more channel laminated layers which are sequentially stacked in the longitudinal direction, the channel laminated layer comprises a sacrificial layer and a channel layer which is positioned on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the substrate, the grid structure covers part of the top and part of the side walls of the channel laminated structure, a first groove is formed in the channel laminated structure and part of the substrate on two sides of the grid structure, and the insulating layer is formed on the side walls of the substrate exposed by the first groove.

The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a first groove in a channel laminated structure and a part of a substrate on two sides of a grid structure, forming an insulating layer on the side wall of the substrate exposed out of the first groove, wherein the insulating layer has an insulating effect, and after a source-drain doped layer covering the side wall of the insulating layer is formed in the first groove, the insulating layer can reduce the probability that the source-drain doped layer and a device grid structure formed by a subsequent process generate leakage current through the substrate below the channel layer, so that the performance of the semiconductor structure is improved.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 2 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

The semiconductor structure comprises a substrate (not shown), a channel structure layer 202 suspended on top of the substrate, the channel structure layer 202 comprising one or more channel layers 2022 arranged at intervals in the longitudinal direction, a device gate structure 289 on the substrate and crossing the channel structure layer 202, the device gate structure 289 covering part of the top, part of the side walls and part of the bottom of the channel layer 2022, a source-drain doping layer 297 in the channel structure layer 202 and part of the substrate on both sides of the device gate structure 289, an insulating layer 293 between the side walls of the source-drain doping layer 297 and the substrate, an inner wall layer 296 between the side walls of the device gate structure 289 and the source-drain doping layer 297 directly below the channel layer 2022, an interlayer dielectric layer 298 on top of the source-drain doping layer 297, and the interlayer dielectric layer 298 covering the side walls of the device gate structure 289.

Specifically, by disposing the insulating layer 293 between the sidewall of the source-drain doped layer 297 and the substrate, the insulating layer 293 has an insulating effect, and after disposing the source-drain doped layer 297 covering the sidewall of the insulating layer 293 in the first recess, the insulating layer 293 can reduce the probability that the source-drain doped layer 297 and the device gate structure 289 generate leakage current through the substrate under the channel layer 2022, thereby improving the performance of the semiconductor structure.

The substrate is used to provide a process platform for forming a Gate-all-around (GAA) transistor.

In this embodiment, the base is a three-dimensional base, and the base includes a substrate 280 and a protrusion 281 protruding from the substrate 280.

In this embodiment, the substrate 280 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

In this embodiment, the bump 281 is made of the same material as the substrate 280, and the bump 281 is made of silicon. In other embodiments, the material of the protruding portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the protruding portion may be different from the material of the substrate.

Specifically, the channel structure layer 202 is used to provide a conductive channel for the transistor.

In this embodiment, the channel structure layer 202 includes a plurality of channel layers 2022 disposed at intervals, and the stacking direction of the plurality of stacked channel layers 2022 is perpendicular to the surface of the substrate 280. In this embodiment, the number of channel layers 2022 is two.

In other embodiments, the number of channel layers may also be not limited to just two.

In this embodiment, the material of the channel structure layer 202 is the same as that of the protrusion 281, and the material of the channel structure layer 202 is Si.

The device gate structure 289 is used to control the opening and closing of the conductive channel when the device is in operation.

Specifically, the device gate structure 289 is a metal gate structure.

In this embodiment, the device gate structure 289 includes a gate dielectric layer (not shown) conformally covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 2022, and a gate electrode layer (not shown) covering the gate dielectric layer.

In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, zrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, al O3, siO2 and La2O 3.

Specifically, the gate dielectric layer includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 2022, and a high-k gate dielectric layer conformally covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.

The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.

In this embodiment, the semiconductor structure further includes a sidewall layer 203 on the sidewall of the device gate structure 289.

In this embodiment, the sidewall layer 203 is a single-layer structure, and the material of the sidewall layer 203 is silicon nitride.

Specifically, the source-drain doped layer 297 is used as a source region and a drain region of a transistor.

In this embodiment, an inner wall layer 296 is located between the sidewalls of the device gate structure 289 and the source drain doped layer 297 directly below the channel layer 2022.

Specifically, the inner wall layer 296 is located between the source-drain doped layer 297 and the device gate structure 289, and the inner wall layer 296 can play a role in isolating between the source-drain doped layer 297 and the device gate structure 289, which is beneficial to reducing parasitic capacitance between the source-drain doped layer 297 and the device gate structure 289.

In this embodiment, the material of the inner wall layer 296 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

Specifically, silicon nitride, silicon oxide, and silicon oxynitride are dielectric materials that can electrically isolate the device gate structure 289 from the source-drain doped layer 297.

The insulating layer 293 has an insulating effect, and the insulating layer 293 can reduce the probability of leakage current generated between the source/drain doped layer 297 and the device gate structure 289 through the substrate under the channel layer 2022, thereby improving the performance of the semiconductor structure.

It should be noted that, taking the direction parallel to the substrate and perpendicular to the extending direction of the device gate structure 289 as the lateral direction, the lateral dimension of the insulating layer 293 is not too large or too small. If the lateral dimension of the insulating layer 293 is too large, the protrusion 281 at the bottom of the device gate structure 289 is easily oxidized during the formation process of the insulating layer 293, thereby affecting the electrical performance of the semiconductor structure, and if the lateral dimension of the insulating layer 293 is too small, the insulating effect of the insulating layer 293 is poor, and the probability of leakage current generated between the source/drain doped layer 297 and the device gate structure 289 through the substrate under the channel layer 2022 is increased, thereby improving the performance of the semiconductor structure. For this reason, in the present embodiment, the insulating layer 293 has a lateral dimension of 2 nm to 6 nm, with a direction parallel to the substrate and perpendicular to the extending direction of the device gate structure 289 as a lateral direction.

In this embodiment, the material of the insulating layer 293 includes one or more of silicon oxide, silicon oxynitride, and silicon carbide nitride.

Silicon oxide, silicon oxynitride and silicon carbide nitride are all dielectric materials with good insulating properties, which can reduce the probability of leakage current generated by the source/drain doped layer 297 and the device gate structure 289 through the substrate under the channel layer 2022.

Interlayer dielectric layer 298 is used to achieve electrical isolation between adjacent devices.

In this embodiment, the material of the interlayer dielectric layer 298 is silicon oxide.

Fig. 3 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 3 to 4, a substrate 100 is provided, on which a channel stack structure 129 is formed on the substrate 100, the channel stack structure 129 including one or more channel stacks 102 stacked in sequence in a longitudinal direction, the channel stack 102 including a sacrificial layer 1021 and a channel layer 1022 on the sacrificial layer 1021, a gate structure 104 crossing the channel stack structure 129 being formed on the substrate 100, the gate structure 104 covering a portion of a top and a portion of a sidewall of the channel stack structure 129.

The substrate 100 is used to provide a process platform for forming a Gate-all-around (GAA) transistor.

In this embodiment, the channel stack structure 129 includes one or more channel stacks 102 stacked in order in the longitudinal direction.

Each of the channel stacks 102 includes a sacrificial layer 1021 and a channel layer 1022 on the sacrificial layer 1021. The channel stack 102 provides a process basis for the subsequent formation of the channel layer 1022 that is spaced apart in a floating manner. Specifically, the sacrificial layer 1021 supports the channel layer 1022, thereby providing a process basis for subsequent implementation of spaced-apart suspended placement of the channel layer 1022, and also occupying a spatial location for subsequent formation of the device gate structure 189, the channel layer 1022 serving to provide a conductive channel for the fully-enclosed gate transistor.

Accordingly, when the number of the channel stacks 102 is plural, the number of the channel layers 1022 is plural, and the plural channel layers 1022 are disposed at intervals.

In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. In the subsequent process of removing the sacrificial layer 1021, the etching selection of SiGe and Si is relatively high, so that the effect of the process of removing the sacrificial layer 1021 on the channel layer 1022 can be effectively reduced by setting the material of the sacrificial layer 1021 to SiGe and the material of the channel layer 1022 to Si, thereby improving the quality of the channel layer 1022 and further being beneficial to improving the device performance.

In this embodiment, the gate structure 104 is a dummy gate structure, and the gate structure 104 occupies a space for the subsequently formed device gate structure 189. In this embodiment, the gate structure 104 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.

In this embodiment, the method of forming the semiconductor structure further includes forming a gate oxide layer 105 on the top surface of the channel stack structure 129 prior to forming the gate structure 104.

The gate oxide layer 105 is used to protect the channel stack structure 129, and the gate oxide layer 105 can also be used as an etching stop layer in a subsequent step of removing the gate structure 104, so as to reduce the probability of damage to the channel stack structure 129 caused by a process of removing the gate structure 104.

In this embodiment, the material of the gate oxide layer 105 includes silicon oxide.

In this embodiment, the sidewall of the gate structure 104 is further formed with a sidewall layer 103.

The sidewall layer 103 is used as an etching mask for a subsequent etching process to define a formation region of the source/drain doped layer, and the sidewall layer 103 is also used to protect a sidewall of the gate structure 104.

In this embodiment, the sidewall layer 103 has a single-layer structure, and the material of the sidewall layer 103 is silicon nitride.

Referring to fig. 5, a first recess 107 is formed in the channel stack structure 129 and a portion of the substrate 100 on both sides of the gate structure 104.

The first recess 107 provides a space for the subsequent formation of the protective layer and the insulating layer, and also provides a process window for the subsequent formation of the second recess.

In this embodiment, the step of forming the first recess 107 includes forming a hard mask layer (not shown) on top of the gate structure 104, and patterning the channel stack structure 129 and a portion of the substrate 100 using the hard mask layer as a mask to form the first recess 107 in the channel stack structure 129 and a portion of the substrate 100.

In this embodiment, the process of forming the first recess 107 includes a dry etching process.

After patterning a portion of the substrate 100, the substrate 100 becomes a three-dimensional substrate 100, and the substrate 100 includes a substrate 180 and a protruding portion 181 protruding from the substrate 180.

In this embodiment, the substrate 180 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

The protrusions 181 expose portions of the substrate 180 to provide a process basis for the subsequent formation of an isolation layer.

In this embodiment, the bump 181 is made of the same material as the substrate 180, and the bump 181 is made of silicon. In other embodiments, the material of the protruding portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the protruding portion may be different from the material of the substrate.

In this embodiment, the channel stack structure 129 is located on top of the protruding portion 181, and the extending direction of the channel stack structure 129 is the same as the extending direction of the protruding portion 181.

It should be noted that, after the first recess 107 is formed, the method for forming a semiconductor structure further includes removing the hard mask layer.

The process of removing the hard mask layer includes an ashing process.

Referring to fig. 6 to 7, after forming the first recess 107, before forming an insulating layer later, a protective layer 190 is formed on the sidewall of the channel stack structure 129 exposed by the first recess 107.

Specifically, during the subsequent formation of the insulating layer, the protection layer 190 protects the channel stack structure 129 exposed by the first groove 107, so that the probability that part of the channel layer 1022 will be consumed during the subsequent formation of the insulating layer is reduced, that is, the probability that the insulating layer is formed on the sidewall of the channel layer 1022 is greatly reduced, thereby improving the carrier mobility of the channel layer 1022.

In this embodiment, the step of forming the protection layer 190 includes forming a protection material layer 191 on the sidewalls and top of the gate structure 104 and the bottom and sidewalls of the first recess 107, removing the protection material layer 191 on the sidewalls and top of the gate structure 104 and the bottom of the first recess 107, and using the protection material layer 191 on the sidewalls of the channel stack structure 129 exposed by the first recess 107 as the protection layer 190.

As an example, the process of forming the protective material layer 191 includes an atomic layer deposition process.

It should be noted that, the protective material layer 191 at the bottom of the first groove 107 is removed, so that the top surface of the substrate 180 can be exposed, thereby providing a process basis for the subsequent modification treatment.

In this embodiment, the process of removing the sidewall and top of the gate structure 104 and the protective material layer 191 at the bottom of the first recess 107 includes a plasma dry etching process.

The plasma dry etching process has the characteristics of high controllability of etching direction, and the like, and the purpose of removing the side wall and the top of the gate structure 104 and the protective material layer 191 at the bottom of the first groove 107 cleanly can be achieved by adopting plasma to perform chemical reaction and physical reaction with the side wall and the top of the gate structure 104 and the protective material layer 191 at the bottom of the first groove 107.

In this embodiment, the material of the protective layer 190 includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

The silicon nitride, silicon oxynitride and silicon carbide nitride have an etching selectivity with the materials selected for the insulating layer to be formed later, so that the insulating layer can be remained in the process of removing the protective layer 190 later, which means that after the source-drain doped layer covering the sidewall of the insulating layer is formed later in the first groove 107, the insulating layer can reduce the probability that the source-drain doped layer and the device gate structure 189 formed by the subsequent process generate leakage current through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure.

It should be noted that, the direction parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 104 is a lateral direction, and the lateral dimension of the protection layer 190 is not too large or too small. If the lateral dimension of the protection layer 190 is too large, the aspect ratio of the remaining space of the first groove 107 is easily increased, which results in that the subsequent process window for forming an insulating layer on the sidewall of the substrate 100 exposed by the first groove 107 is reduced, and the process difficulty of forming the insulating layer is increased, and if the lateral dimension of the protection layer 190 is too small, the protection effect of the protection layer 190 on the channel layer 1022 is easily insignificant, and the probability of consuming part of the channel layer 1022 in the subsequent process of forming the insulating layer is increased, which means that the probability of forming an insulating layer on the sidewall of the channel layer 1022 is greatly increased, thereby increasing the probability of electrical failure of the semiconductor structure. For this reason, in the present embodiment, the direction parallel to the surface of the substrate 100 and perpendicular to the extending direction of the gate structure 104 is a lateral direction, and the lateral dimension of the protection layer 190 is 2 nm to 4 nm.

Referring to fig. 8 to 9, an insulating layer 193 is formed on the sidewall of the substrate 100 exposed from the first recess 107.

Specifically, an insulating layer 193 is formed on the sidewall of the substrate 100 exposed by the first groove 107, the insulating layer 193 has an insulating function, and after a source-drain doped layer covering the sidewall of the insulating layer 193 is formed in the first groove 107, the insulating layer 193 can reduce the probability that the source-drain doped layer and a device gate structure 189 formed by a subsequent process generate leakage current through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure.

In this embodiment, the step of forming the insulating layer 193 includes modifying the substrate 100 exposed by the first recess 107 to form an insulating material layer 192, and removing the insulating material layer 192 at the bottom of the first recess 107, wherein the insulating material layer 192 located on the sidewall of the first recess 107 serves as a node of the insulating layer 193.

Specifically, by modifying the substrate 100 exposed by the first groove 107, a portion of the substrate 100 is converted into the insulating material layer 192, and compared with a scheme of depositing the insulating material layer 192 on the surface of the substrate 100 exposed by the first groove 107 by using a deposition process, in the modification process, the influence of the aspect ratio of the first groove 107 on the formation quality of the insulating material layer 192 is not required to be considered, thereby improving the formation quality of the insulating material layer 192, reducing the probability of generating voids in the insulating material layer 192, and further improving the performance of the semiconductor structure.

In this embodiment, the modification treatment of the substrate 100 exposed in the first recess 107 includes a thermal oxidation process.

Specifically, the thermal oxidation process has the characteristics of low process cost, high controllability, and the like, and the substrate 100 at the bottom and the side wall of the first groove 107 can be oxidized into the insulating material layer 192 by performing modification treatment on the substrate 100 at the bottom and the side wall of the first groove 107 through the thermal oxidation process.

In this embodiment, the process gas of the thermal oxidation process includes oxygen.

Specifically, the thermal oxidation process is a high temperature process, and oxygen atoms in the oxygen gas diffuse into the substrate 100 at the bottom and the sidewall of the first recess 107 at a high temperature and chemically react with silicon atoms in the substrate 100, thereby converting a portion of the substrate 100 exposed from the first recess 107 into the insulating material layer 192.

It should be noted that the process temperature of the thermal oxidation process should not be too high or too low. If the process temperature of the thermal oxidation process is too high, it is easy to cause the entire protrusion portion 181 under the gate structure 104 to be oxidized, thereby affecting the desired electrical performance of the semiconductor structure, and if the process temperature of the thermal oxidation process is too low, it is easy to cause the process time for forming the insulating layer 193 to be too long, increasing the process cost. For this reason, in the present embodiment, the process temperature of the thermal oxidation process is 700 ℃ to 850 ℃.

It should be noted that the process time of the thermal oxidation process should not be too long or too short. If the process time of the thermal oxidation process is too long, the consumption of the substrate 100 at the bottom and the side wall of the first groove 107 is too much, which means that the insulating material layer 192 formed on the surface of the substrate 100 exposed by the first groove 107 is too much, which increases the difficulty of removing the insulating material layer 192 at the bottom of the first groove 107, and if the process time of the thermal oxidation process is too short, the consumption of the substrate 100 at the bottom and the side wall of the first groove 107 is too little, which means that the insulating layer 193 formed on the side wall of the substrate 100 exposed by the first groove 107 is too little, which means that the insulating effect of the insulating layer 193 is poor after the source-drain doped layer covering the side wall of the insulating layer 193 is formed in the first groove 107, which increases the probability of generating leakage current between the source-drain doped layer and the device gate structure 189 formed by the subsequent process through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure. For this reason, in this embodiment, the process time of the thermal oxidation process is 10min to 30min.

In particular, the gas flow rate of the thermal oxidation process is not too high nor too low. If the gas flow of the thermal oxidation process is too large, the consumption of the substrate 100 at the bottom and the side wall of the first groove 107 is easy to be excessive, which means that the insulating material layer 192 formed on the surface of the substrate 100 exposed by the first groove 107 is too much, which increases the difficulty of removing the insulating material layer 192 at the bottom of the first groove 107, and if the gas flow of the thermal oxidation process is too small, the consumption of the substrate 100 at the bottom and the side wall of the first groove 107 is easy to be too small, which means that the insulating layer 193 formed on the side wall of the substrate 100 exposed by the first groove 107 is too small, which means that the insulating effect of the insulating layer 193 is poor after the source-drain doped layer covering the side wall of the insulating layer 193 is formed in the first groove 107, which increases the probability of leakage current generated by the source-drain doped layer and the device gate structure 189 formed by the subsequent process through the substrate 100 under the channel layer 1022, thereby improving the performance of the semiconductor structure. For this reason, in the present embodiment, the gas flow rate of the thermal oxidation process is 0.5slm to 10slm.

In this embodiment, the process of removing the insulating material layer 192 at the bottom of the first recess 107 includes a dry etching process.

It should be noted that the dry etching process is an anisotropic dry etching process, and the anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate is greater than the transverse etching rate, and the profile control of the anisotropic dry etching process is better, so that the profile shape quality of the insulating material layer 192 on the side wall of the first groove 107 is improved, in addition, the selected anisotropic dry etching process is beneficial to realizing a higher etching selection ratio, so that the probability of misetching other film layers is reduced.

It should be noted that, taking a direction parallel to the substrate 100 and perpendicular to the extending direction of the gate structure 104 as a lateral direction, the lateral dimension of the insulating layer 193 should not be too large or too small. If the lateral dimension of the insulating layer 193 is too large, the remaining space of the protruding portion 181 under the gate structure 104 is easily reduced, which means that the space area of the effective channel region is reduced, thereby affecting the electrical performance of the semiconductor structure, and if the lateral dimension of the insulating layer 193 is too small, the insulating effect of the insulating layer 193 is poor after the source-drain doped layer covering the sidewall of the insulating layer 193 is subsequently formed in the first recess 107, so that the probability that leakage current is generated between the source-drain doped layer and the device gate structure 189 formed by the subsequent process through the substrate 100 under the channel layer 1022 is increased, thereby improving the performance of the semiconductor structure. For this reason, in the present embodiment, the insulating layer 193 has a lateral dimension of 2 nm to 6 nm, with a direction parallel to the substrate 100 and perpendicular to the extending direction of the gate structure 104.

In this embodiment, the material of the insulating layer 193 includes one or more of silicon oxide, silicon oxynitride, and silicon carbide nitride.

The silicon oxide, the silicon oxynitride and the silicon carbide nitride are all dielectric materials, have good insulating performance, can reduce the probability that the source-drain doped layer and the device gate structure 189 formed by the subsequent process technology generate leakage current through the substrate 100 below the channel layer 1022, and meanwhile, have etching selectivity between the silicon oxide, the silicon oxynitride and the silicon carbide nitride and the materials selected for the protective layer 190, so that the probability that the insulating layer 193 is etched and removed in the subsequent process of removing the protective layer 190 is reduced.

In other embodiments, the step of forming the insulating layer may further include performing a deposition process on the bottom and the side wall of the first groove to form an insulating material layer, and removing the insulating material layer at the bottom of the first groove and located on the side wall of the first groove as the insulating layer.

The process of carrying out deposition treatment on the bottom and the side wall of the first groove comprises an atomic layer deposition process or a chemical vapor deposition process.

Referring to fig. 10, after forming the insulating layer 193, before subsequently forming the source and drain doped layers, the method further includes removing the protective layer 190.

It should be noted that, by removing the protection layer 190, the sidewall of the channel stack structure 129 is exposed, so that subsequent etching of the portion of the sacrificial layer 1021 exposed by the sidewall of the first recess 107 is facilitated.

It should also be noted that by removing the protective layer 190 after the anti-punch-through layer is formed, the probability of doping ions entering the channel layer 1022 during the formation of the anti-punch-through layer is reduced, thereby reducing the risk of affecting the carrier mobility of the channel layer 1022 and further improving the performance of the semiconductor structure.

In this embodiment, the process of removing the protection layer 190 includes a wet etching process.

Referring to fig. 11, after the insulating layer 193 is formed, before the source/drain doped layer is formed subsequently, a second recess (not shown) is formed by laterally etching a portion of the sacrificial layer 1021 exposed from the sidewall of the first recess 107 in a direction parallel to the substrate 100 and perpendicular to the extending direction of the gate structure 104.

The second grooves provide spatial locations for subsequent formation of the inner wall layer.

As an example, the second groove is surrounded by the adjacent channel layer 1022 and the remaining sacrificial layer 1021, or the second groove is surrounded by the substrate 100, the channel layer 1022 adjacent to the substrate 100, and the remaining sacrificial layer 1021.

In this embodiment, the process of laterally etching the exposed portion of the sidewall of the first recess 107 to form the second recess by using the sacrificial layer 1021 includes a wet etching process.

The wet etching process is an isotropic etching process, so that the sacrificial layer 1021 can be etched along a direction parallel to the substrate 100 and perpendicular to the extending direction of the gate structure 104, and the wet etching process is easy to realize a larger etching selection ratio, thereby being beneficial to reducing the difficulty of etching the sacrificial layer 1021 and reducing the probability of damaging other film structures.

In this embodiment, the material of the sacrificial layer 1021 is SiGe, the material of the channel layer 1022 is Si, and the exposed sacrificial layer 1021 is wet etched by HCl vapor. The etching rate of the HCl vapor to the SiGe material is much greater than that of the Si material, so that the probability of damage to the channel layer 1022 can be effectively reduced by etching the exposed portion of the sidewall of the first recess 107 with the HCl vapor to the sacrificial layer 1021.

In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, the etching solution used in the wet etching process is a tetramethylammonium hydroxide (TMAH) solution. The difference between the etching rate of the tetramethyl ammonium hydroxide solution to the Si material and the etching rate to the SiGe material is large, so that the probability of loss of the channel layer can be effectively reduced by adopting the tetramethyl ammonium hydroxide solution to etch the sacrificial layer.

With continued reference to fig. 11, an inner wall layer 196 is formed in the second recess.

Specifically, the inner wall layer 196 is located between the subsequently formed source-drain doped layer and the device gate structure 189, and the inner wall layer 196 can play a role in isolating between the source-drain doped layer and the device gate structure 189, so that parasitic capacitance between the source-drain doped layer and the device gate structure 189 is reduced.

In this embodiment, the step of forming the inner wall layer 196 in the second recess includes forming an inner wall material layer (not shown) in the sidewalls and bottom of the first recess 107, the top and sidewalls of the gate structure 104, and the second recess, removing the inner wall material layer of the bottom and sidewalls of the first recess 107, and the inner wall material layer of the top and sidewalls of the gate structure 104, and the remaining inner wall material layer in the second recess serves as the inner wall layer 196.

In this embodiment, the process of forming the inner wall material layer includes an atomic layer deposition process or a chemical vapor deposition process.

Taking an atomic layer deposition process as an example, the atomic layer deposition process has good film step coverage, reduces the risk of occurrence of voids in the inner wall material layer, and improves the performance of the semiconductor structure.

In this embodiment, the material of the inner wall layer 196 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

Specifically, the silicon nitride, silicon oxide and silicon oxynitride are dielectric materials, which can electrically isolate the subsequently formed device gate structure 189 from the source-drain doped layer.

Referring to fig. 12, a source drain doped layer 197 is formed in the first recess 107 to cover the sidewall of the insulating layer 193.

Specifically, the source-drain doped layer 197 serves as a source region and a drain region of the transistor.

In this embodiment, the process of forming the source-drain doped layer 197 includes an epitaxial process.

Specifically, the epitaxy process has the characteristics of high growth rate, good filling performance and the like, and the source-drain doped layer 197 is formed by selecting the epitaxy process, so that the risk of generating a cavity in the source-drain doped layer 197 is reduced, and the performance of the source-drain doped layer 197 is improved.

Referring to fig. 13, after the source-drain doped layer 197 is formed, the method further includes forming an interlayer dielectric layer 198 on top of the source-drain doped layer 197, where the interlayer dielectric layer 198 covers sidewalls of the gate structure 104.

Interlayer dielectric layer 198 is used to achieve electrical isolation between adjacent devices.

In this embodiment, the material of the interlayer dielectric layer 198 is silicon oxide.

In this embodiment, the step of forming the interlayer dielectric layer 198 includes forming a dielectric material layer (not shown) on the substrate 100 on the sidewall of the gate structure 104, wherein the dielectric material layer also covers the top of the gate structure 104, and removing the dielectric material layer higher than the top of the gate structure 104, wherein the remaining dielectric material layer serves as the interlayer dielectric layer 198.

Referring to fig. 14, the gate structure 104 is removed and a gate opening 183 is formed in the interlayer dielectric layer 198.

Specifically, the gate opening 183 provides a process window for subsequent formation to remove the sacrificial layer 1021, while also providing a spatial location for subsequent formation of a device gate structure 189.

In this embodiment, the process for removing the gate structure 104 includes a dry etching process.

In this embodiment, the method for forming the semiconductor structure further includes removing the gate mask layer before removing the gate structure 104.

Specifically, the gate mask layer is removed, thereby exposing the top of the gate structure 104, in preparation for removing the gate structure 104.

With continued reference to fig. 14, the sacrificial layer 1021 exposed by the gate opening 183 is removed, and a through groove 187 communicating with the gate opening 183 is formed under the channel layer 1022.

Specifically, the sacrificial layer 1021 is removed to form the via 187, providing a spatial location for the subsequent formation of a device gate structure 189.

In this embodiment, a wet etching process is used to remove the sacrificial layer 1021. Specifically, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe, so that the sacrificial layer 1021 exposed by the gate opening 183 is removed by HCl vapor, and the etching rate of the sacrificial layer 1021 by the wet etching process is much greater than the etching rate of the channel layer 1022 and the protruding portion 181.

The sacrificial layer 1021 is removed after the source-drain doped layer 197 is formed, so that after the sacrificial layer 1021 is removed, two ends of the channel layer 1022 are connected with the source-drain doped layer 197 along the extending direction of the protruding portion 181 and suspended in the gate opening 183, thereby providing a foundation for surrounding the channel layer 1022 by the gate structure 189 of the subsequent device.

After the sacrificial layer 1021 is removed, the channel layers 1022 are disposed at intervals, and the remaining channel layers 1022 constitute a channel structure layer that is disposed on the protruding portion 181 and is disposed at intervals from the protruding portion 181.

Referring to fig. 15, a device gate structure 189 is formed in the gate opening 183 and the via 187, the device gate structure 189 surrounding the channel layer 1022.

The device gate structure 189 is used to control the opening and closing of the conductive channel during operation of the device.

Specifically, the device gate structure 189 is a metal gate structure.

In this embodiment, the material of the gate dielectric layer includes one or more of HfO ₂、ZrO₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al₂O₃、SiO₂ and La ₂O₃.

Specifically, the gate dielectric layer includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 1022, and a high-k gate dielectric layer conformally covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.

It should be noted that the gate dielectric layer also conformally covers a portion of the top of the spacer layer.

The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A semiconductor structure, comprising:

a substrate;

A channel structure layer suspended on top of the substrate, the channel structure layer including one or more channel layers spaced apart in a longitudinal direction;

A device gate structure on the substrate and crossing the channel structure layer, the device gate structure covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer;

The source-drain doped layer is positioned in the channel structure layer and part of the substrate at two sides of the grid structure of the device;

the insulating layer is positioned between the side wall of the source-drain doping layer and the substrate;

the inner wall layer is positioned between the side wall of the device grid structure right below the channel layer and the source-drain doped layer;

and the interlayer dielectric layer is positioned at the top of the source-drain doped layer and covers the side wall of the device grid structure.

2. The semiconductor structure of claim 1, wherein the material of the inner wall layer comprises one or more of silicon nitride, silicon oxide, and silicon oxynitride.

3. The semiconductor structure of claim 1, wherein the material of the insulating layer comprises one or more of silicon oxide, silicon oxynitride, and silicon carbide nitride.

4. The semiconductor structure of claim 1, wherein the insulating layer has a lateral dimension of 2 nm to 6 nm in a direction parallel to the substrate and perpendicular to an extension direction of the device gate structure.

5. A method of forming a semiconductor structure, comprising:

Providing a substrate, wherein a channel laminated structure is formed on the substrate, the channel laminated structure comprises one or more channel laminated layers which are sequentially stacked in the longitudinal direction, the channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the substrate, and the grid structure covers part of the top and part of the side wall of the channel laminated structure;

Forming a first groove in the channel laminated structure and part of the substrate at two sides of the grid structure;

Forming an insulating layer on the exposed substrate side wall of the first groove;

and forming a source-drain doped layer covering the side wall of the insulating layer in the first groove.

6. The method of forming a semiconductor structure of claim 5, wherein forming the first recess comprises forming a hard mask layer on top of the gate structure, patterning the channel stack structure and a portion of the substrate using the hard mask layer as a mask, forming a first recess in the channel stack structure and a portion of the substrate, and removing the hard mask layer.

7. The method of forming a semiconductor structure according to claim 5, further comprising forming a protective layer on sidewalls of the channel stack structure exposed by the first recess after forming the first recess and before forming the insulating layer;

After the insulating layer is formed, before the source-drain doped layer is formed, the protective layer is removed.

8. The method of forming a semiconductor structure of claim 7, wherein forming the protective layer comprises forming a protective material layer on sidewalls and tops of the gate structure and bottoms and sidewalls of the first recess, removing the protective material layer on the sidewalls and tops of the gate structure and bottoms of the first recess, and using the protective material layer on the sidewalls of the channel stack structure exposed by the first recess as the protective layer.

9. The method of forming a semiconductor structure of claim 8, wherein the process of removing the protective material layer of the gate structure sidewall and top, and the first recess bottom comprises a plasma dry etch process.

10. The method of forming a semiconductor structure of claim 7, wherein the material of the protective layer comprises one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

11. The method of claim 7, wherein a direction parallel to the substrate surface and perpendicular to the extending direction of the gate structure is a lateral direction, and the lateral dimension of the protective layer is 2 nm to 4 nm.

12. The method of forming a semiconductor structure of claim 5, wherein the step of forming the insulating layer comprises modifying the substrate exposed by the first recess to form a layer of insulating material; removing the insulating material layer at the bottom of the first groove, wherein the insulating material layer positioned on the side wall of the first groove is used as a node of the insulating layer;

Or alternatively

And removing the insulating material layer at the bottom of the first groove, and taking the insulating material layer positioned on the side wall of the first groove as the insulating layer.

13. The method of forming a semiconductor structure of claim 12, wherein the modifying the substrate exposed by the first recess comprises a thermal oxidation process.

14. The method of claim 13, wherein the thermal oxidation process comprises a process gas comprising oxygen at a process temperature of 700 ℃ to 850 ℃, a process time of 10 minutes to 30 minutes, and a gas flow of 0.5slm to 10slm.

15. The method of forming a semiconductor structure of claim 12, wherein the process of removing the layer of insulating material at the bottom of the first recess comprises a dry etching process.

16. The method of forming a semiconductor structure according to claim 5, wherein after forming the insulating layer and before forming the source/drain doped layer, further comprising laterally etching a portion of the sacrificial layer exposed by the sidewall of the first recess in a direction parallel to the substrate and perpendicular to an extending direction of the gate structure to form a second recess;

forming an inner wall layer in the second groove;

After the source-drain doped layer is formed, forming an interlayer dielectric layer on the top of the source-drain doped layer, wherein the interlayer dielectric layer covers the side wall of the gate structure;

Removing the gate structure and forming a gate opening in the interlayer dielectric layer;

Removing the sacrificial layer exposed by the gate opening, and forming a through groove communicated with the gate opening below the channel layer;

and forming a device gate structure in the gate opening and the through groove, wherein the device gate structure surrounds the channel layer.