CN119480825A

CN119480825A - Intermediate layer and manufacturing method thereof, three-dimensional packaging structure and manufacturing method thereof

Info

Publication number: CN119480825A
Application number: CN202411649479.1A
Authority: CN
Inventors: 陈�峰; 林谷宜
Original assignee: Dongguan Ruixin Instrument Co ltd
Current assignee: Dongguan Ruixin Instrument Co ltd
Priority date: 2024-11-18
Filing date: 2024-11-18
Publication date: 2025-02-18

Abstract

An interposer and a manufacturing method thereof, a three-dimensional packaging structure and a manufacturing method thereof relate to the technical field of semiconductor devices, wherein the interposer comprises a substrate and a rewiring layer; the substrate is provided with a plurality of through holes penetrating from a first surface to a second surface, each through hole is filled with conductive materials to form the conductive through holes, the substrate is provided with a groove penetrating from the first surface to the second surface, the groove divides the substrate into a plurality of connecting areas which are separated by the groove, one connecting area is configured to be connected with one chip, the chip is electrically connected with the conductive through holes in the corresponding connecting area, the rewiring layer is arranged on the second surface and is flexible and electrically connected with the conductive through holes, and the conductive through holes in one connecting area are electrically connected with the conductive through holes in the other connecting area through the rewiring layer so as to realize interconnection of the chip corresponding to one connecting area and the other chip corresponding to the other connecting area. The application can overcome the stress problem of the intermediate layer and the chip or the packaging substrate.

Description

Interposer and manufacturing method thereof, three-dimensional packaging structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to an interposer and a manufacturing method thereof, a three-dimensional packaging structure and a manufacturing method thereof.

Background

With the development of artificial intelligence, high-performance computing and other technologies, the demand on the computing power of the chip is continuously increased, and the high-performance chip generally adopts a 2.5D packaging form. 2.5D packaging to reduce power consumption and improve performance, multiple HBMs (High Bandwidth Memory, high bandwidth memories) and XPUs are typically integrated together. The development of multi-chip encapsulation technology makes the size of the Interposer (Interposer) continuously increased, the height of the pads/bumps (Bump) at the bottom of the Interposer and the Pitch of the pads continuously reduced, and the requirements on the TTV (total thickness variation), the uniformity of the Bump height, the matching of the Coefficient of Thermal Expansion (CTE) of the material and other indexes of the Interposer are increasingly higher. The oversized interposer and the IC Substrate material also have CTE mismatch and other problems, so that reliability problems such as Bump soldering failure and the like are very easy to occur, which seriously affect subsequent processes, thereby reducing the qualification rate.

Disclosure of Invention

The invention mainly solves the technical problem that the prior packaging structure has stress due to unmatched thermal expansion coefficients of the interposer, the interposer bottom bump and the packaging substrate material.

According to a first aspect, an embodiment provides an interposer, in one embodiment, comprising a substrate and a rewiring layer;

The substrate is provided with a first surface and a second surface which are opposite, the substrate is provided with a plurality of through holes penetrating from the first surface to the second surface, and each through hole is filled with a conductive material to form a conductive through hole;

The substrate is provided with a groove penetrating from the first surface to the second surface, the groove divides the substrate into a plurality of connecting areas which are separated by the groove, one connecting area is configured to be connected with one chip, and the chip is electrically connected with the conductive through hole in the corresponding connecting area;

the rewiring layer is arranged on the second surface, has flexibility and is electrically connected with the conductive through hole;

The conductive through holes in one connection region are electrically connected with the conductive through holes in the other connection region through the rewiring layer, so that the chips corresponding to the one connection region are interconnected with the other chips corresponding to the other connection region.

In one embodiment, the rewiring layer comprises a metal layer and a dielectric layer, the dielectric layer has flexibility, the metal layer is electrically connected with the conductive through hole, and the dielectric layer is made of resin.

In one embodiment, the interposer further includes a plurality of first pads;

the first solder joint is arranged on the first surface and is electrically connected with the conductive through hole, and the first solder joint is configured to be electrically connected with the chip.

In one embodiment, the interposer further includes a plurality of second pads;

The second welding spot is arranged on the surface of the rewiring layer far away from the substrate, and is electrically connected with the rewiring layer and configured to be electrically connected with the packaging substrate.

According to a second aspect, in one embodiment, a three-dimensional package structure is provided, including a plurality of chips and the interposer described in the first aspect;

the plurality of chips at least comprise a first chip and a second chip;

The first chip and the second chip are respectively attached to the corresponding connection areas on the intermediate layer, and the first chip and the second chip are electrically connected with the rewiring layer through conductive through holes on the intermediate layer.

In one embodiment, the first chip is a memory chip and the second chip is a processing chip.

In one embodiment, the three-dimensional package structure further includes a package substrate;

The interposer further includes a plurality of second pads;

the second welding spot is arranged on the surface of the rewiring layer, far away from the substrate, and is electrically connected with the rewiring layer and the packaging substrate.

In one embodiment, the three-dimensional package structure further comprises an insulating adhesive, wherein the insulating adhesive is arranged between the substrate and the chip, and the insulating adhesive wraps welding spots electrically connected between the substrate and the chip.

According to a third aspect, in one embodiment, there is provided a method for manufacturing an interposer, including:

the method comprises the steps of providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite to each other, the substrate is provided with a plurality of through holes penetrating from the first surface to the second surface, and each through hole is filled with a conductive material to form a conductive through hole;

And patterning the substrate to form a groove, wherein the groove penetrates from the first surface to the second surface, the groove divides the substrate into a plurality of connecting areas which are separated by the groove, one connecting area is configured to be connected with one chip, and the chip is electrically connected with the conductive through holes in the corresponding connecting areas.

According to a fourth aspect, in one embodiment, there is provided a method for manufacturing a three-dimensional package structure, including:

preparing an interposer using the method for manufacturing an interposer described in the third aspect;

attaching at least two chips to the corresponding connection areas, wherein the at least two chips comprise a first chip and a second chip, and the first chip and the second chip are electrically connected with the rewiring layer through conductive through holes;

the interposer with the chip is attached to a package substrate, which is electrically connected to the rewiring layer.

According to the interposer and the manufacturing method thereof, the three-dimensional packaging structure and the manufacturing method thereof, the substrate is provided with the conductive through holes along the thickness direction, the conductive through holes are electrically connected with the chips, the rewiring layer is arranged on the second surface of the interposer, the rewiring layer is flexible and is connected with the packaging substrate, the chips are stacked on the first surface of the interposer and are interconnected through the conductive through holes and the rewiring layer, the grooves penetrate through the first surface of the interposer to the second surface along the gaps among the chips, namely, the rewiring layer in each connecting area is cut from the front surface of the interposer to the rewiring layer, and the rewiring layers are connected. Through slotting in the middle of the substrate, the substrate can be subjected to stress buffering, the problems of stress generated by mismatching of thermal expansion coefficients among the substrate, the bottom bump and the packaging substrate, further caused welding failure, material layering and the like are reduced, most of stress can be further eliminated by the flexible rewiring layer, and the warping problem of a large-size packaging structure is solved.

Drawings

FIG. 1 is a schematic diagram of an interposer according to an embodiment of the present application;

Fig. 2 is a schematic structural diagram of a three-dimensional package structure according to an embodiment of the present application;

FIG. 3 is a top view of FIG. 1;

FIG. 4 is a schematic process diagram of a method for manufacturing an interposer according to an embodiment of the application;

FIG. 5 is a schematic diagram of a process of a method for manufacturing an interposer according to an embodiment of the application;

fig. 6 is a process schematic diagram of a method for manufacturing a three-dimensional package structure according to another embodiment of the application.

The reference numerals comprise 001-three-dimensional packaging structure, 1-intermediate layer, 2-groove, 3-chip, 11-substrate, 12-rewiring layer, 121-metal layer, 122-medium layer, 111-conductive through hole, 13-first welding point, 14-second welding point, 4-packaging substrate, 131-first conductive bump, 132-first welding ball, 141-second conductive bump, 142-second welding ball, 52-temporary bonding adhesive, 51-bearing plate, 53-photoresist, 54-photoetching groove and 55-V-shaped groove.

Detailed Description

The application will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, related operations of the present application have not been shown or described in the specification in order to avoid obscuring the core portions of the present application, and may be unnecessary to persons skilled in the art from a detailed description of the related operations, which may be presented in the description and general knowledge of one skilled in the art.

Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.

The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated.

With the development of multi-chip packaging technology, the size of the interposer is increased continuously, the height and the distance of the bumps/welding spots at the bottom of the interposer are reduced continuously, and the requirements on indexes such as total thickness change, bump height uniformity, material thermal expansion coefficient matching and the like of the interposer are higher and higher. The oversized interposer and the packaging substrate material also have the problems of unmatched thermal expansion coefficients, and the like, so that the reliability problems such as welding failure of welding spots and the like are very easy to occur, the subsequent process is seriously influenced, and the product yield is reduced.

In the present application, an interposer 1 and a three-dimensional package structure 001 are provided, and in particular, a slot is formed in the interposer 1, which can effectively solve the reliability problems such as solder joint failure caused by mismatching of thermal expansion coefficients of the interposer 1 and materials of the solder joint and the package substrate 4 due to the continuous increase of the size of the interposer 1.

Example 1

As shown in fig. 1, an interposer 1 according to an embodiment of the present application may include a substrate 11 and a rewiring layer 12 (ReDistribution Layer _, RDL layer).

The substrate 11 has a first surface (upper surface in fig. 1, or referred to as front surface) and a second surface (lower surface in fig. 1, or referred to as bottom surface) opposite to each other, and the substrate 11 has a plurality of through holes penetrating from the first surface to the second surface, each of which is filled with a conductive material, forming conductive through holes 111.

The substrate 11 has a groove 2 penetrating from the first surface to the second surface, the groove 2 dividing the substrate 11 into a plurality of connection areas (or sub-intermediaries) separated by the groove, one connection area being configured to connect one chip 3, the chip 3 being electrically connected with the conductive via 111 in the corresponding connection area.

The rewiring layer 12 is provided on the second surface, and the rewiring layer 12 has flexibility and is electrically connected to the conductive via 111.

The conductive via 111 in one connection region is electrically connected to the conductive via 111 in the other connection region through the rewiring layer 12 to realize interconnection of the chip 3 corresponding to the one connection region with the other chip 3 corresponding to the other connection region.

For example, the interposer 1 may be provided with first pads 13 on the front surface and second pads 14 on the back surface, and the interposer 1 is composed of the substrate 11 and the rewiring layer 12. The substrate 11 is provided with conductive through holes 111 in the thickness direction thereof, the front surface is connected with the chips 3 by bonding through first welding spots 13, the rewiring layer 12 is arranged on the back surface of the intermediate layer 1, the rewiring layer 12 is connected with the packaging substrate 4 by second welding spots 14, a plurality of chips 3 are stacked on the front surface of the intermediate layer 1 and are interconnected through the front surface lines (such as the conductive through holes 111 and the first welding spots 13) of the substrate 11 and the rewiring layer 12 on the back surface of the substrate 11, the grooves 2 are cut from the front surface of the intermediate layer 1 to the rewiring layer 12 along the gaps among the chips 3, the intermediate layer 1 is divided into a plurality of sub intermediate layers by the grooves 2, and the bottom surface RDL layers of the sub intermediate layers are connected. The bottom RDL layer is electrically connected to the conductive via 111 and the chip 3.

The conductive via 111 is disposed along the thickness direction (up-down direction in fig. 1) of the interposer 1, so that vertical interconnection of the interposer 1 can be realized, and the package height can be reduced.

For example, the substrate 11 may be made of silicon, or an inorganic material such as glass, siC, gaN, or the like, and when the substrate 11 is a silicon wafer, the conductive via 111 may be referred to as a Through Silicon Via (TSV). The substrate 11 is provided with conductive vias 111 along its thickness and the front surface is bonded to the chip 3, and the rewiring layer 12 may be connected to the package substrate 4 (e.g., PCB board) to form electrical interconnections. The chip 3 is laminated on the front side of the interposer 1, and interconnection is achieved through the front-side wiring of the substrate 11 and the back-side rewiring layer 12.

By slotting in the middle of the substrate 11, a stress buffering effect can be achieved on the substrate 11, and CTE mismatch problems caused by oversized substrate 11 and PCB interconnection and reliability processes are reduced. Even if there is a stress due to mismatch of thermal expansion coefficients, most of the stress can be further eliminated by the flexible rewiring layer 12, and the warpage problem of the large-sized package structure can be solved.

As shown in fig. 1 and 3, the grooves 2 are cut from the front surface of the interposer 1 to the rewiring layer 12 along the gaps between the chips 3, so that the substrate 11 is cut into sub-blocks, and the grooves 2 serve as stress buffers for the interposer 1 to the substrate 11/package substrate 4. The shape of the groove 2 may be a straight groove or a V-groove/trapezoid groove.

As shown in fig. 1, in one embodiment, the rewiring layer 12 may include a metal layer 121 or metal conductive line and a dielectric layer 122, where the dielectric layer 122 has flexibility, and the metal layer 121 is electrically connected to the conductive via 111, and the material of the dielectric layer 122 may be resin.

The rewiring layer 12 is disposed on the back surface of the interposer 1, and is made of metal conductive wires such as silver, copper, aluminum, gold, and the like, and resin polyimide, epoxy, acrylic, and the like. The embodiment of the application adopts the resin material as the dielectric layer 122, so that the dielectric layer 122 has flexibility, the metal layer 121 has ductility and elasticity, and the metal layer can be combined with the dielectric layer 122, so that the rewiring layer 12 has flexibility as a whole.

As shown in FIG. 1, in one embodiment, interposer 1 may further include a plurality of first pads 13, first pads 13 disposed on the first surface and electrically connected to conductive vias 111, first pads 13 configured to electrically connect to die 3. The front side of interposer 1 may be bonded to die 3 via first bond pads 13.

For example, the first solder joint 13 may include a first conductive bump 131 and a first solder ball 132, and by providing the first solder ball 132 on the first conductive bump 131, the flexible interposer 1 and the chip 3 package module may be electrically connected through the first solder ball 132, and the connection between the interposer 1 and the chip 3 may be more firm.

In some embodiments, the number of conductive vias 111 on each connection region is N, the number of corresponding first pads 13 is M, and the ratio of N to M may be 1:1, n:1, or 1:n. According to the actual arrangement of the solder joints or pins for connecting the chip 3, the first solder joints 13 are generally in one-to-one correspondence with the solder joints of the chip 3, but the conductive through holes 111 and the first solder joints 13 may not be in one-to-one correspondence, and at this time, a connection layer such as an interconnection layer may be arranged to realize connection. Thus, the interposer 1 may further include an interconnect layer disposed on the first surface between the first pad 13 and the substrate 11, the first pad 13 being electrically connected to the conductive via 111 through the interconnect layer. The interconnect layer may also include a metal layer and a dielectric layer, the metal layer making electrical connection of the first pads 13 with the conductive vias 111.

As shown in FIG. 1, in one embodiment, the interposer 1 may further include a plurality of second pads 14, the second pads 14 being disposed on a surface of the rewiring layer 12 remote from the substrate 11, the second pads 14 being electrically connected to the rewiring layer 12, the second pads 14 being configured to be electrically connected to the package substrate 4. The rewiring layer 12 may be connected to the package substrate 4 by a second pad 14 to form an electrical interconnection.

For example, the second pads 14 may include second conductive bumps 141 and second solder balls 142, the second pads 14 are formed on the back surface of the rewiring layer 12, the second solder balls 142 are disposed on the second conductive bumps 141, and the interposer 1 and the package substrate 4 may be electrically connected through the second solder balls 142.

The substrate 11 is provided with conductive through holes 111 along the thickness direction thereof, the front surface is connected with the chips 3 in a bonding way, the rewiring layer 12 is arranged on the back surface of the flexible intermediate layer 1, the rewiring layer 12 can be connected with the packaging substrate 4, a plurality of chips 3 can be stacked on the front surface of the intermediate layer 1 and interconnected through the front surface lines (such as the conductive through holes 111 and the first welding spots 13) of the substrate 11 and the rewiring layer 12 on the back surface of the substrate 11, the grooves 2 are cut from the front surface of the intermediate layer 1 to the rewiring layer 12 along the gaps among the chips 3, and the bottom surface RDL layers of all the sub intermediate layers are connected. Through slotting in the middle of the substrate 11, the substrate 11 can be subjected to stress buffering, and the problems of welding failure or material layering and the like generated in the processes of interconnection with a PCB and reliability due to oversized substrate 11 are reduced. Even if there is a stress due to mismatch of thermal expansion coefficients, most of the stress can be further eliminated by the flexible rewiring layer 12, and the warpage problem of the large-sized package structure can be solved.

Example two

As shown in fig. 2, the embodiment of the present application further provides a three-dimensional package structure 001, which may include a plurality of chips 3 and the interposer 1 described in the embodiment.

The plurality of chips 3 at least comprise a first chip and a second chip, wherein the first chip and the second chip are respectively attached to corresponding connection areas on the interposer, and the first chip and the second chip are electrically connected with the rewiring layer through conductive through holes 111 on the interposer.

The interposer 1 is composed of a substrate 11 and a rewiring layer 12. The substrate 11 is provided with conductive through holes 111 in its thickness direction, the front surface of which can be bonded to the chips 3 through first pads 13, the rewiring layer 12 is provided on the back surface of the interposer 1, the rewiring layer 12 is connected to the package substrate 4 through second pads 14, the plurality of chips 3 are laminated on the front surface of the interposer 1 and interconnected through the front-surface wiring of the substrate 11 and the rewiring layer 12 on the back surface of the substrate 11, the grooves 2 are cut from the front surface of the interposer 1 to the rewiring layer 12 along the gaps between the chips 3, the interposer 1 is divided into a plurality of sub-intermediaries (connection areas) by the grooves 2, and the bottom surface RDL layers of the respective sub-intermediaries are connected. The bottom RDL layer is electrically connected to the conductive vias 111 and the chips 3, and the chips 3 are interconnected by the front wiring and the back rewiring layer 12 of the substrate 11, so as to maintain signal transmission between the chips 3.

It should be noted that, the three-dimensional package structure 001 provided in the embodiment of the present application may further include a third chip, a fourth chip, and other chips. The third chip is used as an example, and the third chip can be interconnected with any one of the first chip and the second chip, or is interconnected with both the first chip and the second chip, or is not interconnected with both the first chip and the second chip, or is interconnected with the fourth chip. Therefore, the three-dimensional package structure 001 does not limit the number of specific chips 3, and does not limit the interconnection condition therein, so as to at least ensure that the first chip and the second chip are interconnected.

In one embodiment, the first chip may be a memory chip and the second chip may be a processing chip. The memory chip may be a memory chip such as HBM, DRAM (dynamic random access memory ), SDRAM (synchronous dynamic random access memory, synchronous dynamic random-access memory), etc., the processing chip may be an XPU, and the concept of XPU covers a plurality of different processor technologies, including CPU, GPU, FPGA, ASIC, etc., which are integrated into a unified architecture to adapt to specific computing requirements.

In one embodiment, as shown in fig. 2, the three-dimensional package structure 001 may further include a package substrate 4, where the package substrate 4 may be an organic substrate or a glass substrate, such as a PCB (printed circuit board ). The package substrate 4 may be printed or deposited with circuitry and the upper and lower surfaces may be formed with solder joints/pads. The interposer 1 may further include a plurality of second pads 14, the second pads 14 being disposed on a surface of the rewiring layer 12 remote from the substrate 11, the rewiring layer 12 being electrically connected to the package substrate 4 through the second pads 14.

In one embodiment, the three-dimensional package structure 001 may further include an insulating paste disposed between the substrate 11 and the chip 3, and the insulating paste wraps the pads/lands electrically connected between the substrate 11 and the chip 3. The underfill layer protects the pads/solder joints on the one hand and makes the connection between the chip 3 and the interposer 1 more secure on the other hand.

The grooves 2 are cut along the gaps between the chips 3 from the front side of the interposer 1 to the rewiring layer 12 so that the substrate 11 is cut into individual sub-blocks, the grooves 2 acting as stress buffers for the interposer 1 to the substrate 11. A flexible metal conductive rewiring layer 12 is provided between the substrate 11 and the package substrate 4. The plurality of substrates 11 may be electrically interconnected by the flexible metal conductive rewiring layer 12 while reducing stress due to CTE mismatch.

The first welding spots 13 are welded with the chip 3, so that the interposer 1 and the chip 3 are electrically connected, and meanwhile, the connection between the interposer 1 and the chip 3 is firmer. And can carry out the underfill between interposer 1 and chip 3, the underfill can protect the pad on the one hand, on the other hand can make the connection between chip 3 and interposer 1 more firm. The interposer 1 and the package substrate 4 may be electrically connected by the second pads 14. The interposer 1 is provided with conductive vias 111 along its thickness, and the conductive vias 111 enable vertical electrical interconnection of the flexible interposer 1 and effectively reduce package height.

The three-dimensional package structure 001 of the present embodiment also corresponds to the interposer 1 of the first embodiment, and will not be described again here.

Example III

As shown in fig. 4 and fig. 5, the embodiment of the present application further provides a method for manufacturing an interposer 1, which may be used to manufacture the interposer 1 described in the first embodiment, and may include:

Step 1, as shown in fig. 4 (a) and fig. 5 (a), a substrate 11 is provided, wherein the substrate 11 has a first surface and a second surface opposite to each other, the substrate 11 has a plurality of through holes penetrating from the first surface to the second surface, each through hole is filled with a conductive material to form a conductive through hole 111, a rewiring layer 12 is disposed on the second surface, the rewiring layer 12 has flexibility, and the rewiring layer 12 is electrically connected with the conductive through hole 111.

And 2, patterning the substrate 11 to form a groove 2, wherein the groove 2 penetrates from the first surface to the second surface, the groove 2 divides the substrate 11 into a plurality of connecting areas which are separated by the groove, one connecting area is configured to be connected with one chip 3, and the chip 3 is electrically connected with the conductive through holes 111 in the corresponding connecting areas.

In step 1, the substrate 11 may be pre-formed with the conductive via 111 and the rewiring layer 12, and may be pre-formed with the first pad 13 and the second pad 14. The method can also be prepared by the following steps:

Step 100, providing a substrate 11, and performing patterning treatment on the substrate 11 to form a plurality of through holes penetrating from the first surface to the second surface.

Step 101, filling conductive material in the through hole to form a conductive through hole 111.

Step 102, forming a plurality of first solder joints 13 on the first surface of the substrate 11.

Step 103, forming a rewiring layer 12 on the second surface of the substrate 11.

Step 104, forming a plurality of second pads 14 on the surface of the rewiring layer 12 away from the substrate 11. The order of steps 102 and 103 is not limited.

In step 2, as shown in fig. 4 (C) and fig. 5 (C), the groove 2 may be formed as a straight groove or a V groove according to different requirements. For example, the straight grooves may be opened by dry etching/laser grooving/mechanical grooving/wet etching, or the like. V-grooves are formed by wet etching.

Two specific implementation modes are provided for different groove 2 forms, and the process scheme of the straight groove is shown in fig. 4, and the specific steps are as follows:

In step 310, the interposer 1 is adhered to the carrier plate 51 by the temporary bonding adhesive 52 by using a temporary bonding method.

In step 320, as shown in fig. 4 (a) and (B), the photoresist 53 is coated on the interposer 1, and the photoresist 53 requiring the photolithography groove 54 is removed by means of exposure and development.

Step 330, as shown in fig. 4 (C), the depth of the trench is opened to the rewiring layer 12 by dry etching/laser grooving/mechanical grooving/wet etching or the like.

In step 340, as shown in fig. 4 (D), the photoresist 53 on the surface of the interposer 1 is removed by wet cleaning.

The process scheme for forming the V-shaped groove is shown in fig. 5, and comprises the following specific steps:

In step 410, the interposer 1 is adhered to the carrier plate 51 by the temporary bonding adhesive 52.

In step 420, as shown in fig. 5 (a) and (B), a photoresist 53 is coated on the interposer 1, and the photoresist 53 requiring the photolithography groove 54 is removed by means of exposure and development.

Step 430, as shown in fig. 5 (C), the groove is opened to the rewiring layer 12 by wet etching with the groove in the V-groove 55.

In step 440, as shown in fig. 5 (D), the photoresist 53 on the surface of the interposer 1 is removed by wet cleaning.

The manufacturing method of the present embodiment can prepare the interposer 1 of the first embodiment, and the technical effects of the interposer 1 of the first embodiment are corresponding to those of the interposer 1 of the first embodiment, and will not be repeated here.

Example IV

As shown in fig. 6, the embodiment of the present application further provides a method for manufacturing a three-dimensional package structure 001, which may be used to prepare the three-dimensional package structure 001 described in the second embodiment, and may include:

Step 10, the interposer 1 is prepared by the method for manufacturing the interposer 1 described in the third embodiment.

In step 20, at least two chips 3 are mounted on the connection area, where the at least two chips 3 include a first chip and a second chip, and the first chip and the second chip are electrically connected to the rewiring layer 12 through the conductive via 111, for example, a soldering manner is adopted to realize connection between the solder joint of the chip and the conductive via 111, so as to realize soldering between the solder joint of the chip and the first solder joint 13.

In step 30, the interposer 1 with the chip 3 is attached to the package substrate 4, and the package substrate 4 is electrically connected to the rewiring layer 12, for example, by soldering, so as to connect the solder joint of the package substrate 4 to the rewiring layer 12, and to solder the second solder joint 14 to the solder joint of the package substrate 4.

The following provides a specific embodiment, as shown in fig. 5, a method for manufacturing the three-dimensional package structure 001 may include:

In step 510, as shown in fig. 4 (a) and fig. 5 (a), the interposer 1 is bonded to the carrier plate 51 by the temporary bonding adhesive 52 by means of temporary bonding.

Step 520, as shown in fig. 6 (a), slots are formed in the interposer 1 in the manner shown in fig. 4 or 5, so that the interposer 1 is diced into different sub-blocks (connection regions).

In step 530, as shown in fig. 6B, the chip 3 is attached to each sub-interposer (connection region) through the first pads 13 on the front surface of the interposer 1.

In step 540, as shown in fig. 6 (C), the carrier plate 51 is removed by the unbinding method, and the temporary bonding glue 52 is removed by wet cleaning. After the interposer 1 is cleaned, the substrate 11 is diced.

In step 550, as shown in fig. 6 (D), the diced substrate 11 is mounted on the package substrate 4 through the second pads 14 on the back surface of the interposer 1.

The manufacturing method of the present embodiment can prepare the three-dimensional package structure 001 of the second embodiment, which corresponds to the technical effect of the three-dimensional package structure 001 of the second embodiment, and the description thereof will not be repeated here.

In summary, the interposer 1, the method for manufacturing the same, the three-dimensional package structure 001 and the method for manufacturing the same according to the present application have the substrate 11 provided with the conductive via 111 along the thickness direction thereof, the front surface thereof being bonded and connected to the chip 3 through the solder joint, the rewiring layer 12 provided on the back surface of the flexible interposer 1, the rewiring layer 12 being connected to the package substrate 4 through the solder joint, the plurality of chips 3 being laminated on the front surface of the interposer 1 and interconnected through the front surface circuit of the substrate 11 and the rewiring layer 12 on the back surface of the substrate 11, the grooves 2 being cut from the front surface of the interposer 1 to the rewiring layer 12 along the gaps between the chips 3, the bottom surface RDL layers of the respective sub-interposers being connected. By grooving the middle of the substrate 11, the substrate 11 can be subjected to stress buffering, and the problems of welding failure, material layering and the like caused by stress generated by mismatch of thermal expansion coefficients among the substrate 11, the bottom bump and the packaging substrate 4 are reduced. Even if there is a stress due to mismatch of thermal expansion coefficients, most of the stress can be further eliminated by the flexible rewiring layer 12, and the warpage problem of the large-sized package structure can be solved.

Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by a computer program. When all or part of the functions in the above embodiments are implemented by means of a computer program, the program may be stored in a computer-readable storage medium, which may include a read-only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to implement the functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above can be realized. In addition, when all or part of the functions in the above embodiments are implemented by means of a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and the program in the above embodiments may be implemented by downloading or copying the program into a memory of a local device or updating a version of a system of the local device, and when the program in the memory is executed by a processor.

Reference is made to various exemplary embodiments herein. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope herein. For example, the various operational steps and components used to perform the operational steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or combined into other steps) depending on the particular application or taking into account any number of cost functions associated with the operation of the system.

While the principles herein have been shown in various embodiments, many modifications of structure, arrangement, proportions, elements, materials, and components, which are particularly adapted to specific environments and operative requirements, may be used without departing from the principles and scope of the present disclosure. The above modifications and other changes or modifications are intended to be included within the scope of this document.

The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive in character, and all such modifications are intended to be included within the scope thereof. Also, advantages, other advantages, and solutions to problems have been described above with regard to various embodiments. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, system, article, or apparatus. Furthermore, the term "couple" and any other variants thereof are used herein to refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.

Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the invention. Accordingly, the scope of the invention should be determined only by the following claims.

Claims

1. An interposer, characterized in that it comprises: a substrate (11) and a redistribution layer (12);

The substrate (11) has a first surface and a second surface opposite to each other, and the substrate (11) has a plurality of through holes extending from the first surface to the second surface, each of the through holes being filled with a conductive material to form a conductive through hole (111);

The substrate (11) has a groove (2) extending from the first surface to the second surface, the groove (2) dividing the substrate (11) into a plurality of connection areas separated by the groove, one of the connection areas being configured to connect a chip (3), the chip (3) being electrically connected to the conductive through hole (111) in the corresponding connection area;

The rewiring layer (12) is arranged on the second surface, the rewiring layer (12) is flexible, and is electrically connected to the conductive through hole (111);

The conductive via (111) in one of the connection areas is electrically connected to the conductive via (111) in another of the connection areas through the rewiring layer (12), so as to interconnect the chip (3) corresponding to one of the connection areas with another chip (3) corresponding to another of the connection areas.

2. The interposer according to claim 1, characterized in that the rewiring layer (12) comprises a metal layer (121) and a dielectric layer (122), the dielectric layer (122) is flexible, the metal layer (121) is electrically connected to the conductive via (111), and the material of the dielectric layer (122) is resin.

3. The interposer according to claim 1, characterized in that the interposer (1) further comprises a plurality of first solder joints (13);

The first solder joint (13) is arranged on the first surface and is electrically connected to the conductive through hole (111), and the first solder joint (13) is configured to be electrically connected to the chip (3).

4. The interposer according to claim 1, characterized in that the interposer (1) further comprises a plurality of second solder joints (14);

The second solder joint (14) is arranged on a surface of the rewiring layer (12) away from the substrate (11), the second solder joint (14) is electrically connected to the rewiring layer (12), and the second solder joint (14) is configured to be electrically connected to the packaging substrate (4).

5. A three-dimensional packaging structure, characterized in that it comprises a plurality of chips (3) and an interposer (1) as claimed in claims 1 to 4;

The plurality of chips (3) include at least a first chip and a second chip;

The first chip and the second chip are respectively mounted on the corresponding connection areas on the intermediary layer, and the first chip and the second chip are electrically connected to the rewiring layer (12) through the conductive through-holes (111) on the intermediary layer.

6 . The three-dimensional packaging structure according to claim 5 , wherein the first chip is a storage chip and the second chip is a processing chip.

7. The three-dimensional packaging structure according to claim 5, characterized in that the three-dimensional packaging structure (001) further comprises a packaging substrate (4);

The intermediate layer (1) further comprises a plurality of second welding points (14);

The second solder joint (14) is arranged on a surface of the rewiring layer (12) away from the substrate (11), the second solder joint (14) is electrically connected to the rewiring layer (12), and the second solder joint (14) is electrically connected to the packaging substrate (4).

8. The three-dimensional packaging structure according to claim 5 is characterized in that the three-dimensional packaging structure (001) also includes insulating glue, which is arranged between the substrate (11) and the chip (3), and the insulating glue wraps the solder joints electrically connected between the substrate (11) and the chip (3).

9. A method for manufacturing an intermediate layer, characterized by comprising:

A substrate (11) is provided; wherein the substrate (11) has a first surface and a second surface opposite to each other; the substrate (11) has a plurality of through holes extending from the first surface to the second surface, each of the through holes being filled with a conductive material to form a conductive through hole (111); a rewiring layer (12) is arranged on the second surface, the rewiring layer (12) is flexible, and the rewiring layer (12) is electrically connected to the conductive through hole (111);

The substrate (11) is patterned to form a groove (2); wherein the groove (2) runs from the first surface to the second surface, and the groove (2) divides the substrate (11) into a plurality of connection areas separated by the grooves, and one of the connection areas is configured to connect a chip (3), and the chip (3) is electrically connected to the conductive through hole (111) in the corresponding connection area.

10. A method for manufacturing a three-dimensional packaging structure, comprising:

The intermediary layer (1) is prepared by adopting the method for manufacturing the intermediary layer (1) according to claim 9;

Mounting at least two chips (3) to the corresponding connection areas, the at least two chips (3) comprising a first chip and a second chip, the first chip and the second chip being electrically connected to the rewiring layer (12) via the conductive through-hole (111);

The interposer (1) with the chip (3) is mounted on a packaging substrate (4), and the packaging substrate (4) is electrically connected to the redistribution layer (12).