CN220474621U - Circuit carrier boards and electronic packages - Google Patents

Abstract

The utility model discloses a circuit carrier board and an electronic package, wherein the circuit carrier board is suitable for mounting multiple chip components. The circuit carrier board includes multiple circuit sub-boards, an adhesive layer and a redistribution circuit structure. The sealant layer covers these circuit sub-boards and fills the gaps between these circuit sub-boards. One side of the sealant layer exposes one side of each of these circuit daughter boards. The redistribution circuit structure is disposed on the side of the sealant layer that is far away from the circuit sub-boards and is suitable for mounting the chip components thereon, so that the chip components are electrically connected to the circuit sub-boards through the redistribution circuit structure.

Description

Circuit carrier boards and electronic packages

Technical field

The utility model relates to an electronic component, and in particular to a circuit carrier board and an electronic package.

Background technique

Circuit carriers for chip packaging are used to secure integrated circuit (IC) chips and serve as a medium for electrical connection to other electronic components. Depending on whether it has a dielectric core, circuit carrier boards can be divided into core types and coreless types. In the case of multi-chip packaging, a large size circuit carrier board is required. However, large-size circuit carrier boards have low layout utilization and yield during mass production, which increases production costs.

Utility model content

The utility model provides a circuit carrier board to reduce production costs.

The utility model provides an electronic package to reduce production costs.

A circuit carrier board according to an embodiment of the present invention is suitable for mounting multiple chip components. The circuit carrier board includes multiple circuit sub-boards, an adhesive layer and a redistribution circuit structure. The sealant layer covers these circuit sub-boards and fills the gaps between these circuit sub-boards. One side of the sealant layer exposes one side of each of these circuit daughter boards. The redistribution circuit structure is disposed on a side of the sealant layer that is far away from the circuit sub-boards and is suitable for mounting the chip components thereon, so that the chip components are electrically connected to the circuit sub-boards through the redistribution circuit structure.

In an embodiment of the present invention, the chip components are electrically connected to each other through the redistribution wiring structure.

In an embodiment of the present invention, the circuit daughter boards are electrically connected to each other through the redistribution circuit structure.

In one embodiment of the present invention, the redistribution circuit structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards.

In an embodiment of the present invention, the rectangular sizes of the circuit sub-boards are different.

In an embodiment of the present invention, the circuit sub-boards have different thicknesses.

In an embodiment of the present invention, the circuit sub-boards in the sealant layer are insulated from each other.

In an embodiment of the present invention, the circuit carrier board further includes: a circuit substrate, and the circuit sub-boards are installed on the circuit substrate to be electrically connected to the circuit substrate.

An electronic package according to an embodiment of the present invention includes a plurality of chip components and a circuit carrier board. The circuit carrier board includes multiple circuit sub-boards, an adhesive layer and a redistribution circuit structure. The sealant layer covers these circuit sub-boards and fills the gaps between these circuit sub-boards. One side of the sealant layer exposes one side of each of these circuit daughter boards. The redistribution circuit structure is disposed on the side of the sealant layer that is far away from the circuit sub-boards and allows the chip components to be mounted thereon, so that the chip components are electrically connected to the circuit sub-boards through the redistribution circuit structure.

In an embodiment of the present invention, the chip components are electrically connected to each other through the redistribution wiring structure.

In an embodiment of the present invention, one of the chip components is a bare chip or a chip package.

In an embodiment of the present invention, the chip components are electrically connected to each other through the redistribution wiring structure.

In an embodiment of the present invention, the circuit daughter boards are electrically connected to each other through the redistribution circuit structure.

In one embodiment of the present invention, the redistribution circuit structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards.

In an embodiment of the present invention, the rectangular sizes of the circuit sub-boards are different.

In an embodiment of the present invention, the circuit sub-boards have different thicknesses.

In an embodiment of the present invention, the circuit sub-boards in the sealant layer are insulated from each other.

In one embodiment of the present invention, the electronic package further includes a protective cover, which is installed on the redistribution circuit structure and covers the chip components.

In one embodiment of the present invention, the protective cover has a heat dissipation function.

In one embodiment of the present invention, the electronic package further includes a chip encapsulant, which is disposed on the redistribution circuit structure and fills the gaps between the chip components.

In one embodiment of the present invention, the circuit carrier board also includes a circuit substrate, and the circuit sub-boards are installed on the circuit substrate.

Based on the above, the advantage of the present invention is that multiple circuit sub-boards are covered with a sealant layer and a redistributed circuit structure is arranged on the sealant layer to electrically connect these circuit sub-boards. Compared with large-sized circuit carrier boards traditionally used for chip packaging, small-sized circuit carrier boards have significantly higher layout utilization and yield rates. Therefore, in this case, a small-sized circuit carrier board is used as a circuit sub-board to form a large-sized circuit carrier board, which can also reduce production costs.

Description of drawings

Figure 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the present invention;

Figure 2A is a schematic top view of an arrangement of chip components, circuit sub-boards and redistribution circuit structures of the electronic package of Figure 1;

Figure 2B is a schematic top view of another arrangement of chip components, circuit sub-boards and redistribution circuit structures of the electronic package of Figure 1;

Figure 2C is a schematic top view of another arrangement of chip components, circuit sub-boards and redistribution circuit structures of the electronic package of Figure 1;

Figure 3 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention;

Figure 4 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention;

Figure 5 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention;

Figure 6 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention;

7A to 7F are schematic diagrams of a method for manufacturing an electronic structure according to another embodiment of the present invention;

Figure 8 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the present invention;

Figure 9 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the present invention.

Symbol Description

50: Electronic package

51: Chip components

52: Protective cover

52a: Chip sealant

53: Conductive bumps

53a: Pre-connected pad

100: Line carrier board

110, 110a, 110b: Line daughter board

112: Daughter board dielectric layer

114: Daughter board patterned conductive layer

116: Daughter board conductive via

120: Sealing layer

130: Rewiring the line structure

132: Redistribution of dielectric layer

134, 134a: Redistribution of patterned conductive layer

136: Redistribution of conductive channels

140: Daughter board conductive ball

150: Circuit substrate

160: Substrate conductive ball

202: Temporary joint layer

204: Temporary vehicle

P: conductive pad

Detailed ways

Please refer to FIG. 1 . In this embodiment, the electronic package 50 includes a plurality of chip components 51 and a circuit carrier board 100 . These chip components 51 are, for example, integrated circuit bare chips or small chip packages (such as multi-chip packages, stacked chip packages, chip-size packages, etc.). These chip components 51 are mounted to the circuit carrier board 100 , for example via conductive bumps 53 .

In this embodiment, the circuit carrier board 100 includes a plurality of circuit sub-boards 110, an adhesive layer 120 and a redistribution circuit structure 130. The sealant layer 120 covers the circuit sub-boards 110 and fills the gaps between the circuit sub-boards 110, that is, the circuit sub-boards 110 in the sealant layer 120 are insulated from each other. One side of the sealant layer 120 exposes one side of each of these circuit sub-boards 110 to connect to the next level of electronic components (such as a motherboard or a module board, etc.). The redistribution circuit structure 130 is disposed on the side of the sealant layer 120 that is far away from the circuit sub-boards 110 and allows the chip components 51 to be mounted thereon, so that the chip components 51 are electrically connected to the circuit sub-boards 110 through the redistribution circuit structure 130 . Because the circuit sub-boards 110 in the sealant layer 120 are insulated from each other and cannot be directly electrically connected in the sealant layer 120 , the circuit sub-boards 110 can be electrically connected to each other through the redistribution circuit structure 130 . In addition, these circuit sub-boards 110 can be mounted to next-level electronic components, such as a motherboard or a module board, via a plurality of sub-board conductive balls 140 .

In this embodiment, each circuit sub-board 110 may include a plurality of sub-board dielectric layers 112 , a plurality of sub-board patterned conductive layers 114 and a plurality of sub-board conductive vias 116 . The sub-board patterned conductive layers 114 and the sub-board dielectric layers 112 are alternately laminated. The sub-board conductive vias 116 are respectively connected to the sub-board patterned conductive layers 114 . In addition, the redistribution circuit structure 130 may include a plurality of redistribution dielectric layers 132 , a plurality of redistribution patterned conductive layers 134 and a plurality of redistribution conductive vias 136 . The redistributed patterned conductive layers 134 and the redistributed dielectric layers 132 are alternately overlapped. The redistribution conductive channels 136 are respectively connected to the redistribution patterned conductive layers 134 . In one embodiment, the redistribution circuit structure 130 further includes a redistribution patterned conductive layer 134a, which can directly electrically connect at least two circuit sub-boards 110 to transmit signals. In addition, these chip components 51 may also be electrically connected to each other via the redistribution wiring structure 130 to transmit signals.

Please refer to FIG. 2A, FIG. 2B, and FIG. 2C. These chip components 51 and these circuit daughter boards 110 are arranged within the scope of the redistribution circuit structure 130. These circuit sub-boards 110 may be in a rectangular shape, and their lengths and widths may be equal or unequal. The rectangular dimensions of these circuit daughter boards 110 may vary. These circuit sub-boards 110 may be arranged in an area array or in a linear arrangement. In addition, some chip components 51 may be located on corresponding circuit sub-boards 110 respectively, and some chip components 51 may be located on multiple circuit sub-boards 110 at the same time, that is, at least spanning two adjacent circuit sub-boards 110 .

Please refer to FIG. 3. Compared with the electronic package 50 of FIG. 1, the circuit sub-board 110a of the electronic package 50 of FIG. There is no difference in the thickness of these circuit sub-boards 110 in 1, and they can be the same type of circuit sub-boards. Please refer to FIG. 4 . Compared with the electronic package 50 of FIG. 1 , the circuit sub-board 110 and the circuit sub-board 110 b of the electronic package 50 of FIG. 4 may be of different types. For example, the circuit sub-board 110 is a core-less circuit board, and the circuit sub-board 110b may be a core-based circuit board. In other words, in different embodiments, the thickness or type of circuit sub-boards can be selected and combined according to different requirements.

Please refer to FIG. 1 again. In this embodiment, the electronic package 50 may also include a protective cover 52 or other components with a heat dissipation function. The protective cover 52 may also have a heat dissipation function. The protective cover 52 is installed on the redistribution wiring structure 130 and covers the chip components 51 . In addition, please refer to FIG. 5. Compared with the embodiment of FIG. 1, the electronic package 50 of FIG. In one embodiment, the chip encapsulant 52a will expose the backside (non-active side) of these chip components 51. In addition, please refer to FIG. 6. Compared with the embodiment of FIG. 1, the circuit carrier board 100 of the electronic package 50 of FIG. The sub-board 110 may be mounted on the circuit substrate 150 via a plurality of sub-board conductive balls 140 . In addition, the circuit substrate 150 can be mounted to a next-level electronic component, such as a motherboard or a module board, via a plurality of substrate conductive balls 160 .

A method of manufacturing an electronic structure according to another embodiment of the present invention will be described below with reference to FIGS. 7A to 7F .

Referring to FIG. 7A , a plurality of circuit daughter boards 110 are fixed to a temporary carrier 204 via a temporary bonding layer 202 . In this embodiment, the circuit sub-board 110 has a plurality of conductive pads P. In one embodiment, the conductive pad P is made of copper and includes a bottom copper pad and an upper copper pillar.

Referring to FIG. 7B , a sealant layer 120 is formed to cover the temporary bonding layer 202 and the circuit sub-boards 110 . The sealant layer 120 fills the gaps between the circuit sub-boards 110 . In other words, the circuit sub-boards 110 in the sealant layer 120 are insulated from each other and cannot be directly electrically connected in the sealant layer 120 . In this embodiment, the sealant layer 120 also covers these conductive pads P.

Referring to FIG. 7C , a portion of the sealant layer 120 is removed to expose a portion of each of the conductive pads P, for example, the top surface of the conductive pad P is exposed. This step can flatten the surface of the electronic structure to facilitate subsequent steps.

Referring to FIG. 7D , a redistribution circuit structure 130 is formed on the sealant layer 120 , wherein the redistribution circuit structure 130 is electrically connected to the circuit sub-boards 110 . In this embodiment, a plurality of redistribution conductive channels 136 and a redistribution patterned conductive layer 134 of the redistribution circuit structure 130 are made from the top surfaces of the conductive pads P to electrically connect with the circuit sub-boards 110 . In one embodiment, the redistribution circuit structure 130 further includes a redistribution patterned conductive layer 134a, which can directly electrically connect at least two circuit sub-boards 110. In addition, pre-connection pads 53a may be formed on the redistribution patterned conductive layer 134 of the redistribution wiring structure 130, and may later be used to connect other components. In another embodiment not shown, the temporary bonding layer 202 and the temporary carrier 204 can be removed to form the circuit carrier board 100 of FIG. 8 . Then, these circuit sub-boards 110 can be mounted on the circuit substrate 150 of FIG. 6 to form the circuit carrier board 100 of FIG. 9 .

Referring to FIG. 7E , a plurality of chip components 51 are mounted on the redistribution wiring structure 130 so that the chip components 51 are electrically connected to the circuit daughter boards 110 via the redistribution wiring structure 130 . In addition, these chip components 51 may also be electrically connected to each other via the redistribution wiring structure 130 . In this embodiment, these chip components 51 can be connected to the pre-connection pads 53 a of the redistribution wiring structure 130 via a plurality of conductive bumps 53 . In another not-shown embodiment, a protective cover 52 as shown in FIG. 1 can be installed on the redistribution wiring structure 130 in FIG. 7E and cover the chip components 51 . In another not-shown embodiment, a chip encapsulant 52a as shown in FIG. 5 can be formed on the redistribution wiring structure 130 in FIG. 7E to cover the chip components 51 and expose the back surfaces of the chip components 51 .

Referring to FIG. 7F , the temporary bonding layer 202 and the temporary carrier 204 of FIG. 7E are removed to expose the circuit daughter boards 110 . In another not-shown embodiment, these circuit sub-boards 110 can be mounted on the circuit substrate 150 of FIG. 6 .

To sum up, multiple circuit sub-boards are covered with a sealant layer and a redistributed circuit structure is configured on the sealant layer to electrically connect these circuit sub-boards. Compared with traditional large-size circuit carrier boards used for chip packaging, which have a lower yield rate, small-size circuit carrier boards have significantly higher layout utilization and yield rates. Therefore, in this case, a small-sized circuit carrier board is used as a circuit sub-board to form a large-sized circuit carrier board, which can reduce production costs.

Claims (21)

1. A circuit carrier adapted to mount a plurality of chip components, the circuit carrier comprising:

a plurality of line sub-boards;

a sealing layer covering the circuit sub-boards and filling gaps among the circuit sub-boards, wherein one surface of the sealing layer exposes one surface of each of the circuit sub-boards; and

and the re-wiring circuit structure is arranged on one surface of the sealing adhesive layer, which is far away from the circuit sub-boards, and is suitable for the chip elements to be installed on, so that the chip elements are electrically connected with the circuit sub-boards through the re-wiring circuit structure.

2. The circuit carrier of claim 1, wherein the chip components are electrically connected to each other via the redistribution circuit structure.

3. The circuit carrier of claim 1, wherein the circuit sub-boards are electrically connected to each other via the redistribution circuit structure.

4. The circuit carrier of claim 3, wherein the redistribution circuit structure comprises a redistribution patterned conductive layer, and wherein the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards.

5. The circuit carrier of claim 1, wherein the rectangular dimensions of the circuit sub-boards are different.

6. The circuit carrier of claim 1, wherein the plurality of circuit sub-boards have different thicknesses.

7. The circuit carrier of claim 1, wherein the plurality of circuit sub-boards in the encapsulation layer are insulated from each other.

8. The circuit carrier of claim 1, further comprising:

and the circuit substrates are arranged on the circuit substrates and are electrically connected with the circuit substrates.

9. An electronic package, comprising:

a plurality of chip elements; and

a circuit carrier board comprising:

a plurality of line sub-boards;

a sealing layer covering the circuit sub-boards and filling gaps among the circuit sub-boards, wherein one surface of the sealing layer exposes one surface of each of the circuit sub-boards; and

and the re-wiring circuit structure is arranged on one surface of the sealing adhesive layer, which is far away from the circuit sub-boards, and is used for mounting the chip elements thereon, so that the chip elements are electrically connected with the circuit sub-boards through the re-wiring circuit structure.

10. The electronic package of claim 9, wherein the chip components are electrically connected to each other via the redistribution circuit structure.

11. The electronic package of claim 9, wherein one of the chip components is a bare chip or a chip package.

12. The electronic package of claim 11, wherein the chip components are electrically connected to each other via the redistribution circuit structure.

13. The electronic package of claim 9, wherein the plurality of circuit sub-boards are electrically connected to each other via the redistribution circuit structure.

14. The electronic package of claim 13, wherein the redistribution circuit structure comprises a redistribution patterned conductive layer, and wherein the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards.

15. The electronic package of claim 9, wherein the rectangular dimensions of the circuit sub-boards are different.

16. The electronic package of claim 9, wherein the plurality of circuit sub-boards have different thicknesses.

17. The electronic package of claim 9, wherein the plurality of circuit sub-boards in the encapsulant layer are insulated from each other.

18. The electronic package of claim 9, further comprising:

and a protective cover mounted on the rerouting circuit structure and covering the chip elements.

19. The electronic package of claim 18, wherein the protective cover has a heat dissipation function.

20. The electronic package of claim 9, further comprising:

and the chip sealing glue is arranged on the rerouting circuit structure and fills the gap between the chip elements.

21. The electronic package of claim 9, wherein the circuit carrier further comprises:

and the circuit substrates are arranged on the circuit substrates.