CN119479751A - Resistance test structure of flash memory and forming method thereof - Google Patents
Resistance test structure of flash memory and forming method thereof Download PDFInfo
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Abstract
The invention provides a resistance test structure of a flash memory and a forming method thereof, comprising that N rows of word lines are formed on a provided substrate, and a row of control gates are distributed on two sides of each row of word lines along the column direction; the two rows of control grids on two sides of each row of word lines are connected with each other along the ends of the two control grids on one side of the two rows of word lines, the ends of the two control grids on the other side of the two control grids are disconnected with each other, the first row of control grids are electrically connected with the first end metal layer, the two rows of control grids between every two adjacent rows of word lines are electrically connected with each other through the middle metal layer, and the last row of control grids are electrically connected with the tail end metal layer. The two rows of control gates on both sides of each row of word lines are themselves interconnected without the need for an additional metal layer. Control grids on two sides of each of the N rows of word lines are sequentially connected in series through plugs in the metal layers and the contact holes, so that a test structure is simplified, and disconnection of a control grid series connection passage is avoided. The test structure is simple, the wafer is easy to accept and test, the influence of process and test fluctuation is smaller, and the test result is more stable.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a resistance test structure of a flash memory and a forming method thereof.
Background
FLASH memory (FLASH) has become a mainstream of nonvolatile semiconductor memory technology. The FLASH can not only program, erase and read data by an electrical method, but also retain data in the power interruption process, has the advantages of high access speed, light weight, large capacity, small size of an access device and the like, and is widely applied to various electronic products such as smart cards, SIM cards (subscriber identity cards), microcontrollers, mobile phones and the like.
The control gate square resistance of the flash memory is an important parameter in the acceptance test of the flash memory wafer, the existing flash memory test structure has problems, and the phenomenon of disconnection in the control gate serial connection passage often occurs due to unstable test results.
Disclosure of Invention
The invention aims to provide a resistance test structure of a flash memory and a forming method thereof, wherein the two rows of control gates on two sides of each row of word lines are connected with each other without an additional metal layer. The control gates on the two sides of each of the N rows of word lines are sequentially connected in series through the metal layer and the plugs in the contact holes to form a resistance test path of the control gates. The test structure is simple, the wafer is easy to accept and test, the influence of process and test fluctuation is smaller, and the test result is more stable.
The invention provides a resistance test structure of a flash memory, which comprises the following components:
step S1, providing a substrate, wherein N rows of word lines are formed on the substrate, and are distributed in parallel along the row direction, and one row of control gates are distributed on two sides of each row of word lines along the column direction;
s2, forming a dielectric layer, wherein the dielectric layer covers the control gate layer, the word lines and the substrate, forming contact holes in the dielectric layer, and arranging the contact holes on one side, far away from the word lines, of each control gate on two sides of each row of word lines in the column direction;
And S3, forming a metal layer on the dielectric layer, wherein the metal layer comprises a head end metal layer, a middle metal layer and a tail end metal layer, the control gates in the first row are electrically connected with the head end metal layer, the control gates in the two rows between every two adjacent rows of word lines are electrically connected through the middle metal layer, the control gates in the last row are electrically connected with the tail end metal layer, and the control gates on two sides of each N rows of word lines are sequentially connected in series through plugs in the metal layer and the contact holes to form a resistance test path of the control gates.
Further, the step S1 specifically includes:
s11, forming a floating gate material layer and a control gate material layer on the substrate in sequence;
s12, patterning the control gate material layer and the floating gate material layer by using a floating gate correction mask plate, forming N rows of floating gate patterns distributed at intervals, wherein the control gate material layer and the floating gate material layer in the area where the floating gate patterns are located are reserved;
s13, etching and removing the control gate material layer and the floating gate material layer in the middle area of each row of floating gate patterns to form an opening, and forming a word line in the opening;
And S14, etching and removing one of two sides of each row of floating gate patterns along the row direction, so that the ends of the two control gates on one side are connected with each other, and the ends of the two control gates on the other side are disconnected with each other.
Furthermore, in the floating gate correction mask, correction patterns are arranged at two corner positions, which correspond to the two rows of control gates on two sides of each row of word lines and are connected with each other, and the floating gate correction mask is obtained by taking the floating gate patterns as target patterns and combining the target patterns with the correction patterns.
Further, the floating gate pattern is rectangular in a top view, and the correction pattern is square or rectangular.
Further, two control gates on two sides of each row of word lines extend out of an extension block on one side, away from the word lines, of each control gate in the column direction, and the control gate material layer and the floating gate material layer in the area where the extension block is located remain;
The projection of the contact hole on the substrate falls into the projection of the extension block on the substrate, and the bottom of the plug in the contact hole is electrically connected with the extension block.
The invention also provides a resistance test structure of the flash memory, which comprises the following components:
The semiconductor device comprises a substrate, wherein N rows of word lines are formed on the substrate, the N rows of word lines are distributed in parallel along the row direction, and a row of control grids are distributed on two sides of each row of word lines along the column direction;
the control grid comprises a substrate, a dielectric layer, contact holes, two control grids, a plurality of word lines, a plurality of control gates and a plurality of control gates, wherein the dielectric layer covers the control gates, the word lines and the substrate;
The metal layer comprises a head end metal layer, a middle metal layer and a tail end metal layer, wherein the first row of control gates are electrically connected with the head end metal layer, two rows of control gates between every two adjacent rows of word lines are electrically connected through the middle metal layer, the last row of control gates are electrically connected with the tail end metal layer, and the control gates on two sides of each N rows of word lines are sequentially connected in series through plugs in the metal layer and the contact holes to form a resistance test path of the control gates.
Further, two sides of the control gate along the row direction are defined as a first side and a second side, respectively.
Further, the ends of the control gates of two rows on both sides of the column direction of each row of the word line are connected to each other on the first side, and are disconnected from each other on the second side.
Further, the ends of the control gates of the two rows on both sides of the column direction of the word line of the odd rows are connected with each other on the first side, and are disconnected with each other on the second side;
The ends of the control gates of the two rows on the two sides of the word line in the column direction of the even-numbered rows are disconnected from each other on the first side, and are connected to each other on the second side.
Further, in the resistance test path of the control gate, the resistance R between the head end metal layer and the end metal layer is measured, the total length of all the control gates is L, the width of the control gate is W, the square resistance of the control gate is Rs, and rs=r×w/L.
Compared with the prior art, the invention has the following beneficial effects:
The invention provides a resistance test structure of a flash memory and a forming method thereof, comprising the steps of providing a substrate, forming N rows of word lines which are distributed in parallel along the row direction on the substrate, wherein each row of word lines is distributed with one row of control gates along the column direction, the ends of two control gates on one side of each row of word lines are connected with each other in two sides of each row of word lines along the row direction, the ends of two control gates on the other side of each row of word lines are disconnected with each other, forming a dielectric layer which covers the control gate layer, the word lines and the substrate, forming contact holes in the dielectric layer, forming contact holes on one side, far away from the word lines, of each control gate on the two sides of each row of word lines in the column direction, of each control gate on the dielectric layer, forming a metal layer which comprises a first end metal layer, a middle metal layer and a tail end metal layer, wherein the first row of control gates are electrically connected with the first end metal layer, the two rows of control gates between each two adjacent rows of word lines are electrically connected with the tail end metal layer through the middle metal layer, and the last row of control gates are electrically connected with the tail end metal layer.
According to the invention, the two rows of control gates on two sides of each row of word lines are connected with each other without an additional metal layer. The control gates on the two sides of each of the N rows of word lines are sequentially connected in series through the metal layer and the plugs in the contact holes to form a resistance test path of the control gates. The test structure is simple, the wafer is easy to accept and test, the influence of process and test fluctuation is smaller, and the test result is more stable.
Furthermore, in the floating gate correction mask, correction patterns are arranged at two corner positions, which correspond to the two rows of control gates on two sides of each row of word lines and are connected with each other, and the floating gate correction mask is obtained by taking the floating gate patterns as target patterns and combining the target patterns with the correction patterns. And (3) through optical proximity effect correction of the floating gate correction mask, the control gate structures at two corners where the control gates of two rows on two sides of each row of word lines are connected with each other are regular and uniform, and the resistance of the control gate at the corners is uniform and stable.
Drawings
FIG. 1 is a schematic diagram of a resistance test structure of a flash memory.
FIG. 2 is a flow chart of a method for forming a resistance test structure of a flash memory according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a floating gate correction mask used in a method for forming a resistance test structure of a flash memory according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a first example of a resistance test structure of a flash memory according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a second example of a resistance test structure of a flash memory according to an embodiment of the present invention.
Wherein, the reference numerals are as follows:
01-word line, 02-control gate, 03-metal layer, 04-contact hole;
11-word lines, 12, 22-control gates, 131-head end metal layer, 132-middle metal layer, 133-end metal layer, 14-contact holes, F-floating gate pattern, 120-target pattern, 121-correction pattern.
Detailed Description
As described in the background art, the unstable test result of the square resistance of the control gate of the flash memory often has the phenomenon of disconnection in the serial path of the control gate.
As shown in fig. 1, in a resistance test structure of a flash memory, a control gate series path structure is complex. For example, signals of the control gate can be led out through vertical connection of more than 1 or 2 contact holes 04 in the thickness direction of the flash memory, the connection positions of the contact holes are complex in structure and small in size, the results of process and test fluctuation and the like are greatly affected, the test result is often open circuit (broken), and the real condition of the resistance of the control gate cannot be monitored. In addition, in the plane parallel to the upper surface of the flash memory, the control gates 02 on both sides of each word line 01 are disconnected, and an additional metal layer 03 is needed to realize connection across two rows of control gates 02. Whether the vertical metal connection in the thickness direction of the flash memory is problematic or the parallel connection of the metal layer in the plane parallel to the upper surface of the flash memory is problematic, the control gate sheet resistance test fails.
Based on the above study, the invention provides a resistance test structure of a flash memory and a forming method thereof. The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the invention.
For ease of description, some embodiments of the application may use spatially relative terms, such as "above," "below," "top," "below," and the like, to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
The invention provides a method for forming a resistance test structure of a flash memory, as shown in fig. 2, comprising the following steps:
Step S1, providing a substrate, wherein N rows of word lines are formed on the substrate, wherein the N rows of word lines are distributed in parallel along the row direction, and one row of control gates are distributed on two sides of each row of word lines along the column direction;
S2, forming a dielectric layer, wherein the dielectric layer covers the control gate layer, the word lines and the substrate, and forming contact holes in the dielectric layer;
And S3, forming a metal layer on the dielectric layer, wherein the metal layer comprises a head end metal layer, a middle metal layer and a tail end metal layer, the first row of control gates are electrically connected with the head end metal layer, the two rows of control gates between every two adjacent rows of word lines are electrically connected through the middle metal layer, the last row of control gates are electrically connected with the tail end metal layer, and the control gates on two sides of each N rows of word lines are sequentially connected in series through the head end metal layer, plugs in the contact holes, the middle metal layer and the tail end metal layer to form a control gate resistance test path.
The following describes in detail the steps of the method for manufacturing the resistance test structure of the flash memory according to the embodiment of the invention with reference to the accompanying drawings.
FIG. 3 is a schematic top view of a floating gate correction mask used in the method for forming a resistance test structure of a flash memory according to an embodiment of the present invention. Fig. 4 is a schematic top view of a first example of a resistance test structure of a flash memory according to an embodiment of the present invention. As shown in fig. 3 and 4, step S1 specifically includes:
S11, forming a floating gate material layer and a control gate material layer on a substrate in sequence;
S12, patterning the control gate material layer and the floating gate material layer by using a floating gate correction mask plate, forming N rows of floating gate patterns F distributed at intervals, wherein the control gate material layer and the floating gate material layer in the region where the floating gate patterns F are located remain;
S13, etching and removing the control gate material layer and the floating gate material layer in the middle area of each row of floating gate patterns F to form an opening, and forming a word line 11 in the opening;
And S14, etching and removing one of two sides of each row of floating gate patterns F along the row direction, so that the ends of the two control gates 12 on one side are connected with each other, and the ends of the two control gates 12 on the other side are disconnected with each other.
The floating gate correction mask in step S12 adopts optical proximity correction (OPC, optical Proximity Correction). As integrated circuit fabrication technology advances toward higher integration and smaller feature sizes, photolithographic techniques have become a critical factor limiting the advancement of integrated circuits toward smaller feature sizes. The main task of the photoetching process is to transfer the design layout of the integrated circuit from the mask plate to the surface of the silicon wafer. However, as the feature size is reduced, the interference and diffraction effects of light cause great difference between the actual pattern generated by photoetching on the silicon wafer and the ideal pattern of the design layout, and the pattern transfer distortion of the mask plate affects the performance and the yield of the circuit.
The optical proximity effect correction is a method for correcting the design layout of a circuit in advance to compensate defects caused by interference and diffraction effects of light, and transferring a corrected pattern from a mask plate to the surface of a silicon wafer so as to meet the requirement of an exposure process. And correcting the formation correction pattern of a certain specific layer of the semiconductor by adopting optical proximity effect correction. The target pattern to be exposed on the semiconductor substrate of the wafer is calculated and corrected by using computer and software operation to obtain a corrected mask pattern different from the target pattern, and then the corrected mask pattern is manufactured on the mask, and the pattern projected on the semiconductor substrate by the light beam through the mask can be almost the same as the target pattern.
As shown in fig. 3 and fig. 4, in the floating gate correction mask, correction patterns 121 are disposed at two corner positions corresponding to the interconnection of the two rows of control gates 12 at both sides of each row of word lines 11, and the floating gate pattern F is taken as a target pattern 120, and the target pattern 120 is combined with the correction patterns 121 to obtain the floating gate correction mask. The control grid 11 at the corner is regular and uniform in structure, and the resistance of the control grid 11 at the corner is uniform and stable. The target pattern 120 is rectangular in plan view, and the corrected pattern 121 is square or rectangular. The two control gates 12 on both sides of each row of word lines 11 extend out of the extension block 15 on the side away from the word lines 11 in the column direction, the control gate material layer and the floating gate material layer in the area where the extension block is located remain, and the control gate 12 and the extension block 15 are formed by the control gate material layer. The projection of the contact hole 14 on the substrate falls into the projection of the extension block 15 on the substrate, and the bottom of the plug in the contact hole 14 is electrically connected with the extension block 15.
The invention also provides a resistance test structure of the flash memory, which comprises the following components:
the semiconductor device comprises a substrate, wherein N rows of word lines 11 are formed on the substrate, the N rows of word lines 11 are distributed in parallel along the row direction, and one row of control gates 12 are distributed on two sides of each row of word lines 11 along the column direction;
The semiconductor device comprises a control grid, word lines 11, a substrate, a dielectric layer, contact holes 14, two control grids 12, a contact hole 14 and a first electrode, wherein the dielectric layer covers the control grid, the word lines 11 and the substrate;
the metal layer is positioned on the dielectric layer and comprises a head end metal layer 131, a middle metal layer 132 and a tail end metal layer 133, wherein the first row of control gates are electrically connected with the head end metal layer 131, the two rows of control gates between every two adjacent rows of word lines are electrically connected through the middle metal layer 132, the last row of control gates are electrically connected with the tail end metal layer 133, and the control gates on two sides of each N rows of word lines are sequentially connected in series through the metal layer and plugs in the contact holes 14, namely, the control gates of the whole test memory cell array are connected in series to form a resistance test path of the control gates. The row direction and the column direction are perpendicular. The two sides of the control gate in the row direction are defined as a first side and a second side, respectively. A floating gate may be formed directly under the control gate.
In one example, as shown in fig. 4, the ends of the two rows of control gates 12 on both sides in the column direction of each row of word lines 11 are connected to each other on the first side (left side) and disconnected from each other on the second side (right side).
In another example, as shown in fig. 5, the ends of the two rows of control gates 22 on both sides in the column direction of the odd-numbered row word line 11 are connected to each other on the first side (left) and disconnected from each other on the second side (left), and the ends of the two rows of control gates 22 on both sides in the column direction of the even-numbered row word line 11 are disconnected from each other on the first side (left) and connected to each other on the second side (right).
In the resistance test path of the control gate, the resistance between the head end metal layer 131 and the end metal layer 133 is measured as R, the total length of all the control gates is L, the width of the control gate is W, the square resistance of the control gate is Rs, rs=r×w/L. The test structure and the wafer acceptance calculation method are simple, less influenced by process and test fluctuation, and more stable test results.
In summary, the invention provides a resistance test structure of a flash memory and a forming method thereof, comprising the steps of providing a substrate, forming N rows of word lines which are distributed in parallel along a row direction on the substrate, wherein each row of word lines is distributed with one row of control gates along two sides of a column direction, ends of two control gates on one side of two rows of control gates on two sides of each row of word lines are connected with each other, ends of two control gates on the other side of the two control gates are disconnected with each other, forming a dielectric layer which covers the control gate layer, the word lines and the substrate, forming a contact hole in the dielectric layer, forming a contact hole on one side, far away from the word lines, of the two control gates on two sides of each row of word lines in the column direction, of each control gate is provided with a contact hole, forming a metal layer on the dielectric layer, wherein the metal layer comprises a first end metal layer, a middle metal layer and a tail end metal layer, the first row of control gates are electrically connected with the first end metal layer, the two rows of control gates between each two adjacent rows of word lines are electrically connected with the tail end metal layer through the middle metal layer, and the last row of control gates are electrically connected with the tail end metal layer.
According to the invention, the two rows of control gates on two sides of each row of word lines are connected with each other without an additional metal layer. The control gates on the two sides of each of the N rows of word lines are sequentially connected in series through the metal layer and the plugs in the contact holes to form a resistance test path of the control gates. The test structure is simple, the wafer is easy to accept and test, the influence of process and test fluctuation is smaller, and the test result is more stable.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
1. The method for forming the resistance test structure of the flash memory is characterized by comprising the following steps of:
step S1, providing a substrate, wherein N rows of word lines are formed on the substrate, and are distributed in parallel along the row direction, and one row of control gates are distributed on two sides of each row of word lines along the column direction;
S2, forming a dielectric layer, wherein the dielectric layer covers the control gate layer, the word lines and the substrate, forming contact holes in the dielectric layer, and arranging the contact holes on one side, away from the word lines, of each control gate on two sides of each row of word lines in the column direction;
And S3, forming a metal layer on the dielectric layer, wherein the metal layer comprises a head end metal layer, a middle metal layer and a tail end metal layer, the control gates in the first row are electrically connected with the head end metal layer, the control gates in the two rows between every two adjacent rows of word lines are electrically connected through the middle metal layer, the control gates in the last row are electrically connected with the tail end metal layer, and the control gates on two sides of each N rows of word lines are sequentially connected in series through plugs in the metal layer and the contact holes to form a resistance test path of the control gates.
2. The method for forming a resistance test structure of a flash memory according to claim 1, wherein the step S1 specifically comprises:
s11, forming a floating gate material layer and a control gate material layer on the substrate in sequence;
s12, patterning the control gate material layer and the floating gate material layer by using a floating gate correction mask plate, forming N rows of floating gate patterns distributed at intervals, wherein the control gate material layer and the floating gate material layer in the area where the floating gate patterns are located are reserved;
S13, etching and removing the control gate material layer and the floating gate material layer in the middle area of each row of floating gate patterns to form an opening, and forming a word line in the opening;
And S14, etching and removing one of two sides of each row of floating gate patterns along the row direction, so that the ends of the two control gates on one side are connected with each other, and the ends of the two control gates on the other side are disconnected with each other.
3. The method of forming a resistance test structure for a flash memory according to claim 2, wherein,
And in the floating gate correction mask, correction patterns are arranged at two corner positions, which correspond to the two rows of control gates on two sides of each row of word lines and are connected with each other, and the floating gate correction mask is obtained by combining the target patterns with the correction patterns by taking the floating gate patterns as target patterns.
4. The method for forming a resistance test structure of a flash memory according to claim 3, wherein,
The floating gate pattern is rectangular in top view, and the correction pattern is square or rectangular.
5. The method of forming a resistance test structure for a flash memory according to claim 2, wherein,
Two control gates on two sides of each row of word lines extend out of an extension block on one side, away from the word lines, of each control gate in the column direction, and the control gate material layer and the floating gate material layer in the area where the extension block is located are reserved;
The projection of the contact hole on the substrate falls into the projection of the extension block on the substrate, and the bottom of the plug in the contact hole is electrically connected with the extension block.
6. A resistance test structure of a flash memory, comprising:
The semiconductor device comprises a substrate, wherein N rows of word lines are formed on the substrate, the N rows of word lines are distributed in parallel along the row direction, and a row of control grids are distributed on two sides of each row of word lines along the column direction;
the control grid comprises a control grid, a word line, a substrate, a dielectric layer, contact holes, two control grids, a plurality of contact holes, a plurality of control gates and a plurality of control gates, wherein the control grid, the word line and the substrate are covered by the dielectric layer;
The metal layer comprises a head end metal layer, a middle metal layer and a tail end metal layer, wherein the first row of control gates are electrically connected with the head end metal layer, two rows of control gates between every two adjacent rows of word lines are electrically connected through the middle metal layer, the last row of control gates are electrically connected with the tail end metal layer, and the control gates on two sides of each N rows of word lines are sequentially connected in series through plugs in the metal layer and the contact holes to form a resistance test path of the control gates.
7. The resistance test structure of the flash memory according to claim 6, wherein,
Two sides of the control gate along the row direction are defined as a first side and a second side, respectively.
8. The resistance test structure of flash memory according to claim 7, wherein,
The ends of the control gates of two rows on both sides of the column direction of each row of word lines are connected with each other on the first side, and are disconnected with each other on the second side.
9. The resistance test structure of flash memory according to claim 7, wherein,
The ends of the control gates of the two rows on the two sides of the column direction of the word line of the odd rows are connected with each other on the first side, and are disconnected with each other on the second side;
The ends of the control gates of the two rows on the two sides of the word line in the column direction of the even-numbered rows are disconnected from each other on the first side, and are connected to each other on the second side.
10. The structure of claim 6, wherein in the resistance test path of the control gate, the resistance R between the head metal layer and the tail metal layer is measured, the total length of all the control gates is L, the width of the control gate is W, the square resistance of the control gate is Rs, rs=r×w/L.
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