CN119402068A - Satellite short message radio frequency circuit and frequency conversion method thereof - Google Patents
Satellite short message radio frequency circuit and frequency conversion method thereof Download PDFInfo
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Abstract
The application relates to a satellite short message radio frequency circuit and a frequency conversion method thereof, wherein the satellite short message radio frequency circuit comprises a single phase-locked loop circuit, the phase-locked loop circuit is coupled with an oscillator module, a local oscillator frequency division circuit is coupled with the phase-locked loop circuit, the local oscillator frequency division circuit divides a vco signal output by the oscillator module into a receiving local oscillator signal and sends the receiving local oscillator signal to a receiving down-conversion circuit, the local oscillator frequency division circuit divides the vco signal output by the oscillator module into a transmitting local oscillator signal and sends the transmitting local oscillator signal to a transmitting up-conversion circuit, the receiving down-conversion circuit mixes signals output by the receiving local oscillator signal and the receiving radio frequency circuit to generate a receiving radio frequency signal and sends the receiving radio frequency signal to a receiving base frequency circuit, and the transmitting up-conversion circuit mixes signals output by the transmitting local oscillator signal and the transmitting base frequency circuit to generate a transmitting radio frequency signal and sends the transmitting radio frequency signal to the transmitting radio frequency circuit. The application has the effect of reducing the phase-locked loop area and the power consumption in the radio frequency circuit.
Description
Technical Field
The application relates to the field of RDSS (radio frequency identification system) radio frequency technology, in particular to a satellite short message radio frequency circuit and a frequency conversion method thereof.
Background
For the increasing satellite short message demand, the most challenging difficulty to integrate the function in portable terminal devices, such as mobile phones, child watches, and geriatric monitoring devices, is that the area and power consumption of the existing satellite short message (RDSS) radio frequency chip are large. According to satellite communication frequency defined by a radio measurement satellite system RDSS, the satellite downlink and terminal receiving frequency ranges are 2483.5-2500 MHz, and the satellite uplink and terminal transmitting frequency ranges are 1610-1626.5 MHz, and the distance between the two ranges is larger. The service of RDSS satellite communication requires that the terminal receive uninterrupted, and for the terminal radio frequency chip to have the capability of simultaneous receiving and transmitting, i.e. full duplex operation capability. The receiving and transmitting respectively need to use local oscillation signals close to the frequency of the wireless signals to complete the frequency conversion operation of the radio frequency signals and the fundamental frequency signals, and the local oscillation signals need to be accurate and stable and are generally provided by an on-chip phase-locked loop.
Because the receiving and transmitting frequencies are relatively large in distance and have no simple integer multiple relation, independent phase-locked loops are usually needed to operate at the integer multiple frequency of the local oscillation frequency, then frequency division is used for providing at least four phases of receiving local oscillation signals for generating I and Q two paths of quadrature fundamental frequency signals, and the transmitting phase-locked loops also provide a plurality of phases of transmitting local oscillation signals for up-conversion through frequency division.
Conventional RDSS radio frequency chips therefore require a receive phase locked loop and a transmit phase locked loop that operate independently. If the working clock required by the baseband processing unit has special requirements and cannot have compatible integer multiple relation with the frequencies of the receiving local oscillator and the transmitting local oscillator signals, a third phase-locked loop is also required to be independently provided. The area consumption of the fully integrated phase-locked loop needs to be huge, and the circuit such as a resonant inductor, a loop filter resistor, a capacitor and the like generally occupies more than 1/3 of the area of the whole receiving or transmitting circuit, so that the area and the power consumption of a radio frequency chip are large, and improvement is needed.
Disclosure of Invention
In order to reduce the phase-locked loop area and power consumption in a radio frequency circuit and reduce the area and power consumption of the whole RDSS radio frequency chip, the application provides a satellite short message radio frequency circuit and a frequency conversion method thereof.
The first object of the present application is achieved by the following technical solutions:
a satellite short message radio frequency circuit comprises a single phase-locked loop circuit, a local oscillator frequency dividing circuit, a receiving down-conversion circuit, a transmitting up-conversion circuit, a receiving base frequency circuit, a receiving radio frequency circuit, a transmitting base frequency circuit and a transmitting radio frequency circuit;
The phase-locked loop circuit is coupled with an oscillator module;
The local oscillator frequency division circuit is coupled with the phase-locked loop circuit and is used for dividing the vco signal output by the oscillator module into a receiving local oscillator signal by two and transmitting the receiving local oscillator signal to the receiving down-conversion circuit;
The receiving down-conversion circuit is coupled with the receiving baseband circuit, mixes the receiving local oscillation signal with the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit;
The transmitting up-conversion circuit is coupled with the transmitting radio frequency circuit, mixes the transmitting local oscillation signal with the signal output by the transmitting fundamental frequency circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.
Further, the oscillator module presets a working frequency value interval according to the frequencies of the received radio frequency signal and the transmitted radio frequency signal, wherein the working frequency value interval is 1.8-2.2 times of the frequency of the received radio frequency signal and 2.8-3.2 times of the frequency of the transmitted radio frequency signal, or is equal to 3 times of the central frequency value of the transmitted radio frequency signal.
Further, the local oscillator frequency division circuit comprises a receiving local oscillator frequency division circuit;
the receiving local oscillator divide-by-two circuit is used for dividing the vco signal output by the oscillator module into a first receiving local oscillator signal and transmitting the first receiving local oscillator signal to the receiving down-conversion circuit;
The receiving down-conversion circuit comprises a first mixer, wherein the first mixer is coupled to the receiving radio frequency circuit, mixes the signal output by the receiving radio frequency circuit with the first receiving local oscillation signal to generate a first receiving radio frequency signal, and sends the first receiving radio frequency signal to the receiving baseband circuit.
Further, the receiving local oscillator frequency division circuit comprises a receiving local oscillator LO1 generating circuit, wherein the receiving local oscillator LO1 generating circuit comprises two latches, CK and CKB pins of a first latch and a second latch are both coupled to the phase-locked loop circuit to input vco signals, Y and Yb pins of the first latch are coupled to D and Db pins of the second latch, and Y and Yb pins of the second latch are coupled to Db and D pins of the first latch.
Further, the local oscillator frequency dividing circuit comprises a receiving local oscillator frequency dividing circuit and a receiving local oscillator N frequency dividing circuit, wherein N is a positive integer;
the receiving local oscillator divide-by-two circuit is used for dividing the vco signal output by the oscillator module into a first receiving local oscillator signal and transmitting the first receiving local oscillator signal to the receiving down-conversion circuit;
the input end of the receiving local oscillator N frequency dividing circuit is coupled with the phase-locked loop circuit, and the receiving local oscillator N frequency dividing circuit is used for dividing the vco signal N outputted by the oscillator module into a second receiving local oscillator signal and sending the second receiving local oscillator signal to the receiving down-conversion circuit;
the receiving down-conversion circuit comprises a first mixer and a second mixer;
the first mixer is coupled to the receiving radio frequency circuit, mixes the signal output by the receiving radio frequency circuit with the first receiving local oscillation signal to generate a first receiving radio frequency signal, and sends the first receiving radio frequency signal to the second mixer;
The second mixer is coupled to the first mixer, mixes the first received radio frequency signal output by the first mixer with the second received local oscillator signal to generate a second received radio frequency signal, and sends the second received radio frequency signal to the receiving baseband circuit.
Further, the receiving local oscillator divide-by-N circuit comprises a third latch, a fourth latch and a prepositioned div_by_n/2 circuit, wherein the div_by_n/2 circuit generates signals pre_p and pre_n subjected to divide-by-N/2 according to an input vco signal, CK and CKB pins of the third latch and the fourth latch are both coupled to the N/2 frequency divider, Y and Yb pins of the third latch are coupled to D and Db pins of the fourth latch, and Y and Yb pins of the fourth latch are coupled to Db and D pins of the third latch;
the value of N satisfies the following conditions:
;
Or:
;
wherein Fref represents a received radio frequency signal, fvco represents an oscillation frequency synthesized by a phase-locked loop circuit, fadc represents a working clock of an ADC module, and N is an even number when quadrature radio frequency signal output is required to be generated.
The transmitting local oscillator frequency division circuit is used for dividing vco signals output by the oscillator module into transmitting local oscillator signals;
The transmitting local oscillator three-frequency dividing circuit comprises a first half-phase inverter, a second half-phase inverter and a third half-phase inverter, clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to a phase-lock PLL, an out pin of the first half-phase inverter is coupled to an in pin of the second half-phase inverter, an out pin of the second half-phase inverter is coupled to an in pin of the third half-phase inverter, an out pin of the third half-phase inverter is coupled to an in pin of the first half-phase inverter, and an out pin of the third half-phase inverter outputs a three-frequency dividing local oscillator signal TxL0 of a vco signal.
Further, the first half-phase inverter comprises a first pmos tube, a second pmos tube, a first nmos tube and a second nmos tube, wherein the grid electrodes of the first pmos tube and the second nmos tube are coupled to the clk pin, the grid electrodes of the second pmos tube and the first nmos tube are coupled to the in pin, the drain electrode of the first pmos tube is coupled to the vdd pin, the drain electrode of the second pmos tube is coupled to the source electrode of the first pmos tube, the source electrode of the second pmos tube and the drain electrode of the first nmos tube are coupled to the out pin, the drain electrode of the second nmos tube is coupled to the source electrode of the first nmos tube, and the source electrode of the second nmos tube is coupled to the vss pin.
The phase-locked loop circuit further comprises a frequency division module, a frequency discrimination and phase discrimination module, a charge pump module, a loop filtering module and an oscillator module, wherein the frequency division module divides an output signal of the oscillator module to obtain an Fdiv signal, the frequency discrimination and phase discrimination module is connected with a reference clock signal Fref and the frequency division signal Fdiv, the output end of the frequency discrimination and phase discrimination module is coupled with the input end of the charge pump module, the output end of the charge pump module is coupled with the input end of the loop filtering module, the output end of the loop filtering module is coupled with the input end of the oscillator module, and the output end of the oscillator module is used as the output end of the phase-locked loop circuit to output the vco signal.
In addition, the application also provides a frequency conversion method based on the satellite short message radio frequency circuit, which comprises the following steps:
The local oscillator frequency dividing circuit divides vco signals output by the oscillator module into two parts to be received local oscillator signals and sends the received local oscillator signals to the receiving down-conversion circuit;
The local oscillator frequency dividing circuit divides vco signals output by the oscillator module into transmitting local oscillator signals by three frequencies and sends the transmitting local oscillator signals to the transmitting up-conversion circuit;
The receiving down-conversion circuit mixes the received local oscillation signal with the signal output by the receiving RF circuit to generate a receiving RF signal, and sends the receiving RF signal to the receiving baseband circuit, and
The transmitting up-conversion circuit mixes the transmitting local oscillation signal and the signal output by the transmitting base frequency circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.
In summary, the present application includes at least one of the following beneficial technical effects:
1. The method comprises the steps of using only one phase-locked loop circuit to perform special 3-removing circuit on a VCO signal to obtain a transmitting local oscillator with 50% duty ratio, completing transmitting up-conversion, performing first frequency conversion on an input radio frequency signal by performing 2-removing on the VCO signal to obtain a receiving local oscillator, generating a first receiving radio frequency signal, performing N-removing on the VCO signal to obtain a secondary local oscillator, and continuously performing second frequency mixing on the first receiving radio frequency signal to obtain a second receiving radio frequency signal. In addition, the signals with the working frequency required by the ADC can be obtained through frequency division, and the value of the signals is particularly expressed in the following aspects of overcoming the RDSS receiving and transmitting radio frequency with larger difference, providing complete up-and-down conversion functions, greatly reducing the area and the power consumption of a radio frequency chip by reducing the number of required phase-locked loop circuits, simultaneously meeting the receiving and transmitting work of a single phase-locked loop circuit, avoiding the adverse effect of mutual pumping of a plurality of phase-locked loop circuits in the same die and reducing interference factors.
2. The key points include special planning of frequency, proper frequency dividing method and reasonable frequency conversion scheme, so that a phase-locked loop circuit can provide all receiving and transmitting local oscillation signals, realize the frequency conversion function required by RDSS receiving and transmitting, and form the RDSS terminal radio frequency transceiver circuit.
3. The single phase-locked loop circuit obtains the receiving local oscillator signal and the transmitting local oscillator signal by frequency division of 2 and frequency division of 3 respectively, the obtained receiving local oscillator and transmitting local oscillator can not be ensured to have accuracy at the same time, only the accuracy of one of the receiving local oscillator and the transmitting local oscillator can be considered, the difference is eliminated by the scheme of second frequency conversion, and enough accuracy is still obtained. In particular, the RDSS radio frequency transceiver system preferably adopts a frequency planning scheme of transmitting one frequency conversion, namely transmitting local oscillation accuracy, so that the phase-locked loop circuit phase-locked frequency is aligned to the 3 frequency multiplication point of the transmitting radio frequency, and the receiving frequency is converted from the radio frequency to the required receiving radio frequency by means of two frequency conversion.
Drawings
FIG. 1 is a schematic diagram of the internal circuit structure of a conventional RDSS RF chip according to the background of the application;
FIG. 2 is a schematic circuit diagram of a satellite short message radio frequency circuit according to the present application;
FIG. 3 is a schematic diagram of a PLL circuit in an embodiment of a satellite short message RF circuit according to the present application;
FIG. 4 is a schematic diagram of a circuit configuration of a receiving local oscillator divide-by-two circuit in an embodiment of a satellite short message RF circuit according to the present application;
fig. 5 is a schematic circuit diagram of a receiving local oscillator divide-by-N circuit in an embodiment of a star burst radio frequency circuit according to the present application;
Fig. 6 is a schematic circuit diagram of a circuit structure of a transmit local oscillator divide-by-three circuit in an embodiment of a star burst radio frequency circuit according to the present application;
fig. 7 is a diagram of the internal circuit of a half-phase inverter in an embodiment of a star burst radio frequency circuit according to the present application.
Detailed Description
The present application is described in further detail below with reference to fig. 1-7.
According to the satellite communication frequency defined by the radio measurement satellite system, the receiving frequency range of the terminal is 2483.5-2500 MHz, and the (terminal transmitting) frequency range is 1610-1626.5 MHz, which are separated by 873.5M. The service of RDSS satellite communication requires that the terminal receives uninterruptedly, and the transmitting time can be selected independently, and the terminal radio frequency chip needs to have the capability of receiving and transmitting simultaneously, namely the full duplex operation capability. The receiving and transmitting respectively need to use local oscillation signals close to the frequency of the wireless signals to complete the frequency conversion operation of the radio frequency signals and the fundamental frequency signals, and the local oscillation signals need to be accurate and stable and are generally provided by an on-chip phase-locked loop. Because the receiving and transmitting frequencies are relatively large in distance and have no simple integer multiple relation, independent phase-locked loops are usually needed to operate at the integer multiple frequency of the local oscillation frequency, then frequency division is used for providing at least four phases of receiving local oscillation signals for generating I and Q two paths of quadrature fundamental frequency signals, and the transmitting phase-locked loops also provide a plurality of phases of transmitting local oscillation signals for up-conversion through frequency division.
Referring to fig. 1, a conventional RDSS radio frequency chip therefore requires a receive phase locked loop and a transmit phase locked loop that operate independently. If the working clock required by the baseband processing unit has special requirements and cannot have compatible integer multiple relation with the frequencies of the receiving local oscillator and the transmitting local oscillator signals, a third phase-locked loop is also required to be independently provided. The fully integrated phase-locked loop generally occupies a larger area, such as more than 1/3 of the total receiving or transmitting circuit, due to the need to include circuits with large area consumption, such as resonant inductance, loop filter resistance, and capacitance.
In some embodiments, as shown in fig. 2, the application discloses a satellite short message radio frequency circuit, which comprises a single phase-locked loop circuit, a local oscillator frequency division circuit, a receiving down-conversion circuit, a transmitting up-conversion circuit, a receiving base frequency circuit, a receiving radio frequency circuit, a transmitting base frequency circuit and a transmitting radio frequency circuit;
The phase-locked loop circuit is coupled with an oscillator module;
The local oscillator frequency division circuit is coupled with the phase-locked loop circuit and is used for dividing the vco signal output by the oscillator module into a receiving local oscillator signal by two and transmitting the receiving local oscillator signal to the receiving down-conversion circuit;
the receiving down-conversion circuit is coupled with the receiving baseband circuit, mixes the received local oscillation signal with the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit, wherein the receiving radio frequency signal is particularly the receiving radio frequency signal.
The transmitting up-conversion circuit is coupled with the transmitting radio frequency circuit, mixes the transmitting local oscillation signal with the signal output by the transmitting fundamental frequency circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.
Further, the oscillator module presets a working frequency value interval according to the frequencies of the received radio frequency signal and the transmitted radio frequency signal, wherein the working frequency value interval is 1.8-2.2 times of the frequency of the received radio frequency signal and 2.8-3.2 times of the frequency of the transmitted radio frequency signal, or is equal to 3 times of the central frequency value of the transmitted radio frequency signal.
In some embodiments, the local oscillator frequency division circuit includes a receive local oscillator frequency division circuit;
the receiving local oscillator divide-by-two circuit is used for dividing the vco signal output by the oscillator module into a first receiving local oscillator signal and transmitting the first receiving local oscillator signal to the receiving down-conversion circuit;
The receiving down-conversion circuit comprises a first mixer, wherein the first mixer is coupled to the receiving radio frequency circuit, mixes the signal output by the receiving radio frequency circuit with the first receiving local oscillation signal to generate a first receiving radio frequency signal, and sends the first receiving radio frequency signal to the receiving baseband circuit.
In some embodiments, the receiving local oscillator frequency division circuit comprises a receiving local oscillator LO1 generating circuit, wherein the receiving local oscillator LO1 generating circuit comprises two latches, CK and CKB pins of a first latch and a second latch are coupled to the phase-locked loop circuit to input vco signals, Y and Yb pins of the first latch are coupled to D and Db pins of the second latch, and Y and Yb pins of the second latch are coupled to Db and D pins of the first latch.
In some embodiments, the local oscillator frequency division circuit comprises a receiving local oscillator frequency division circuit and a receiving local oscillator frequency division circuit, wherein N is a positive integer;
the receiving local oscillator divide-by-two circuit is used for dividing the vco signal output by the oscillator module into a first receiving local oscillator signal and transmitting the first receiving local oscillator signal to the receiving down-conversion circuit;
the input end of the receiving local oscillator N frequency dividing circuit is coupled with the phase-locked loop circuit, and the receiving local oscillator N frequency dividing circuit is used for dividing the vco signal N outputted by the oscillator module into a second receiving local oscillator signal and sending the second receiving local oscillator signal to the receiving down-conversion circuit;
the receiving down-conversion circuit comprises a first mixer and a second mixer;
the first mixer is coupled to the receiving radio frequency circuit, mixes the signal output by the receiving radio frequency circuit with the first receiving local oscillation signal to generate a first receiving radio frequency signal, and sends the first receiving radio frequency signal to the second mixer;
The second mixer is coupled to the first mixer, mixes the first received radio frequency signal output by the first mixer with the second received local oscillator signal to generate a second received radio frequency signal, and sends the second received radio frequency signal to the receiving baseband circuit.
In some embodiments, the receiving local oscillator divide-by-N circuit includes third and fourth latches and a leading div_by_n/2 circuit, the div_by_n/2 circuit generating N/2 divided signals pre_p and pre_n according to an input vco signal, CK and CKb pins of the third and fourth latches are coupled to the N/2 divider, Y and Yb pins of the third latch are coupled to D and Db pins of the fourth latch, and Y and Yb pins of the fourth latch are coupled to Db and D pins of the third latch;
the value of N satisfies the following conditions:
;
Or:
;
wherein Fref represents a received radio frequency signal, fvco represents an oscillation frequency synthesized by a phase-locked loop circuit, fadc represents a working clock of an ADC module, and N is an even number when quadrature radio frequency signal output is required to be generated.
In some embodiments, the local oscillator frequency dividing circuit further comprises a transmitting local oscillator frequency dividing circuit, wherein the transmitting local oscillator frequency dividing circuit is used for dividing vco signals output by the oscillator module into transmitting local oscillator signals;
The transmitting local oscillator three-frequency dividing circuit comprises a first half-phase inverter, a second half-phase inverter and a third half-phase inverter, clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to a phase-lock PLL, an out pin of the first half-phase inverter is coupled to an in pin of the second half-phase inverter, an out pin of the second half-phase inverter is coupled to an in pin of the third half-phase inverter, an out pin of the third half-phase inverter is coupled to an in pin of the first half-phase inverter, and an out pin of the third half-phase inverter outputs a three-frequency dividing local oscillator signal TxL0 of a vco signal.
In some embodiments, the first half-phase inverter comprises a first pmos transistor, a second pmos transistor, a first nmos transistor and a second nmos transistor, wherein the gates of the first pmos transistor and the second nmos transistor are coupled to the clk pin, the gates of the second pmos transistor and the first nmos transistor are coupled to the in pin, the drain of the first pmos transistor is coupled to the vdd pin, the drain of the second pmos transistor is coupled to the source of the first pmos transistor, the source of the second pmos transistor and the drain of the first nmos transistor are coupled to the out pin, the drain of the second nmos transistor is coupled to the source of the first nmos transistor, and the source of the second nmos transistor is coupled to the vss pin.
In some embodiments, the phase-locked loop circuit comprises a frequency division module, a frequency discrimination and phase discrimination module, a charge pump module, a loop filter module and an oscillator module, wherein the frequency division module divides an output signal of the oscillator module to obtain an Fdiv signal, the frequency discrimination and phase discrimination module is connected with a reference clock signal Fref and a frequency division signal Fdiv, an output end of the frequency discrimination and phase discrimination module is coupled with an input end of the charge pump module, an output end of the charge pump module is coupled with an input end of the loop filter module, an output end of the loop filter module is coupled with an input end of the oscillator module, and an output end of the oscillator module is used as an output end of the phase-locked loop circuit to output the vco signal.
Specifically, as shown in fig. 2, the receiving radio frequency (RxRF) circuit 11 of the present application, i.e., a low noise amplifier, amplifies the input radio frequency signal RxANT while ensuring a sufficient signal-to-noise ratio.
The pll circuit 12 includes a frequency and phase discrimination module, and a loop filter module, where the frequency and phase discrimination module is connected to the reference clock signal Fref13, an output end of the frequency and phase discrimination module is coupled to an input end of the loop filter module, an output end of the loop filter module is coupled to an input end of the pll circuit, an output end of the pll circuit outputs a vco signal with frequency Fvco, and a local oscillator frequency division circuit is coupled to the frequency and phase discrimination circuit, as shown in fig. 3.
The local oscillator frequency dividing circuit 14 includes a receiving local oscillator frequency dividing circuit and a receiving local oscillator frequency dividing circuit, the receiving local oscillator frequency dividing circuit includes a two-frequency divider div and a mixer MIX1, an input end of the two-frequency divider div is coupled to the phase-locked loop circuit to receive vco signals and output two-frequency division frequencies from Flo 1to the mixer MIX1, the mixer MIX1 carries out a first frequency conversion to output a first radio frequency Fif 1to a filtering and amplifying (RxIF 1) processing circuit 15 of the first radio frequency signals so as to filter high-frequency mixing components generated by the first frequency mixing and also to inhibit out-of-band interference to a certain extent; the receiving local oscillator divide-by-N circuit includes a divide-by-N divN mixer MIX2, an input terminal of a divide-by-N divN is coupled to the pll circuit to receive the vco signal, and outputs the divided-by-N vco signal divided by a predetermined division ratio to a mixer MIX2, the frequency is Flo2, an input terminal of the mixer MIX2 is coupled to a filtering and amplifying (RxIF 1) processing circuit of the first rf signal to MIX Fif1 and Flo2, an output terminal of the mixer MIX2 is connected in series with a receiving rf (RxIF 2) circuit 16, and then outputs the vco signal to the receiving baseband circuit (RxBB) 17, and analog-to-digital conversion is performed on the rf, that is, the ADC and the digital rf processing are performed on the final rf signal obtained by the frequency conversion by the receiving rf (RxIF 2) circuit 16, so as to provide a signal with a proper amplitude for the subsequent ADC, filter to generate an additional mixing component, and also filter an unwanted out-of-band signal, and reduce interference.
The local oscillator frequency dividing circuit further comprises a transmitting local oscillator frequency dividing circuit, the transmitting local oscillator frequency dividing circuit is used for generating three frequency divisions of a VCO signal, the transmitting local oscillator (TxLO) is generated from the three frequency divisions of the VCO signal, namely, three times of the transmitting carrier frequencies 1614.26MHz and 1618.34MHz of the RDSS system are selected, 4842.78MHz and 4,855.02MHz are selected respectively as an implementation example of the embodiment, the local oscillator frequency dividing circuit comprises a three frequency divider div and a mixer MIX3, the three frequency divider div is coupled to the phase-locked loop circuit to receive the VCO signal of the Fvco frequency, and the output end of the three frequency divider div is coupled to the mixer MIX3.
The output end of the mixer MIX3 is coupled to a transmitting radio frequency (TxRF) circuit 18, the input end of the mixer MIX3 is coupled to a transmitting radio frequency (TxIF) circuit 19, the analog radio frequency is subjected to appropriate filtering and amplitude amplification preparation and is sent to transmitting up-conversion processing, the output end of the mixer MIX3 is coupled to the transmitting radio frequency (TxRF) circuit 18 and is subjected to appropriate differential signal and single-ended signal processing to meet the requirement of an off-chip Power Amplifier (PA), the input end of the transmitting radio frequency (TxIF) circuit 19 is coupled to a transmitting base frequency circuit (TxBB) 20, RDSS uplink information to be transmitted is subjected to digital processing, BPSK can be generated and submitted to the transmitting radio frequency (TxIF) circuit 19 for processing, and the RDSS uplink information can be subjected to digital-analog conversion and then submitted to the transmitting radio frequency (TxIF) circuit 19 for processing.
As shown in fig. 4, the divider div of the receiving local oscillator divide-by-two circuit includes a receiving local oscillator lo1 generating circuit with a frequency of Flo1, two latches latch of the receiving local oscillator lo1 generating circuit, CK pins of the first latch and the second latch are coupled to the pll circuit to receive vco signals, D pin of the first latch is coupled to Qb pin of the second latch, Q pin of the first latch is coupled to D pin of the second latch, and Q pin of the second latch outputs receiving local oscillator lo1.
As shown in fig. 5, the receiving local oscillator divide-by-N circuit includes a third latch and a fourth latch, wherein CK pins of the third latch and the fourth latch are coupled to the divide-by-N circuit divN to receive the divide-by-N vco signal, D pin of the third latch is coupled to Qb pin of the fourth latch, Q pin of the third latch is coupled to D pin of the fourth latch, Q pin output of the fourth latch receives local oscillator lo2, and the value of N satisfies the following equation:
Wherein Fref represents the received rf input signal, the RDSS center frequency is 2491.75MHz, fvco represents the oscillation frequency of the PLL synthesis, 4855.02MHz is taken as an example of the present embodiment, fadc represents the operating clock of the ADC module, 76MHz is taken as an example of the present embodiment, and n=96 may be taken as an example of the present embodiment.
As shown in fig. 6, the transmitting local oscillator three-frequency dividing circuit includes three half-phase inverters, the clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to the PLL, the in pin of the first half-phase inverter is coupled to the out pin of the third half-phase inverter, the out pin of the first half-phase inverter is coupled to the in pin of the second half-phase inverter, the in pin of the second half-phase inverter is coupled to the out pin of the third half-phase inverter, and the out pin of the third half-phase inverter outputs the three-frequency division TxL0 of the vco signal, and the TxLO signal has a duty ratio of 50% by using the three half-phase inverters.
As shown in fig. 7, the half-phase inverter includes a first pmos transistor, a second pmos transistor, a first nmos transistor, and a second nmos transistor, where gates of the first pmos transistor and the second nmos transistor are coupled to the clk pin, gates of the second pmos transistor and the first nmos transistor are coupled to the in pin, a drain of the first pmos transistor is coupled to the vdd pin, a drain of the second pmos transistor is coupled to a source of the first pmos transistor, a source of the second pmos transistor and a drain of the first nmos transistor are coupled to the out pin, a drain of the second nmos transistor is coupled to a source of the first nmos transistor, and a source of the second nmos transistor is coupled to the vss pin.
In some embodiments, the present application further provides a frequency conversion method based on the satellite short message radio frequency circuit, including:
The local oscillator frequency dividing circuit divides vco signals output by the oscillator module into two parts to be received local oscillator signals and sends the received local oscillator signals to the receiving down-conversion circuit;
The local oscillator frequency dividing circuit divides vco signals output by the oscillator module into transmitting local oscillator signals by three frequencies and sends the transmitting local oscillator signals to the transmitting up-conversion circuit;
The receiving down-conversion circuit mixes the received local oscillation signal with the signal output by the receiving RF circuit to generate a receiving RF signal, and sends the receiving RF signal to the receiving baseband circuit, and
The transmitting up-conversion circuit mixes the transmitting local oscillation signal and the signal output by the transmitting base frequency circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.
The following is an explanation of some of the circuits to which the present application relates:
1) The phase-locked loop circuit comprises a circuit such as an input reference clock signal, a main frequency divider, a phase frequency detector, a charge pump, loop filtering and the like besides the oscillator module, and realizes a frequency synthesizer taking the input reference clock as a reference to provide a stable high-frequency clock signal with a required target frequency. Other implementations can also be digital phase-locked loops, wherein the circuits of a phase frequency detector, a charge pump, loop filter and the like are changed into a time-to-digital converter, a digital filter and a digital frequency control oscillator module to realize the same frequency synthesizer and provide the required stable high-frequency clock signal;
2) A receiving radio frequency (RxRF) circuit, i.e. a low noise amplifier is used to amplify the input radio frequency signal while ensuring a sufficient signal-to-noise ratio;
3) A filtering and amplifying processing circuit (RxIF 1) for filtering the first radio frequency signal between two frequency conversion, which mainly aims to filter out the high frequency mixing component generated by the first mixing and to inhibit the out-of-band interference to a certain extent;
4) The receiving radio frequency (RxIF 2) circuit amplifies, filters and controls the gain of the final radio frequency signal obtained by frequency conversion so as to provide signals with proper amplitude for the subsequent ADC, filters and filters to generate additional mixing components, and simultaneously filters out unnecessary out-of-band signals to reduce interference;
5) A receiving baseband circuit (RxBB) for performing analog-to-digital conversion (ADC) and digital radio frequency processing on the radio frequency;
6) The base frequency transmitting circuit (TxBB) carries out digital processing on RDSS uplink information to be transmitted, and can generate BPSK to be sent to TxIF for processing, or can be sent to TxIF for processing after digital-to-analog conversion (DAC);
7) A transmitting radio frequency circuit (TxIF) for performing appropriate filtering and amplitude amplification preparation on the analog radio frequency and transmitting the analog radio frequency to a transmitting up-conversion process;
8) The radio frequency signal after up-conversion is transmitted needs to pass through a transmitting radio frequency (TxRF) circuit and is subjected to proper differential signal and single-ended signal processing, so that the requirement of an off-chip Power Amplifier (PA) is met.
The main functions and the inventive concept of the application are as follows:
1. Oscillator module oscillating around a particular frequency
The working frequency of the oscillator module needs to be compatible with the frequency of the received radio frequency signal and the frequency of the transmitted radio frequency signal, and is locked by the phase-locked loop to be accurate and stable in phase. For the characteristic that the receiving frequency of the RDSS radio frequency signal is about 2491MHz and 1614MHz, frequencies near 2 times the receiving frequency and 3 times the receiving frequency are selected, such as Fvco=4842 MHz.
2. Proper frequency division method
Fvco is divided by a simple frequency of 2 to receive local oscillator frequency Frxlo =2421 MHz and transmit local oscillator frequency is divided by 3 to yield Ftxlo =1614. The divide by three is not a conventional method of dividing frequency, and requires special design if it is desired to achieve a divide by 3 signal that bisects the phase.
3. The single phase-locked loop obtains the receiving local oscillator and the transmitting local oscillator signals by frequency division of 2 and frequency division of 3 respectively, and cannot ensure that the obtained receiving local oscillator and the obtained transmitting local oscillator are accurate at the same time, only one of the receiving local oscillator and the transmitting local oscillator is accurate, and the difference is eliminated by the scheme of second frequency conversion. The cost of two frequency conversions is comprehensively considered for receiving and transmitting, a frequency planning scheme of transmitting one frequency conversion, namely local oscillation accuracy is optimized, the phase locking frequency of the phase-locked loop is aligned to the 3 frequency multiplication point of the transmitting radio frequency, and the receiving finishes the frequency conversion from the radio frequency to the required receiving radio frequency by means of the two frequency conversions.
4. Receiving a secondary frequency conversion scheme
The first radio frequency is obtained after the first frequency conversion and is fif1=2491-2421=70 MHz. And obtaining a second local oscillator by Fvco/96 (about 50M), mixing with the Fif1 to obtain a second radio frequency Fif2 of Fif1-Fvco/96 (about 20 MHz) which can be submitted to digital baseband processing. Other division ratios than 96 are contemplated herein, provided that Fif2 is suitable for baseband processing.
5. Other circuit modules
The RDSS receiving and transmitting requirements are met according to the conventional circuit implementation.
The foregoing embodiments are merely illustrative of the technical solutions of the present application, and not restrictive, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. The satellite short message radio frequency circuit is characterized by comprising a single phase-locked loop circuit, a local oscillator frequency division circuit, a receiving down-conversion circuit, a transmitting up-conversion circuit, a receiving base frequency circuit, a receiving radio frequency circuit, a transmitting base frequency circuit and a transmitting radio frequency circuit;
The phase-locked loop circuit is coupled with an oscillator module;
The local oscillator frequency division circuit is coupled with the phase-locked loop circuit and is used for dividing the vco signal output by the oscillator module into a receiving local oscillator signal by two and transmitting the receiving local oscillator signal to the receiving down-conversion circuit;
The receiving down-conversion circuit is coupled with the receiving baseband circuit, mixes the receiving local oscillation signal with the signal output by the receiving radio frequency circuit to generate a receiving radio frequency signal, and sends the receiving radio frequency signal to the receiving baseband circuit;
The transmitting up-conversion circuit is coupled with the transmitting radio frequency circuit, mixes the transmitting local oscillation signal with the signal output by the transmitting fundamental frequency circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.
2. The short message radio frequency circuit for satellites according to claim 1, wherein the oscillator module presets a working frequency value interval according to frequencies of the received radio frequency signal and the transmitted radio frequency signal, and the working frequency value interval is 1.8-2.2 times of the frequency of the received radio frequency signal and 2.8-3.2 times of the frequency of the transmitted radio frequency signal, or is equal to 3 times of a central frequency value of the transmitted radio frequency signal.
3. The satellite short message radio frequency circuit according to claim 1, wherein the local oscillator frequency dividing circuit comprises a receiving local oscillator frequency dividing circuit;
the receiving local oscillator divide-by-two circuit is used for dividing the vco signal output by the oscillator module into a first receiving local oscillator signal and transmitting the first receiving local oscillator signal to the receiving down-conversion circuit;
The receiving down-conversion circuit comprises a first mixer, wherein the first mixer is coupled to the receiving radio frequency circuit, mixes the signal output by the receiving radio frequency circuit with the first receiving local oscillation signal to generate a first receiving radio frequency signal, and sends the first receiving radio frequency signal to the receiving baseband circuit.
4. The satellite short message radio frequency circuit of claim 3, wherein the receive local oscillator divide-by-two circuit comprises a receive local oscillator LO1 generation circuit, the receive local oscillator LO1 generation circuit comprises two latches, the CK and CKB pins of the first latch and the second latch are coupled to the phase-locked loop circuit for inputting vco signals, the Y and Yb pins of the first latch are coupled to the D and Db pins of the second latch, and the Y and Yb pins of the second latch are coupled to the Db and D pins of the first latch.
5. The satellite short message radio frequency circuit of claim 1, wherein the local oscillator frequency dividing circuit comprises a receiving local oscillator frequency dividing circuit and a receiving local oscillator frequency dividing circuit, wherein N is a positive integer;
the receiving local oscillator divide-by-two circuit is used for dividing the vco signal output by the oscillator module into a first receiving local oscillator signal and transmitting the first receiving local oscillator signal to the receiving down-conversion circuit;
the input end of the receiving local oscillator N frequency dividing circuit is coupled with the phase-locked loop circuit, and the receiving local oscillator N frequency dividing circuit is used for dividing the vco signal N outputted by the oscillator module into a second receiving local oscillator signal and sending the second receiving local oscillator signal to the receiving down-conversion circuit;
the receiving down-conversion circuit comprises a first mixer and a second mixer;
the first mixer is coupled to the receiving radio frequency circuit, mixes the signal output by the receiving radio frequency circuit with the first receiving local oscillation signal to generate a first receiving radio frequency signal, and sends the first receiving radio frequency signal to the second mixer;
the second mixer is coupled to the first mixer, and mixes the first received radio frequency signal output by the first mixer with the second received local oscillator signal to generate a second received radio frequency signal, and sends the second received radio frequency signal to the receiving baseband circuit.
6. The satellite short message radio frequency circuit of claim 5, wherein the receiving local oscillator N frequency dividing circuit comprises a third latch, a fourth latch and a prepositioned div_by_N/2 circuit, the div_by_N/2 circuit generates signals pre_p and pre_n subjected to N/2 frequency division according to an input vco signal, CK and CKB pins of the third latch and the fourth latch are coupled to the N/2 frequency divider, Y and Yb pins of the third latch are coupled to D and Db pins of the fourth latch, and Y and Yb pins of the fourth latch are coupled to Db and D pins of the third latch;
the value of N satisfies the following conditions:
;
Or:
;
wherein Fref represents a received radio frequency signal, fvco represents an oscillation frequency synthesized by a phase-locked loop circuit, fadc represents a working clock of an ADC module, and N is an even number when quadrature radio frequency signal output is required to be generated.
7. The satellite short message radio frequency circuit of claim 1, wherein the local oscillator frequency dividing circuit further comprises a transmitting local oscillator frequency dividing circuit, wherein the transmitting local oscillator frequency dividing circuit is used for dividing vco signals output by the oscillator module into transmitting local oscillator signals;
The transmitting local oscillator three-frequency dividing circuit comprises a first half-phase inverter, a second half-phase inverter and a third half-phase inverter, clk pins of the first half-phase inverter, the second half-phase inverter and the third half-phase inverter are all coupled to a phase-lock PLL, an out pin of the first half-phase inverter is coupled to an in pin of the second half-phase inverter, an out pin of the second half-phase inverter is coupled to an in pin of the third half-phase inverter, an out pin of the third half-phase inverter is coupled to an in pin of the first half-phase inverter, and an out pin of the third half-phase inverter outputs a three-frequency dividing local oscillator signal TxL0 of a vco signal.
8. The satellite short message radio frequency circuit of claim 7, wherein the first half-phase inverter comprises a first pmos transistor, a second pmos transistor, a first nmos transistor and a second nmos transistor, wherein the gates of the first pmos transistor and the second nmos transistor are coupled to the clk pin, the gates of the second pmos transistor and the first nmos transistor are coupled to the in pin, the drain of the first pmos transistor is coupled to the vdd pin, the drain of the second pmos transistor is coupled to the source of the first pmos transistor, the source of the second pmos transistor and the drain of the first nmos transistor are coupled to the out pin, the drain of the second nmos transistor is coupled to the source of the first nmos transistor, and the source of the second nmos transistor is coupled to the vss pin.
9. The satellite short message radio frequency circuit according to claim 1, wherein the phase-locked loop circuit comprises a frequency division module, a frequency discrimination and phase discrimination module, a charge pump module, a loop filter module and an oscillator module, wherein the frequency division module divides an output signal of the oscillator module to obtain an Fdiv signal, the frequency discrimination and phase discrimination module is connected with a reference clock signal Fref and a frequency division signal Fdiv, an output end of the frequency discrimination and phase discrimination module is coupled with an input end of the charge pump module, an output end of the charge pump module is coupled with an input end of the loop filter module, an output end of the loop filter module is coupled with an input end of the oscillator module, and an output end of the oscillator module is used as an output end of the phase-locked loop circuit to output the vco signal.
10. A method of frequency conversion based on the satellite short message radio frequency circuit of any one of claims 1-9, comprising:
The local oscillator frequency dividing circuit divides vco signals output by the oscillator module into two parts to be received local oscillator signals and sends the received local oscillator signals to the receiving down-conversion circuit;
The local oscillator frequency dividing circuit divides vco signals output by the oscillator module into transmitting local oscillator signals by three frequencies and sends the transmitting local oscillator signals to the transmitting up-conversion circuit;
The receiving down-conversion circuit mixes the received local oscillation signal with the signal output by the receiving RF circuit to generate a receiving RF signal, and sends the receiving RF signal to the receiving baseband circuit, and
The transmitting up-conversion circuit mixes the transmitting local oscillation signal and the signal output by the transmitting base frequency circuit to generate a transmitting radio frequency signal, and sends the transmitting radio frequency signal to the transmitting radio frequency circuit.
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