CN119400713B - Bonding method and bonding structure - Google Patents

Abstract

The embodiment of the disclosure relates to the field of semiconductors and provides a bonding method, which comprises the steps of providing a wafer, forming a plurality of contact plugs on the wafer, forming a pseudo passivation layer on the first chip of the wafer, forming a passivation layer in a region except the first chip, jointly covering the plurality of contact plugs, patterning the passivation layer to expose the surface of part of the contact plugs, forming bonding pads in the patterned passivation layer, covering the surface of part of the contact plugs, and electrically connecting the bonding pads with the second chip through the contact plugs, and performing hybrid bonding on at least two wafers to form a bonding structure.

Description

Bonding method and bonding structure

Technical Field

The embodiment of the disclosure relates to the field of semiconductors, in particular to a bonding method and a bonding structure.

Background

With the development of general semiconductor technology and market driving of consumer electronics, the chip is manufactured and packaged in smaller and smaller sizes. In the case where the rate of development of "moore's law gradually approaches a limit, the importance of" supermoore's law in the field of general semiconductors is increasing. The implementation of "heterogeneous mixing" by bonding is one of the important technologies of "supermole law", and the bonding process can perform high-density interconnection on chips manufactured by different process nodes, so as to realize system-level integration with smaller size, higher performance and lower power consumption.

As one type of Wafer-level package (Wafer-LEVEL PACKAGING, WLP), wafer-to-Wafer bonding (WoW) can achieve interconnection between chips by directly bonding two wafers, so that packaging density and performance can be improved, however, the yield of WoW in an actual process is low due to the influence of bad chips in the wafers, and bad chips in one Wafer may be bonded with qualified chips of the other Wafer due to the fact that the bad chips cannot be removed, so that the yield of the finally bonded chips is greatly reduced.

Disclosure of Invention

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a bonding method, including:

providing a wafer, wherein the wafer comprises a plurality of first chips and a plurality of second chips;

forming a plurality of contact plugs on the wafer, wherein the contact plugs are electrically connected with the first chip and the second chip of the wafer;

Forming a pseudo passivation layer on the first chip of the wafer, and forming a passivation layer in a region except the first chip, wherein the pseudo passivation layer and the passivation layer jointly cover a plurality of contact plugs;

Patterning the passivation layer to expose a portion of the surface of the contact plug and forming a bonding pad within the patterned passivation layer, the bonding pad covering a portion of the surface of the contact plug and being electrically connected to the second chip through the contact plug;

and performing hybrid bonding on at least two wafers to form a bonding structure.

In some embodiments, the wafer is tested, and the chips in the wafer are divided into a plurality of first chips and a plurality of second chips according to the test result.

In some embodiments, forming a plurality of contact plugs on the wafer includes depositing an insulating layer on the wafer and planarizing a surface of the insulating layer, the insulating layer covering the first and second chips, patterning the insulating layer to form first trenches exposing portions of surfaces of the first and second chips, depositing a conductive material within the trenches to form the contact plugs, removing the conductive material deposited on the wafer surface, and planarizing the wafer surface.

In some embodiments, forming a dummy passivation layer on the first chip of the wafer, forming a passivation layer on a region other than the first chip, the dummy passivation layer and the passivation layer together covering the plurality of contact plugs, includes forming a dummy passivation layer on the first chip of the wafer, forming a passivation layer on a region other than the first chip, a portion of the passivation layer covering the second chip and the dummy passivation layer, and planarizing the passivation layer and the dummy passivation layer.

In some embodiments, the material of the dummy passivation layer comprises polyimide and the material of the passivation layer comprises silicon carbide nitride.

In some embodiments, the pseudo passivation layer has a thickness in the range of 1-10 μm.

In some embodiments, the temperature of the hybrid bonding is 250-350 ℃.

In some embodiments, after performing the hybrid bonding, cutting the bonding structure is further included to obtain a chip stack structure.

In some embodiments, when the chip stack structure includes the pseudo passivation layer, the chip stack structure is separated to obtain at least one of the first chips.

In some embodiments, the method of separating the chip stack structure includes laser or low temperature lift-off.

According to some embodiments of the present disclosure, there is also provided, in another aspect, a bonding structure including:

The wafer comprises a plurality of first chips, a plurality of second chips, a pseudo passivation layer, a passivation layer and a bonding pad, wherein the plurality of first chips, the plurality of second chips and the plurality of contact plugs are electrically connected with the first chips and the second chips, the pseudo passivation layer and the passivation layer are arranged on the first chips, the passivation layer is arranged in an area outside the first chips, the pseudo passivation layer and the passivation layer jointly cover the plurality of contact plugs, and the bonding pad is arranged on the surface of part of the contact plugs and is electrically connected with the second chips through the contact plugs.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

The method comprises the steps of forming a pseudo passivation layer on a first chip of a wafer, forming a passivation layer in a region except the first chip, wherein the pseudo passivation layer and the passivation layer jointly cover a plurality of contact plugs, patterning the passivation layer to expose part of the surfaces of the contact plugs, forming bonding pads in the patterned passivation layer, wherein the bonding pads cover part of the surfaces of the contact plugs and are electrically connected with a second chip through the contact plugs, and performing hybrid bonding on at least two wafers to form a bonding structure. By forming the pseudo passivation layer on the first chip, the first chip can be separated from other chips after the wafer forms the bonding structure, so that the wafer bonding yield is improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically claimed, and in order to more clearly illustrate the embodiments of the present disclosure or the concepts of the conventional art, the drawings that are required to be utilized in the embodiments will be briefly described below, it will be apparent that the drawings in the following description are merely some embodiments of the present disclosure and that other drawings may be derived from these drawings by one of ordinary skill in the art without undue effort.

Fig. 1 is a flowchart illustrating a bonding method according to an embodiment of the present disclosure.

Fig. 2 is a top view of a wafer according to an embodiment of the present disclosure.

Fig. 3 to 13 are cross-sectional views of a portion of a wafer along the AA' direction corresponding to each step of a bonding method according to an embodiment of the present disclosure.

Fig. 14 is a schematic diagram of a bonding process according to an embodiment of the disclosure.

Fig. 15 is a cross-sectional view of a partially bonded wafer along the AA' direction in accordance with one embodiment of the present disclosure.

Fig. 16 is a schematic diagram of a chip stacking structure along the AA' direction according to an embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Wafer-level packaging (WLP) is an advanced semiconductor packaging technology that packages and tests on wafers before the chips have been cut from the Wafer. The packaging technology can obviously reduce the packaging volume, improve the packaging density, reduce the packaging cost and the signal transmission delay and enhance the packaging performance. As one type of Wafer-level package (Wafer-LEVEL PACKAGING, WLP), wafer-to-Wafer bonding (WoW) can achieve interconnection between chips by directly bonding two wafers, so that packaging density and performance can be improved, however, the yield of WoW in an actual process is low due to the influence of bad chips in the wafers, and bad chips in one Wafer may be bonded with qualified chips of the other Wafer due to the fact that the bad chips cannot be removed, so that the yield of the finally bonded chips is greatly reduced.

To solve the above technical problems, embodiments of the present disclosure provide a bonding method, and a semiconductor structure provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

Fig. 1 is a flow chart of steps of a bonding method according to an embodiment of the present disclosure, fig. 2 is a top view of a wafer according to an embodiment of the present disclosure, fig. 3 to fig. 13 are cross-sectional views of a portion of the wafer along an AA' direction corresponding to each step of the bonding method according to an embodiment of the present disclosure, and fig. 14 is a schematic diagram of a bonding process according to an embodiment of the present disclosure, and the bonding method according to the embodiment will be described in detail with reference to the accompanying drawings.

Fig. 1 is a flowchart of a bonding method according to an embodiment of the present disclosure, which specifically includes:

step S100 provides a wafer, wherein the wafer 100 includes a plurality of first chips C1 and a plurality of second chips C2.

In some embodiments, referring to fig. 2, a wafer 100 includes a plurality of chips arranged in an array, before bonding, the wafer 100 needs to be tested, that is, yield detection, and the chips in the wafer 100 are divided into a plurality of first chips C1 and a plurality of second chips C2 according to a test result, and dicing lanes SL are provided between the first chips C1 and the second chips C2 and between the first chips C1 and the second chips C2 or between the second chips C2 and the second chips C2, where positioning marks and test structures may be formed in the dicing lanes SL, so that alignment and testing of the wafer before dicing are facilitated, and accuracy of dicing and functionality of the chips are ensured. Testing of the wafer 100 involves inspecting the yield of the wafer 100 to evaluate the quality of the chips thereon. Through yield inspection, the percentage of the total number of die that are acceptable per wafer 100, i.e., yield, can be determined. Meanwhile, more detailed information such as the number of pass chips and fail chips, which are defined as the first chip C1, and their specific position distribution on the wafer, can also be acquired through inspection, which is defined as the second chip C2.

In some embodiments, the methods employed for wafer inspection may include electrical performance testing, optical inspection, probe testing, automated optical inspection, and the like, on the wafer. The electrical performance test is to apply an electrical signal to the chip to determine whether the function of the chip meets the design specification, including a direct current test (DC TESTING), an alternating current test (AC TESTING), a functional test (Functional Testing), etc. to check the static and dynamic performances of the chip, the optical test (Optical Inspection) is to check the physical defects of the chip surface, such as scratches, cracks, contaminations, etc., by using a high-resolution optical microscope or a Scanning Electron Microscope (SEM), and the method can detect very tiny defects, and the Probe test (Probe test) is to perform the electrical performance test by contacting the pads of the chip with a Probe card before dicing the wafer to determine which chips are qualified, and evaluate the chips in the wafer 100 in combination with the test results, and finally divide the chips in the wafer 100 into a first chip C1 and a second chip C2.

In some embodiments, one or more of the chips may be logic chips, such as a Central Processing Unit (CPU) chip, a Micro Control Unit (MCU) chip, an Input Output (IO) chip, a baseband (BB) chip, an Application Processor (AP) chip, a system on a chip (SoC), an integrated system on a chip (SoIC), or the like. One or more of the chips may also be a memory semiconductor chip that includes a memory device. For example, the memory device includes a nonvolatile memory device such as at least one of a flash memory, a phase change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a ferroelectric random access memory (FeRAM), and a Resistive Random Access Memory (RRAM). For example, the flash memory includes a NAND flash memory or a V-NAND flash memory. In some embodiments, the memory device includes a volatile memory device, such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM). Among them, a memory semiconductor chip includes a semiconductor device including a plurality of individual devices of various types. The plurality of individual devices include various microelectronic devices such as, for example, metal Oxide Semiconductor Field Effect Transistors (MOSFETs) including CMOS transistors, system large scale integrated circuits (LSIs), active devices, or passive devices.

Wafer 100 may include a substrate 101 having one or more active or passive devices formed therein, wherein the material of substrate 101 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials such as III-V compounds such as gallium arsenide. Wafer 100 may also include device regions 102 for forming chip devices. The device region 102 may be formed to include active devices such as transistors or diodes, or passive devices such as capacitors, inductors, resistors, and the like. An interconnect layer may be formed on the device region 102 for connecting the device region 102 with external control signals or input-output signals.

The interconnect layer may include a dielectric layer 105, and a conductive layer 103 and a via 104 formed in the dielectric layer 105. The dielectric layer of the interconnect junction layer may be formed of a low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride carbide (SiOCN), etc., and illustratively the step of forming the interconnect layer includes depositing the dielectric material, which may include one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof, which may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof, and then etching the dielectric material to form openings and sequentially depositing conductive material within the openings to form conductive layer 103 and via 104. The materials of the conductive layer 103 and the via 104 may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof, and a barrier layer may also be formed within the conductive layer 103 and the via 104, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like. A re-wiring layer 106 may also be formed over the interconnect layer, the re-wiring layer 106 may re-wire the signal and power pins on the chip to enable electrical connection with connection points on an external circuit board while also significantly increasing the I/O number of the chip, the re-wiring layer 106 may be formed with a conductive layer, wherein the material of the conductive layer may include, but is not limited to, copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), silicide, or any combination thereof.

S200 forms a plurality of contact plugs 111 on the wafer 100, and the contact plugs 111 are electrically connected to the first chip C1 and the second chip C2 of the wafer 100.

In some embodiments, referring to fig. 3-8, in particular, the specific steps of forming the plurality of contact plugs 111 on the wafer 100 may include depositing an insulating layer 107 on the wafer 100, and planarizing the surface of the insulating layer 107, where the insulating layer 107 covers the first chip C1 and the second chip C2, and illustratively, the material of the insulating layer 107 may include silicon oxide, where the insulating layer 107 is used to isolate the subsequent contact plugs 111 from other structures on the wafer 100 to avoid shorting, and the planarizing process may use a chemical mechanical Polishing (CHEMICAL MECHANICAL Polishing) technique to remove irregularities on the surface of the insulating layer 107, ensure a smooth surface, and provide a flat surface for the subsequent contact plug 111 formation. The insulating layer 107 is patterned to form a first trench 109, the first trench 109 exposes a portion of the surfaces of the first chip C1 and the second chip C2, and illustratively, a photoresist layer 108 may be coated on the surface of the insulating layer 107, then the photoresist layer 108 is patterned, the insulating layer 107 is etched with the photoresist layer 108 as a mask, so as to form the first trench 109, and the etching process may include wet etching or dry etching. The method includes depositing a conductive material layer 110 in the first trench 109 to form a contact plug 111, removing the conductive material layer 110 deposited on the surface of the wafer 100, and planarizing the surface of the wafer 100 to form the contact plug 111, wherein the material of the conductive material layer 110 may include, but is not limited to, one or more of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni).

S300 forms a dummy passivation layer 112 on the first chip C1 of the wafer 100, forms a passivation layer 113 in a region other than the first chip C1, and the dummy passivation layer 112 and the passivation layer 113 collectively cover the plurality of contact plugs 111.

In some embodiments, referring to fig. 9-11, a dummy passivation layer 112 is formed on a first chip C1 of the wafer 100, a passivation layer 113 is formed on a second chip of the wafer 100, a portion of the passivation layer 113 covering the dummy passivation layer 112, the dummy passivation layer 112 and the passivation layer 113 may be sequentially formed by deposition, which may include, but is not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), spin Coating (Spin Coating), and a planarization process is performed on the passivation layer 113 and the dummy passivation layer 112 after the deposition process, for example, the planarization process may be chemical mechanical polishing.

In some embodiments, the material of the dummy passivation layer 112 may include Polyimide (PI), and the material of the passivation layer 113 may include silicon carbide nitride (SiCN). In the packaging process, polyimide (PI) can effectively protect devices inside the chip from external environments (such as moisture, oxygen and the like), and meanwhile, the difference of Coefficient of Thermal Expansion (CTE) between the packaging material and the chip is reduced, the stress is reduced, and the reliability and the service life of the packaging structure are improved. The passivation layer 113 is formed of silicon carbide nitride (SiCN) to protect the chip surface from external environmental influences such as moisture and contaminants while providing electrical insulation and mechanical protection, and its low dielectric constant helps to reduce capacitive effects during signal transmission and improve circuit performance.

In some embodiments, the dummy passivation layer 112 has a thickness in the range of 1-10 μm, which can ensure that devices inside the chip are not damaged when the later-formed chip stack structure is separated. The passivation layer 113 may have a thickness in the same range as the dummy passivation layer 112, for example, 1 to 10 μm, and thus may protect the chip.

S400 patterns the passivation layer 113 to expose a portion of the surface of the contact plug 111, and forms a bonding pad 115 within the patterned passivation layer 113, the bonding pad 115 covering a portion of the surface of the contact plug 111 and being electrically connected to the second chip C2 through the contact plug 111.

In some embodiments, referring to fig. 11-13, after forming the dummy passivation layer 112 and the passivation layer 113, a bonding pad 114 for encapsulation may be further formed on the wafer 100, specifically, a photoresist may be deposited on the passivation layer 113, the passivation layer 113 may be etched with the patterned photoresist as a mask to form a second trench 114, wherein the second trench 114 exposes a surface of the contact plug 111, a conductive material is deposited in the second trench 114, and the conductive material covering the surface of the passivation layer 113 is removed to form the bonding pad 115, and the conductive material may include, for example, but not limited to, one or more of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), and may be other metal compounds or metal silicides. The rewiring layers 106 of the first chip C1 and the second chip C2 are correspondingly connected to the bonding pads 115 through the contact plugs 111.

S500 hybrid bonding is performed on at least two wafers 100 to form the bonding structure 10.

In some embodiments, referring to fig. 14-15, after forming the bond pads 115, the two wafers 100 are hybrid bonded to form the bond structure 10. Hybrid bonding is a direct bonding technique (e.g., bonding between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and metal-to-metal bonding and dielectric-to-dielectric bonding can be achieved simultaneously. Since the number of the first chip C1 and the second chip C2 of each wafer 100 may be different, the bonding structure 10 may include a bonding structure of the first chip C1 and the second chip C2, that is, a bonding of the passivation layer 112 and the dummy passivation layer 113 and a bonding pad 115 and the dummy passivation layer 113, and a bonding structure of the second chip C2 and the second chip C2, that is, a bonding of the passivation layer 112 and a bonding pad 115 and the bonding pad 115, and a bonding structure of the first chip C1 and the first chip C1, that is, a bonding of the dummy passivation layer 113 and the dummy passivation layer 113.

In some embodiments, the temperature range of the hybrid bonding may be 250-350 ℃, so that the bonding pads 115 may bond together while also ensuring that the passivation layer 112 and the dummy passivation layer 113 and the bonding pads 115 and the dummy passivation layer 113 in the bonding structure 10, or the bonding of the passivation layer 112 and the passivation layer 112, or the dummy passivation layer 113 and the dummy passivation layer 113, form a stable bonding interface, while the low temperature bonding also avoids damage to devices within the wafer 100, thereby improving the structural stability and reliability of the bonding structure 10. An exemplary bonding pad 115 may include copper (Cu), the bonding pads 115 of the two wafers 100 may be bonded to each other by Cu-Cu hybrid bonding, and the bonding pads 115 of the two wafers 100 may thermally expand to contact each other by a heat treatment process at 250-350 ℃.

In some embodiments, thinning the substrate 101 of the wafer 100 may also be included prior to hybrid bonding the wafer 100, thereby reducing the overall volume of the bonded structure 10.

In some embodiments, after performing the hybrid bonding, dicing the bonding structure 10 is further included to obtain the chip stack structure 20. Illustratively, the process of cutting the bonded structure 10 includes, but is not limited to, laser cutting, mechanical cutting (e.g., blade cutting), or water jet cutting. Taking Laser cutting or mechanical cutting as an example, in the cutting process, a Laser beam or a blade moves along a preset cutting path SL to divide the bonding structure 10 into individual chip stacking structures 20, wherein in the Laser cutting, the Laser can be an ultraviolet Laser (UV Laser), the wavelength of the ultraviolet Laser is shorter, the energy density is higher, the cutting accuracy can be improved, finer cutting is realized, and the thermal influence on the bonding structure 10 is reduced.

In some embodiments, referring to fig. 16, when the chip stack structure 20 includes the dummy passivation layer 112, the chip stack structure 20 is separated to obtain at least one first chip C1. For example, after the wafer 100 is inspected for the yield, the inspected defective chip is the first chip C1, and the inspected qualified chip is the second chip C2, so when the chip stack structure 20 includes the dummy passivation layer 112, the dummy passivation layer 112 is formed on the first chip C1, that is, the chip stack structure 20 includes the defective chip, that is, the first chip C1, and at this time, the chip stack structure 20 may include a bonding structure between the first chip C1 and the second chip C2 or a bonding structure between the first chip C1 and the first chip C1. When the chip stacking structure 20 includes the first chip C1 and the second chip C2 that are bonded, the chip stacking structure 20 is separated, that is, the first chip C1 and the second chip C2 are separated, and the second chip C2 is re-bonded with the second chip C2 separated from the other chip stacking structures 20, so that the utilization rate of the qualified chip, that is, the second chip C2 is improved, and the yield of wafer bonding is improved; when the chip stacking structure 20 includes the bonded first chip C1 and the first chip C1, the chip stacking structure 20 is separated, that is, the first chip C1 and the first chip C1 are separated, the separated first chip C1 can be repaired, and the repaired first chip C1 is bonded again, so that the utilization rate of the defective chip, that is, the first chip C1, is improved, and the wafer bonding yield is also improved.

When the chip stack structure 20 includes the first chip C1 and the second chip C2 bonded, since the dummy passivation layer 112 is formed on the first chip C1 and the passivation layer 113 is formed on the second chip C2, when the chip stack structure 20 is separated, since the material of the dummy passivation layer 112 and the passivation layer 113 is different, the bonding force is weak, for example, the material of the dummy passivation layer 112 may be Polyimide (PI), the material of the passivation layer 113 may be silicon carbide nitride (SiCN), and the separation of the first chip C1 and the second chip C2 may be achieved by precisely cutting at the interface of the dummy passivation layer 112 and the passivation layer 113 using the difference of the bonding force therebetween through a chip separation technique. For example, the first chip C1 and the second chip C2 may be peeled by Laser or low temperature, the first chip C1 and the second chip C2 may not be damaged while the separation of the first chip C1 and the second chip C2 is achieved, for example, when the Laser is peeled, the Laser may be an ultraviolet Laser (UV Laser), the wavelength of the ultraviolet Laser is shorter, the energy density is higher, and when the material of the pseudo passivation layer 112 is Polyimide (PI), the absorption of the ultraviolet Laser is better, so that the accuracy of the dicing can be effectively improved, the finer dicing is achieved, and meanwhile, the thermal influence on the chip stacking structure 20 is reduced, when the low temperature peeling is achieved, the temperature of the low temperature peeling may be-100 ℃ to 25 ℃, the bonding strength between the pseudo passivation layer 112 and the passivation layer 113 is facilitated to be weakened, and when the material of the pseudo passivation layer 112 is Polyimide (PI), the brittleness of the pseudo passivation layer 112 is also increased with the decrease of the peeling temperature, the bonding strength is further reduced, and therefore, the first chip C1 and the second chip C2 are easily separated.

When the chip stacking structure 20 includes the first chip C1 and the first chip C1 that are bonded, since the dummy passivation layer 112 is formed on the first chip C1, when the chip stacking structure 20 is separated, since the bonding force of the material of the dummy passivation layer 112 is weak, laser or low-temperature stripping may also be used to recover the first chip C1, and the principle is the same as that described above and is not repeated herein.

In some embodiments, the chip stack structure 20 may include a 2D, 2.5D, or 3D architecture or any other type of packaging structure composed of semiconductor chips including, but not limited to, logic devices, volatile memory devices (e.g., dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM)), and non-volatile memory devices (e.g., flash memory).

Accordingly, still another embodiment of the present disclosure provides a bonding structure 10, which may be manufactured by the bonding method manufactured through the above steps, referring to fig. 10, the bonding structure 10 includes at least two wafers 100, the wafers 100 including a plurality of first chips C1 and a plurality of second chips C2 and a plurality of contact plugs 111, the contact plugs 111 electrically connected to the first chips C1 and the second chips C2, a dummy passivation layer 112 and a passivation layer 113, the dummy passivation layer 112 being disposed on the first chips C1, the passivation layer 113 being disposed at an area outside the first chips C1, the dummy passivation layer 112 and the passivation layer 113 together covering the plurality of contact plugs 111, and a bonding pad 115 disposed at a surface of a portion of the contact plugs 111 and electrically connected to the second chips C2 through the contact plugs 111, wherein a material of the bonding pad 115 may include, but is not limited to, one or more of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), and a material of the bonding pad 115 may include, but is not limited to, one or more of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), or a metal silicide.

In some embodiments, the wafer 100 may include a plurality of first chips C1 and a plurality of second chips C2, wherein the first chips C1 and the second chips C2 may be semiconductor chips, which may be memory semiconductor chips including memory devices. For example, the memory device includes a nonvolatile memory device such as at least one of a flash memory, a phase change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a ferroelectric random access memory (FeRAM), and a Resistive Random Access Memory (RRAM). For example, the flash memory includes a NAND flash memory or a V-NAND flash memory. In some embodiments, the memory device includes a volatile memory device, such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM). Among them, a memory semiconductor chip includes a semiconductor device including a plurality of individual devices of various types. The plurality of individual devices include various microelectronic devices such as, for example, metal Oxide Semiconductor Field Effect Transistors (MOSFETs) including CMOS transistors, system large scale integrated circuits (LSIs), active devices, or passive devices.

In summary, according to the embodiment of the disclosure, a passivation layer is formed on a first chip of a wafer, a passivation layer is formed in a region except the first chip, the passivation layer and the passivation layer cover a plurality of contact plugs together, the passivation layer is patterned to expose a portion of the surface of the contact plugs, a bonding pad is formed in the patterned passivation layer, the bonding pad covers a portion of the surface of the contact plugs and is electrically connected with a second chip through the contact plugs, and at least two wafers are subjected to hybrid bonding to form a bonding structure. By forming the pseudo passivation layer on the first chip, the first chip can be separated from other chips after the wafer forms the bonding structure, so that the wafer bonding yield is improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.

Claims (11)

1. A bonding method, comprising: Providing a wafer, wherein the wafer includes a plurality of first chips and a plurality of second chips; forming a plurality of contact plugs on the wafer, wherein the contact plugs are electrically connected to the first chip and the second chip of the wafer; forming a dummy passivation layer on the first chip of the wafer, and forming a passivation layer in a region other than the first chip, wherein the dummy passivation layer and the passivation layer together cover the plurality of contact plugs; Patterning the passivation layer to expose a portion of the surface of the contact plug, and forming a bonding pad in the patterned passivation layer, wherein the bonding pad covers a portion of the surface of the contact plug and is electrically connected to the second chip through the contact plug; At least two of the wafers are hybrid-bonded to form a bonded structure. 2 . The bonding method according to claim 1 , further comprising testing the wafer and dividing the chips in the wafer into a plurality of the first chips and a plurality of the second chips according to the test results. 3. The bonding method according to claim 1 , wherein forming a plurality of contact plugs on the wafer comprises: depositing an insulating layer on the wafer and planarizing a surface of the insulating layer, wherein the insulating layer covers the first chip and the second chip; patterning the insulating layer to form a first trench, wherein the first trench exposes a portion of the surface of the first chip and the second chip; depositing a conductive material in the trench to form the contact plug; The conductive material deposited on the surface of the wafer is removed, and the surface of the wafer is planarized. 4. The bonding method according to claim 3, wherein a dummy passivation layer is formed on the first chip of the wafer, and a passivation layer is formed in an area other than the first chip, wherein the dummy passivation layer and the passivation layer together cover the plurality of contact plugs, comprising: forming a dummy passivation layer on the first chip of the wafer; forming a passivation layer in an area other than the first chip, wherein a portion of the passivation layer covers the second chip and the dummy passivation layer; The passivation layer and the dummy passivation layer are planarized. 5. The bonding method according to claim 1, wherein the material of the dummy passivation layer comprises polyimide, and the material of the passivation layer comprises silicon carbide nitride. 6. The bonding method according to claim 1, wherein the thickness of the pseudo passivation layer is in the range of 1-10 μm. The bonding method according to claim 1 , wherein the temperature of the hybrid bonding is 250-350° C. 8 . The bonding method according to claim 1 , further comprising cutting the bonded structure to obtain a chip stacking structure after performing the hybrid bonding. 9 . The bonding method according to claim 8 , wherein when the chip stacking structure includes the dummy passivation layer, the chip stacking structure is separated to obtain at least one first chip. 10 . The bonding method according to claim 9 , wherein the method for separating the chip stacking structure comprises: laser or low-temperature peeling. 11. A bonding structure, characterized in that it is prepared by the bonding method according to any one of claims 1 to 7, comprising: at least two wafers, each wafer comprising a plurality of the first chips, a plurality of the second chips, and a plurality of contact plugs, wherein the contact plugs are electrically connected to the first chips and the second chips; a dummy passivation layer and a passivation layer, wherein the dummy passivation layer is disposed on the first chip, and the passivation layer is disposed in a region outside the first chip, and the dummy passivation layer and the passivation layer jointly cover the plurality of contact plugs; A bonding pad is provided on a surface of a portion of the contact plug and is electrically connected to the second chip through the contact plug.