CN114497019A - Multi-chip three-dimensional integrated structure and manufacturing method - Google Patents

Abstract

The invention discloses a multi-chip three-dimensional integrated structure and a manufacturing method, comprising: stacking several substrates layer by layer to form a top substrate, an intermediate substrate and a bottom substrate; The top substrate, the middle substrate and the bottom substrate are all bonded with chips, and the passive components are fixed on the top substrate; the rest surface except the lower surface of the bottom substrate is encapsulated by plastic sealing compound. By stacking the substrates layer by layer and bonding the chips on the substrate, the present invention can realize the three-dimensional integration of multiple chips of different materials and different functions, and has universal applicability to finished chips prepared by different materials and different processes. Single-layer functional components are formed by micro-assembly of chips on the substrate, and functional components are tested to eliminate unqualified single-layer functional components in advance to improve the integration yield.

Description

A kind of multi-chip three-dimensional integrated structure and manufacturing method

technical field

The invention belongs to the field of chip packaging, and relates to a multi-chip three-dimensional integrated structure and a manufacturing method.

Background technique

Multi-chip integration is developing from two-dimensional to three-dimensional, but there are many restrictions on directly punching TSV through holes on the chip wafer, the process requirements are high, and a full understanding of the circuit and structure inside the chip is required, and the chip wafer size requirements are the same as TSV. The size of the process line is consistent, the chip wafer is designed and processed with consideration of the subsequent TSV holes, and the TSV holes need to isolate the transition area (keep-out area), etc., the chips used need to be specially designed to punch TSV holes and carry out stack. At the same time, the vertical stacking of chips also has certain requirements for the equivalence of the size of the chips. In addition, the TSV process has not been moved to compound semiconductor substrates such as GaAs, InP, SiC, GaN, etc., so the chips based on these compound semiconductor substrates are currently Vertical vias connecting the upper and lower surfaces have not been prepared. How to realize the high-density three-dimensional integration of these chips of different sizes, different materials, different processes, and different functions is an urgent technical problem that needs to be solved.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problems in the prior art, to provide a multi-chip three-dimensional integrated structure and a manufacturing method, which can integrate chips with different functions, different materials and different structures, and can reduce the research and development cost of the electronic system integrated microsystem , and also meet the electronic system requirements of many varieties and small batches.

To achieve the above object, the present invention adopts the following technical solutions to realize:

A multi-chip three-dimensional integrated structure, comprising: a multi-chip three-dimensional integrated structure component;

The multi-chip three-dimensional integrated structure assembly includes chips, passive devices, plastic packaging materials and several substrates;

Several substrates are stacked layer by layer, including a top substrate, an intermediate substrate and a bottom substrate;

The top substrate and the middle substrate, the middle substrate and the bottom substrate are all connected by the interlayer bump solder balls; the top substrate, the middle substrate and the bottom substrate are all bonded with chips; the passive devices are fixed on the top substrate; plastic sealing compound The rest of the package except the lower surface of the underlying substrate.

A further improvement of the present invention is:

The top substrate, the middle substrate and the bottom substrate are respectively a first substrate, a second substrate and a third substrate;

The first substrate includes external pads on the lower surface of the first substrate and a first interlayer pad on the upper surface of the first substrate; the second substrate includes a first pad boss on the lower surface of the second substrate and a second pad on the lower surface a second interlayer pad on the upper surface of the substrate; the third substrate comprises a second pad boss on the lower surface of the third substrate and a passive device surface mount pad on the upper surface of the third substrate;

The chip includes a first chip, a second chip, a third chip, a fourth chip and a fifth chip; the interlayer bump solder balls include a first solder ball and a second solder ball;

The first chip is bonded on the upper surface of the third substrate; the second chip and the third chip are bonded on the upper surface of the second substrate; the fourth chip and the fifth chip are bonded on the upper surface of the first substrate;

The passive device is attached to the upper surface of the third substrate by the passive device surface mount pad, and is located around the first chip; the first substrate and the second substrate are connected by the first solder balls; the second substrate The second solder ball is connected to the third substrate; the first solder ball is soldered between the first interlayer pad and the first pad boss, and the second solder ball is soldered to the second interlayer pad and the first pad. Between the two pad bosses;

It also includes third solder balls; the third solder balls are located on the external pads; the plastic sealing compound encapsulates the remaining surfaces except the lower surface of the first substrate.

The first substrate, the second substrate and the third substrate are all TSV silicon transfer substrates.

The first chip, the second chip, the third chip, the fourth chip and the fifth chip are respectively bonded on the third substrate, the second substrate and the first substrate by flip-chip bonding;

The first chip is bonded to the first chip bonding pads on the upper surface of the third substrate through the first flip-chip bumps on the first chip;

The second chip and the third chip are respectively bonded to the second chip bonding pads on the upper surface of the second substrate through the second flip-chip bumps on the second chip and the third flip-chip bumps on the third chip;

The fourth chip and the fifth chip are respectively bonded to the third chip bonding pads on the upper surface of the first substrate through the fourth flip chip bumps on the fourth chip and the fifth flip chip bumps on the fifth chip.

The first substrate further includes a first silicon substrate, a first TSV via, a first multi-layer metal redistribution layer, a first inter-metal dielectric layer, a second multi-layer metal re-distribution layer and a second inter-metal dielectric layer ;

The first multi-layer metal redistribution layer and the first metal interlayer dielectric layer are located on the upper surface of the first substrate; the second multi-layer metal redistribution layer and the second metal interlayer dielectric layer are located on the lower surface of the first substrate; the first The TSV through hole passes through the first silicon substrate, and the first silicon substrate is located in the middle of the first substrate;

The second substrate further includes a second silicon substrate, a second TSV via, a third multi-layer metal redistribution layer, a third inter-metal dielectric layer, a fourth multi-layer metal redistribution layer, and a fourth inter-metal dielectric layer ;

The third multi-layer metal redistribution layer and the third metal interlayer dielectric layer are located on the upper surface of the second substrate; the fourth multi-layer metal redistribution layer and the fourth metal interlayer dielectric layer are located on the lower surface of the second substrate; the second The TSV through hole passes through the second silicon substrate, and the second silicon substrate is located in the middle of the second substrate;

The third substrate further includes a third silicon substrate, a third TSV via, a fifth multi-layer metal redistribution layer, a fifth metal interlayer dielectric layer, a sixth multi-layer metal redistribution layer, and a sixth inter-metal dielectric layer ;

The fifth multi-layer metal redistribution layer and the fifth metal interlayer dielectric layer are located on the upper surface of the third substrate; the sixth multi-layer metal redistribution layer and the sixth metal interlayer dielectric layer are located on the lower surface of the third substrate; the third The TSV via passes through the third silicon substrate, and the third silicon substrate is located in the middle of the third substrate.

The plastic packaging material adopts the plastic packaging material whose thermal expansion coefficient is less than 10ppm/℃; the passive device adopts the SMD passive component or the chip type passive component; the thickness of the second chip, the third chip, the fourth chip and the fifth chip is less than 200 microns .

Also includes an underfill material, the underfill material includes a first filling material, a second filling material, a third filling material, a fourth filling material and a fifth filling material; the first filling material is used to fill the first chip and the third substrate. gaps on the surface; the second filling material and the third filling material are respectively used to fill the gaps between the second chip, the third chip and the upper surface of the second substrate; the fourth filling material and the fifth filling material are respectively used to fill the fourth chip, the gap between the fifth chip and the upper surface of the first substrate;

It also includes a sixth filling material and a seventh filling material; the sixth filling material is used to fill between the second substrate and the third substrate; the seventh filling material is used to fill the space between the first substrate and the second substrate.

It also includes a protective film layer, the protective film layer covers the lower surface of the first substrate, wraps the root of the third solder ball close to the external pad portion, and the crown portion of the top of the third solder ball is exposed outside the protective film layer.

It also includes a metal welding post and a welding cap, the metal welding post is welded on the external pad, and the welding cap is located at one end of the metal welding post.

A method for manufacturing a multi-chip three-dimensional integrated structure, comprising:

Prepare the substrate wafers corresponding to the first substrate, the second substrate and the third substrate, and perform the appearance test and the double-sided electrical continuity test on each of the first substrate, the second substrate and the third substrate on the substrate wafer, and the test is passed. The substrate enters the next single-layer component micro-assembly process;

The fourth chip and the fifth chip are respectively bonded to the third chip bonding pads on the upper surface of the first substrate through the fourth flip chip bumps on the fourth chip and the fifth flip chip bumps on the fifth chip , and apply the fourth filling material and the fifth filling material to fill the gap between the fourth chip, the fifth chip and the upper surface of the first substrate;

Bonding the second chip and the third chip on the second chip bonding pads on the upper surface of the second substrate through the second flip-chip bumps on the second chip and the third flip-chip bumps on the third chip respectively ; And apply the second filling material and the third filling material to fill the gap between the second chip, the third chip and the upper surface of the second substrate;

bonding the first chip on the first chip bonding pad on the upper surface of the third substrate through the first flip-chip bump on the first chip, and applying a first filling material for filling the first chip and the third substrate gaps in the upper surface;

The passive device is surface-mounted on the upper surface of the first substrate through the passive device surface-mounting pad, and is located around the first chip; The back side of the chip; the appearance test and electrical test are performed on the single-layer functional components of the first substrate, the second substrate and the third substrate, and the single-layer components of the first substrate, the second substrate and the third substrate that have passed the test enter the ball-mounting process;

implanting first solder balls on the first interlayer pads on the upper surface of the first substrate; implanting second solder balls on the second interlayer pads on the upper surface of the second substrate;

Through the bonding of the first solder balls with the first pad bosses on the lower surface of the second substrate and the bonding of the second solder balls with the second pad bosses on the lower surface of the third substrate, the first substrate, the second The stacking of the single-layer components of the substrate and the third substrate, and applying the sixth filling material and the seventh filling material, and encapsulating the other sides and the top surface of the lower surface of the first substrate except the surface where the outer pads are located with plastic sealing compound seal to form an envelope;

The top surface of the plastic packaging material is thinned to expose the substrate of the first chip; the external third solder balls are implanted on the external pads on the lower surface of the first substrate; and after cutting and separation, a multi-chip three-dimensional integrated structure assembly is formed.

Compared with the prior art, the present invention has the following beneficial effects:

By stacking the substrates layer by layer and bonding the chips on the substrate, the present invention can realize the three-dimensional integration of multiple chips of different materials and different functions, and has universal applicability to finished chips prepared by different materials and different processes. Single-layer functional components are formed by micro-assembly of chips on the substrate, and single-layer functional components are tested to eliminate unqualified single-layer functional components in advance to improve the integration yield.

Description of drawings

In order to describe the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 is a first schematic diagram of a multi-chip three-dimensional integrated structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a bare component and a bare component dummy array assembled on an underlying substrate wafer according to an embodiment of the present invention;

3 is a second schematic diagram of a multi-chip three-dimensional integrated structure according to an embodiment of the present invention;

4 is a third schematic diagram of a multi-chip three-dimensional integrated structure according to an embodiment of the present invention;

5 is a fourth schematic diagram of a multi-chip three-dimensional integrated structure according to an embodiment of the present invention;

6 is a schematic diagram of another bare component and a bare component dummy array assembled on an organic carrier strip according to an embodiment of the present invention.

Among them, 10-first substrate; 11-first silicon substrate; 12-first TSV through hole; 13-first multi-layer metal rewiring layer; 14-first metal interlayer dielectric layer; layer metal redistribution layer; 16-second metal interlayer dielectric layer; 17-third die bonding pad; 18-external pad; 19-first interlayer pad; 20-second substrate; 21-th Two silicon substrates; 22-the second TSV via; 23-the third multi-layer metal redistribution layer; 24-the third metal interlayer dielectric layer; 25-the fourth multi-layer metal redistribution layer; 26-the fourth metal interlayer dielectric layer; 27-second chip bonding pad; 28-first pad boss; 29-second interlayer pad; 30-third substrate; 31-third silicon substrate; 32-th Three TSV vias; 33- the fifth multi-layer metal re-wiring layer; 34- the fifth metal inter-layer dielectric layer; 35- the sixth multi-layer metal re-wiring layer; 36- the sixth metal inter-layer dielectric layer; 37- the first 1 chip bonding pad; 38 - second pad boss; 39 - passive device surface mount pad; 40 - chip package organic carrier board; 41 - first chip; 42 - second chip; 43 - first chip Three chips; 44-fourth chip; 45-fifth chip; 46-passive components; 50-third solder ball; 51-first flip-chip bump; 52-second flip-chip bump; 53-third Flip Chip Bump; 54 - Fourth Flip Chip Bump; 55 - Fifth Flip Chip Bump; 56 - First Solder Ball; 57 - Second Solder Ball; 61 - First Filling Material; 62 - Second Filling Material 63-Third filling material; 64-Fourth filling material; 65-Fifth filling material; 66-Surface mount solder joint; 67-Sixth filling material; 70-plastic compound; 71-protective film layer; 72-metal solder post; 73-solder cap; 80-bare component; 81-bare component dummy; 100-multi-chip three-dimensional integrated structure component; 101-substrate wafer; 200 - the first multi-chip stereoscopic integrated structure component; 300 - the second multi-chip stereoscopic integrated structure component; 400 - the third multi-chip stereoscopic integrated structure component; 401 - the chip packaging organic carrier board strip.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inside", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings , or the orientation or positional relationship that the product of the invention is usually placed in use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed in a specific orientation and operation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

Furthermore, the presence of the term "horizontal" does not imply that the component is required to be absolutely horizontal, but rather may be tilted slightly. For example, "horizontal" only means that its direction is more horizontal than "vertical", it does not mean that the structure must be completely horizontal, but can be slightly inclined.

In the description of the embodiments of the present invention, it should also be noted that, unless otherwise expressly specified and limited, the terms "set", "installed", "connected" and "connected" should be understood in a broad sense. It can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, and it can be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

Below in conjunction with accompanying drawing, the present invention is described in further detail:

Referring to FIG. 1, the present invention discloses a multi-chip three-dimensional integrated structure, including: a multi-chip three-dimensional integrated structure assembly 100; the multi-chip three-dimensional integrated structure assembly 100 includes a chip, a passive device 46, a plastic sealing compound 70 and several substrates; several The substrates are stacked layer by layer to form a top substrate, an intermediate substrate and a bottom substrate;

The top substrate and the middle substrate, the middle substrate and the bottom substrate are all connected by interlayer bump solder balls; the top substrate, the middle substrate and the bottom substrate are all bonded with chips, and the passive device 46 is fixed on the top substrate; plastic encapsulation The compound 70 encapsulates the remaining surfaces except the lower surface of the underlying substrate.

The top substrate, the middle substrate and the bottom substrate are the first substrate 10, the second substrate 20 and the third substrate 30 respectively;

The first substrate 10 includes external pads 18 on the lower surface of the first substrate 10 and first interlayer pads 19 on the upper surface of the first substrate 10 ; the second substrate 20 includes first solder pads on the lower surface of the second substrate 20 . The pad boss 28 and the second interlayer pad 29 on the upper surface of the second substrate 20; the third substrate 30 includes a second pad boss 38 on the lower surface of the third substrate 30 and a Source device surface mount pad 39;

The chips include a first chip 41, a second chip 42, a third chip 43, a fourth chip 44 and a fifth chip 45; the interlayer bump solder balls include a first solder ball 56 and a second solder ball 57;

The first chip 41 is bonded on the upper surface of the third substrate 30; the second chip 42 and the third chip 43 are bonded on the upper surface of the second substrate 20; the fourth chip 44 and the fifth chip 45 are bonded on the first substrate 10's upper surface;

The thicknesses of the second chip 42 , the third chip 43 , the fourth chip 44 and the fifth chip 45 are less than 200 μm; the second flip-chip bumps 52 , the third flip-chip bumps 53 , and the fourth flip-chip bumps are not included, respectively. The thickness of the point 54 and the fifth flip-chip bump 55; in order to maintain a small distance between adjacent substrate layers, it is more beneficial to increase the electrical interconnection density of the interlayer bump solder balls, and at the same time reduce the multi-chip three-dimensional integrated structure assembly. Overall height, improve integration;

The passive device 46 is soldered on the passive device surface mount pad 39 on the upper surface of the third substrate 30 to form a surface mount pad 66 to realize surface mount assembly on the third substrate 30 and is located around the first chip 41 ; Passive device 46 adopts SMD passive components or chip passive components;

The first substrate 10 and the second substrate 20 are connected by the first solder balls 56; the second substrate 20 and the third substrate 30 are connected by the second solder balls 57; the first solder balls 56 are soldered to the first layer Between the interlayer pads 19 and the first pad bosses 28, the second solder balls 57 are soldered between the second interlayer pads 29 and the second pad bosses 38; the first solder balls 56 and the second solder balls 57 realizes the electrical connection between adjacent substrate layers, and at the same time acts as a physical support for the superstructure. The first solder balls 56 and the second solder balls 57 can be C4 solder balls, solder balls with a core-shell structure, or a copper pillar solder cap structure. The preparation methods of the first solder balls 56 and the second solder balls 57 It can be a ball-mounting method or an electroplating method.

It also includes third solder balls 50 ; the third solder balls 50 are located on the external pads 18 ; the plastic sealing compound 70 encapsulates the remaining surfaces except the lower surface of the first substrate 10 .

The first substrate 10 , the second substrate 20 and the third substrate 30 are all TSV silicon interposer substrates.

The first chip 41, the second chip 42, the third chip 43, the fourth chip 44 and the fifth chip 45 are respectively bonded on the third substrate 30, the second substrate 20 and the first substrate 10 by flip-chip bonding;

The first chip 41 is bonded to the first chip bonding pads 37 on the upper surface of the third substrate 30 through the first flip-chip bumps 51 on the first chip 41;

The second chip 42 and the third chip 43 are respectively bonded to the second surface of the upper surface of the second substrate 20 through the second flip-chip bumps 52 on the second chip 42 and the third flip-chip bumps 53 on the third chip 43 , respectively. on the chip bonding pad 27;

The fourth chip 44 and the fifth chip 45 are respectively bonded to the third chip on the upper surface of the first substrate 10 through the fourth flip-chip bumps 54 on the fourth chip 44 and the fifth flip-chip bumps 55 on the fifth chip 45 . on the die bonding pads 17 .

The chips on the upper surface of the third substrate 30 are preferably chips with higher power and higher requirements for heat dissipation. Because the backside of the chip is exposed, it can be in direct contact with heat sinks, cold plates and other heat dissipation devices, and the heat dissipation effect is the best; The chips on the upper surface of the second substrate 20 preferably interact with the chips on the top layer more frequently, and the data transmission speed is required to be high. low chip. For example, the chips on the upper surface of the third substrate 30 are preferably information processing computing chips such as CPU, GPU, FPGA, DSP, and SOC, and the chips on the upper surface of the second substrate 20 are preferably memory chips such as DDR, which are used to store data in the information processing and computing process. And the temporary file, the chip on the upper surface of the first substrate 10 is preferably a flash memory chip, which is used to save the program code.

The first substrate 10 further includes a first silicon substrate 11, a first TSV via 12, a first multi-layer metal redistribution layer 13, a first inter-metal dielectric layer 14, a second multi-layer metal redistribution layer 15, and a first multi-layer metal redistribution layer 13. Two metal interlayer dielectric layers 16;

The first multi-layer metal redistribution layer 13 and the first inter-metal dielectric layer 14 are located on the upper surface of the first substrate 10 ; the second multi-layer metal re-distribution layer 15 and the second inter-metal dielectric layer 16 are located on the first substrate 10 The lower surface of the first TSV through hole 12 passes through the first silicon substrate 11, and the first silicon substrate 11 is located in the middle of the first substrate 10;

The second substrate 20 further includes a second silicon substrate 21, a second TSV via 22, a third multi-layer metal redistribution layer 23, a third inter-metal dielectric layer 24, a fourth multi-layer metal redistribution layer 25 and a third multi-layer metal redistribution layer 23. Four metal interlayer dielectric layers 26;

The third multi-layer metal redistribution layer 23 and the third inter-metal dielectric layer 24 are located on the upper surface of the second substrate 20 ; the fourth multi-layer metal redistribution layer 25 and the fourth inter-metal dielectric layer 26 are located on the second substrate 20 The lower surface of the second TSV through hole 22 passes through the second silicon substrate 21, and the second silicon substrate 21 is located in the middle of the second substrate 20;

The third substrate 30 further includes a third silicon substrate 31, a third TSV via 32, a fifth multi-layer metal redistribution layer 33, a fifth metal interlayer dielectric layer 34, a sixth multi-layer metal redistribution layer 35, and a fifth multi-layer metal redistribution layer 33. Six metal interlayer dielectric layers 36;

The fifth multi-layer metal redistribution layer 33 and the fifth metal interlayer dielectric layer 34 are located on the upper surface of the third substrate 30 ; the sixth multi-layer metal redistribution layer 35 and the sixth metal interlayer dielectric layer 36 are located on the third substrate 30 The third TSV through hole 32 passes through the third silicon substrate 31 , and the third silicon substrate 31 is located in the middle of the third substrate 30 .

The first TSV through hole 12, the second TSV through hole 22 and the third TSV through hole 32 are preferably vertical solid holes filled with copper, with a diameter of 5 micrometers to 50 micrometers. The first silicon substrate 11, the second silicon substrate 21 and the The thickness of the third silicon substrate 31 is 70 microns to 300 microns, and the thicknesses of the first silicon substrate 11, the second silicon substrate 21 and the third silicon substrate 31 may be the same or different;

Various pad metal material structures on the upper/lower surfaces of the first substrate 10 , the second substrate 20 and the third substrate 30 are composed of copper, nickel and gold.

The plastic sealing compound 70 adopts a plastic sealing material whose thermal expansion coefficient is less than 10ppm/°C; the molding process of the plastic sealing compound 70 preferably adopts a wafer-level plastic sealing process. The second substrate 20 and the third substrate 30 exist as separate substrates assembled on the upper surface of the first substrate 10 .

The backsides of one or more chips flip-chip bonded to the upper surface of the third substrate 30 are exposed, and the backsides of the chips, as well as between the backsides of the chips and the surface of the surrounding plastic compound 70 are flush, which is convenient for the cooling device. imposed. The passive device 46 is wrapped by the plastic compound 70 , and the highest part of the passive device 46 after the surface mount is lower than the surface of the plastic compound 70 . The lateral thickness of the plastic package wrapped on the sides of the first substrate 10 , the second substrate 20 and the third substrate 30 is less than 500 μm.

The underfill material includes a first filling material 61, a second filling material 62, a third filling material 63, a fourth filling material 64 and a fifth filling material 65; the first filling material 61 is used to fill the first chip 41 and the third substrate 30 on the upper surface of the gap; the second filling material 62 and the third filling material 63 are respectively used to fill the gap between the second chip 42, the third chip 43 and the upper surface of the second substrate 20; the fourth filling material 64 and the fifth filling material 65 are respectively used to fill the gaps between the fourth chip 44, the fifth chip 45 and the upper surface of the first substrate 10;

Also includes a sixth filling material 67 and a seventh filling material 68; the sixth filling material 67 is used to fill the gap between the second substrate 20 and the third substrate 30; the seventh filling material 68 is used to fill the first substrate 10 and the first A gap between the two substrates 20 .

The pins on the lower surfaces of the non-bottom second substrate 20 and the third substrate 30 do not use a conventional pad structure, but a pad boss structure with a certain height-diameter ratio, so as to improve the interconnection density between the substrates, at the same time, Adapt to wider gaps between substrates. The first pad bosses 28 on the lower surface of the second substrate 20 and the second pad bosses 38 on the lower surface of the third substrate 30 are preferably made of copper, the surfaces can be protected by a nickel-gold layer, and the copper material has good conductivity and ductility. , reducing the electrical connection resistance between adjacent substrate layers, while improving the mechanical reliability. The preparation method of the first pad boss 28 and the second pad boss 38 is preferably by electroplating the copper boss first, and then electroplating the nickel-gold layer. At this time, the first solder ball 56 and the second solder ball 57 are prepared by ball mounting. way; the first pad boss 28 and the second pad boss 38 and the first solder balls 56 and the second solder balls 57 can also be prepared by electroplating the copper bosses in sequence, and then electroplating the solder.

It also includes a protective film layer 71, the protective film layer 71 covers the lower surface of the first substrate 10, wraps the root of the third solder ball 50 close to the external pad 18, and the top spherical cap portion of the third solder ball 50 is exposed outside the protective film layer 71. .

It includes a metal welding post 72 and a welding cap 73 , the metal welding post 72 is welded on the external pad 18 , and the welding cap 73 is located at one end of the metal welding post 72 .

A method for manufacturing a multi-chip three-dimensional integrated structure, comprising:

Substrate wafers corresponding to the first substrate 10 , the second substrate 20 and the third substrate 30 are prepared, and each of the first substrate 10 , the second substrate 20 and the third substrate 30 on the substrate wafer is subjected to an appearance test and double-sided electrical tests. On-off test, the substrate that passes the test enters the next single-layer component micro-assembly process;

The fourth chip 44 and the fifth chip 45 are respectively bonded to the first surface of the first substrate 10 through the fourth flip-chip bumps 54 on the fourth chip 44 and the fifth flip-chip bumps 55 on the fifth chip 45 . On the three-chip bonding pad 17, the fourth filling material 64 and the fifth filling material 65 are applied to fill the gap between the fourth chip 44, the fifth chip 45 and the upper surface of the first substrate 10;

The second chip 42 and the third chip 43 are respectively bonded to the first surface of the upper surface of the second substrate 20 through the second flip-chip bumps 52 on the second chip 42 and the third flip-chip bumps 53 on the third chip 43 . On the two chip bonding pads 27; and apply the second filling material 62 and the third filling material 63 to fill the gap between the second chip 42, the third chip 43 and the upper surface of the second substrate 20;

The first chip 41 is bonded to the first chip bonding pads 37 on the upper surface of the third substrate 30 through the first flip-chip bumps 51 on the first chip 41 , and the first filling material 61 is applied for filling the first chip 41 . A gap between the chip 41 and the upper surface of the third substrate 30;

The passive device 46 is attached to the upper surface of the first substrate 30 through the passive device surface mount pad 39, and is located around the first chip 41; the highest part of the passive element 46 after surface attachment is lower than the inverted The backside of the first chip 41 after bonding; the appearance test and electrical test are performed on the single-layer functional components of the first substrate 10, the second substrate 20 and the third substrate 30, and the first substrate 10, the second substrate 20 and the The three-substrate 30 single-layer assembly enters the ball-mounting process;

implanting first solder balls 56 on the first interlayer pads 19 on the upper surface of the first substrate 10; implanting second solder balls 57 on the second interlayer pads 29 on the upper surface of the second substrate 20;

Through the bonding of the first solder balls 56 with the first pad bosses 28 on the lower surface of the second substrate 20 and the bonding of the second solder balls 57 with the second pad bosses 38 on the lower surface of the third substrate 30 , The stacking of single-layer components of the first substrate 10 , the second substrate 20 and the third substrate 30 , and the sixth filling material 67 and the seventh filling material 68 are applied to the surface of the outer pad 18 except the lower surface of the first substrate 10 . The other sides and top surfaces are encapsulated with plastic compound 70 to form an encapsulation body;

The top surface of the plastic sealing compound 70 is thinned to expose the substrate of the first chip 41; the external third solder balls 50 are implanted on the external pads 18 on the lower surface of the first substrate 10; after cutting and separation, a multi-chip three-dimensional integrated structure assembly is formed 100.

Referring to FIG. 2 , the encapsulation process of the bare component 80 may be wafer-level encapsulation. In this case, the TSV silicon interposer wafer 101 where the first substrate 10 is located includes a plurality of first substrates arranged periodically in two dimensions. 10. The fourth chip 44 and the fifth chip 45 are flip-chip bonded on the first substrate 10 that has passed the test in a die-to-wafer manner, and the fourth chip 44 and the fifth chip 45 are In the bonding and interconnection test, the single-layer functional components carried by the second substrate 20 and the third substrate 30 are stacked on the first substrate 10 units of the fourth chip 44 and the fifth chip 45 that have passed the test to form a bare assembly 80; A dummy chip is mounted on the first substrate 10 that fails the test to form a dummy 81 of a bare component. The bare component 80 and the bare component dummy 81 are similar in shape and size. Filling the vacancies of the bare components 80 on the TSV silicon interposer wafer 101 with the bare component dummy 81 can make the duty cycle of the TSV silicon interposer wafer 101 during plastic packaging similar within the same batch and between different batches , and then the required amount of plastic sealing material is similar, which facilitates the stability of the plastic sealing material feeding during wafer-level plastic sealing, thereby improving the stability of the plastic sealing process.

Referring to FIG. 3 , the present invention discloses a multi-chip three-dimensional integrated structure; a solder ball array is distributed on the lower surface of the first substrate 10 as the external lead pins of the entire first multi-chip three-dimensional integrated structure assembly 200 . The lower surface of 10 is protected, and at the same time, when the first multi-chip three-dimensional integrated structure assembly 200 is assembled and welded on the PCB board, the thermal stress near the interface between the root of the third solder ball 50 and the external pad 18 is under the first substrate 10. A protective film layer 71 is provided on the second multi-layer metal rewiring layer 15 on the surface. The protective film layer 71 covers the lower surface of the first connection substrate 10 and wraps a part of the root of the third solder ball 50 close to the external pad 18. The top spherical cap portion of the three solder balls 50 is exposed outside the protective film layer 71 ; the protective film layer 71 is made of organic material and is prepared by a method of thermal curing after vacuum lamination.

Referring to FIG. 4 , the present invention discloses a multi-chip three-dimensional integrated structure; metal solder posts 72 are distributed on the lower surface of the first substrate 10 as the external lead-out pins of the entire second multi-chip three-dimensional integrated structure assembly 300 . The metal welding post 72 is preferably in the shape of a cylinder or a truncated truncated cone (the apex of the cone is cut off), which is mainly used to relieve and release the thermal stress caused by the CTE mismatch between the first substrate 10 and the welding plate when the multi-chip three-dimensional integrated structure assembly is applied. Improve the mechanical reliability of the application of multi-chip three-dimensional integrated structure components.

The material of the metal solder post 72 may be copper, lead-tin, etc., but is not limited thereto. The top of the metal welding post 72 can be provided with a welding cap 73 , the melting point of the welding cap 73 is lower than the melting point of the material of the metal welding post 72 , and is mainly used for welding assembly when the second multi-chip three-dimensional integrated structure assembly 300 is applied. The material of the solder cap 73 is solder. The surface of the metal welding post 72 can be covered with a surface protection layer, and the material of the surface protection layer can be an anti-corrosion metal material such as nickel and gold, or an organic protective material. The main function is to improve the anti-corrosion, anti-oxidation, waterproof, Anti-pollution ability. The preparation method of the metal welding post 72 may be, but is not limited to, post implantation, electroplating, 3D printing, and the like.

Referring to FIG. 5, the present invention discloses a multi-chip three-dimensional integrated structure; in the third multi-chip three-dimensional integrated structure component 400, the bottom substrate may be a chip packaging organic carrier board 40, and the main material of the chip packaging organic carrier board 40 is organic Materials, such as epoxy resin, BT material, ABF material, MIF material, etc. Compared with the main material of the first substrate 10 - silicon; the chip packaging organic carrier board 40 is inferior in metal wiring line accuracy, substrate flatness and substrate heat dissipation capability, but the chip packaging organic carrier board 40 has good flexibility, The thermal expansion coefficient may be between the silicon and the printed circuit board (PCB), which plays the role of buffering thermal stress, which is more obvious when the size of the second substrate 20 is larger.

The fourth chip 44 and the fifth chip 45 assembled on the chip package carrier board 40 are located directly under the second substrate 20 and are connected to the first solder balls between the chip package carrier board 40 and the second substrate 20 56.

When the underlying substrate is the chip package organic carrier board 40, the encapsulation process of the bare components 80 may be organic carrier board strip packaging, and the eighth filling material 69 is filled on the chip package organic carrier board 40 and the second substrate. between 20. At this time, as shown in FIG. 6 , the chip packaging organic carrier strip 401 where the chip packaging organic carrier board 40 is located includes a plurality of two-dimensionally periodically arranged chip packaging organic carrier boards 40 , and the fourth chip 44 and the fifth chip 45 are flip-chip bonded on the tested chip package organic carrier board 40 in a die-to-board manner, and the fourth chip 44 and the fifth chip 45 are bonded to each other. In the continuous test, the single-layer functional components carried by the second substrate 20 and the third substrate 30 are stacked on the chip packaging organic carrier strip 401 unit of the fourth chip 44 and the fifth chip 45 that have passed the test to form the bare component 80 ; A dummy piece is attached to the chip package organic carrier board 40 unit that has not passed the test to form a dummy piece 81 of a bare component. The bare component 80 and the bare component dummy 81 are similar in shape and size. The bare component dummy 81 is used to fill the vacancy of the bare component 80 on the chip packaging organic carrier strip 401, which can make the chip packaging in the same batch and between different batches when plastic sealing on the carrier strip 401. The duty cycle is similar, and the required amount of the plastic sealing compound is similar, which is convenient for the stability of the plastic sealing material feeding when the carrier strip is plastic-sealed, thereby improving the stability of the plastic sealing process.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A multi-chip three-dimensional integrated structure, characterized in that, comprising: a multi-chip three-dimensional integrated structure assembly (100); The multi-chip three-dimensional integrated structure assembly (100) includes a chip, a passive device (46), a plastic sealing compound (70) and several substrates; The plurality of substrates are stacked layer by layer, including a top substrate, a middle substrate and a bottom substrate; The top substrate and the middle substrate, the middle substrate and the bottom substrate are all connected by interlayer bump solder balls; the top substrate, the middle substrate and the bottom substrate are all bonded with chips; the passive device (46 ) is fixed on the top substrate; the plastic sealing compound (70) encapsulates the remaining surfaces except the lower surface of the bottom substrate. 2. The multi-chip three-dimensional integrated structure according to claim 1, wherein the top substrate, the middle substrate and the bottom substrate are respectively a first substrate (10), a second substrate (20) and a third substrate (30) ); The first substrate (10) comprises external pads (18) located on the lower surface of the first substrate (10) and first interlayer pads (19) located on the upper surface of the first substrate (10); the second The substrate (20) comprises a first pad boss (28) on the lower surface of the second substrate (20) and a second interlayer pad (29) on the upper surface of the second substrate (20); the third substrate (30) comprising a second pad boss (38) located on the lower surface of the third substrate (30) and a passive device surface mount pad (39) located on the upper surface of the third substrate (30); The chip includes a first chip (41), a second chip (42), a third chip (43), a fourth chip (44) and a fifth chip (45); the interlayer bump solder ball includes a first chip (43) solder balls (56) and second solder balls (57); The first chip (41) is bonded on the upper surface of the third substrate (30); the second chip (42) and the third chip (43) are bonded on the upper surface of the second substrate (20); the fourth chip (44) and the fifth chip (45) are bonded on the upper surface of the first substrate (10); The passive device (46) is attached to the upper surface of the third substrate (30) through the passive device surface mount pad (39), and is located around the first chip (41); the first substrate ( 10) The second substrate (20) is connected by the first solder balls (56); the second substrate (20) and the third substrate (30) are connected by the second solder balls (57); The first solder balls (56) are welded between the first interlayer pads (19) and the first pad bosses (28), and the second solder balls (57) are welded to the second interlayer pads between (29) and the second pad boss (38); It also includes third solder balls (50); the third solder balls (50) are located on the external pads (18); the plastic sealing compound (70) encapsulates the remaining surfaces except the lower surface of the first substrate (10). 3. The multi-chip three-dimensional integrated structure according to claim 2, wherein the first substrate (10), the second substrate (20) and the third substrate (30) are all TSV silicon transition substrates. 4. The multi-chip three-dimensional integrated structure according to claim 3, wherein the first chip (41), the second chip (42), the third chip (43), the fourth chip (44) and the Five chips (45) are respectively bonded on the third substrate (30), the second substrate (20) and the first substrate (10) by flip-chip bonding; The first chip (41) is bonded to the first chip bonding pad (37) on the upper surface of the third substrate (30) through the first flip-chip bumps (51) on the first chip (41); The second chip (42) and the third chip (43) pass through the second flip-chip bumps (52) on the second chip (42) and the third flip-chip bumps (52) on the third chip (43), respectively. 53) bonding on the second die bonding pad (27) on the upper surface of the second substrate (20); The fourth chip (44) and the fifth chip (45) pass through the fourth flip-chip bumps (54) on the fourth chip (44) and the fifth flip-chip bumps (54) on the fifth chip (45), respectively. 55) Bonding on the third die bonding pad (17) on the upper surface of the first substrate (10). 5. The multi-chip three-dimensional integrated structure according to claim 4, characterized in that, the first substrate (10) further comprises a first silicon substrate (11), a first TSV through hole (12), a first multiple a metal redistribution layer (13), a first metal interlayer dielectric layer (14), a second multi-layer metal redistribution layer (15) and a second metal interlayer dielectric layer (16); The first multi-layer metal redistribution layer (13) and the first inter-metal dielectric layer (14) are located on the upper surface of the first substrate (10); the second multi-layer metal redistribution layer (15) and the first The two-metal interlayer dielectric layer (16) is located on the lower surface of the first substrate (10); the first TSV through hole (12) passes through the first silicon substrate (11), and the first silicon substrate (11) ) is located in the middle of the first substrate (10); The second substrate (20) further comprises a second silicon substrate (21), a second TSV through hole (22), a third multi-layer metal redistribution layer (23), and a third metal interlayer dielectric layer (24) , a fourth multi-layer metal redistribution layer (25) and a fourth metal interlayer dielectric layer (26); The third multi-layer metal redistribution layer (23) and the third metal interlayer dielectric layer (24) are located on the upper surface of the second substrate (20); the fourth multi-layer metal redistribution layer (25) and the third multi-layer metal redistribution layer (25) The four-metal interlayer dielectric layer (26) is located on the lower surface of the second substrate (20); the second TSV through hole (22) passes through the second silicon substrate (21), and the second silicon substrate (21) ) is located in the middle of the second substrate (20); The third substrate (30) further comprises a third silicon substrate (31), a third TSV through hole (32), a fifth multi-layer metal redistribution layer (33), and a fifth metal interlayer dielectric layer (34) , a sixth multi-layer metal redistribution layer (35) and a sixth metal interlayer dielectric layer (36); The fifth multi-layer metal redistribution layer (33) and the fifth metal interlayer dielectric layer (34) are located on the upper surface of the third substrate (30); the sixth multi-layer metal redistribution layer (35) and the first The six-metal interlayer dielectric layer (36) is located on the lower surface of the third substrate (30); the third TSV through hole (32) passes through the third silicon substrate (31), and the third silicon substrate (31) ) is located in the middle of the third substrate (30). 6 . The multi-chip three-dimensional integrated structure according to claim 5 , wherein the plastic sealing material ( 70 ) adopts a plastic sealing material with a thermal expansion coefficient of less than 10 ppm/° C.; the passive device ( 46 ) adopts a chip type A source element or a chip-type passive element; the thickness of the second chip (42), the third chip (43), the fourth chip (44) and the fifth chip (45) is less than 200 microns. 7 . The multi-chip three-dimensional integrated structure according to claim 6 , further comprising an underfill material, the underfill material comprising a first filling material ( 61 ), a second filling material ( 62 ), a third filling material a material (63), a fourth filling material (64) and a fifth filling material (65); the first filling material (61) is used to fill the gap between the first chip (41) and the upper surface of the third substrate (30) the second filling material (62) and the third filling material (63) are respectively used to fill the gaps between the second chip (42), the third chip (43) and the upper surface of the second substrate (20); the first The four filling materials (64) and the fifth filling material (65) are respectively used to fill the gaps between the fourth chip (44), the fifth chip (45) and the upper surface of the first substrate (10); Also includes a sixth filling material (67) and a seventh filling material (68); the sixth filling material (67) is used for filling between the second substrate (20) and the third substrate (30); the seventh A filling material (68) is used to fill between the first substrate (10) and the second substrate (20). 8 . The multi-chip three-dimensional integrated structure according to claim 2 , further comprising a protective film layer ( 71 ), the protective film layer ( 71 ) covering the lower surface of the first substrate ( 10 ) and wrapping the third The root of the solder ball (50) is close to the part of the external pad (18), and the top of the third solder ball (50) is exposed outside the protective film layer (71). 9. The multi-chip three-dimensional integrated structure according to claim 2, characterized in that it further comprises a metal welding post (72) and a welding cap (73), the metal welding post (72) being welded to the external pad (18) Above, the welding cap (73) is located at one end of the metal welding post (72). 10. A method for manufacturing a multi-chip three-dimensional integrated structure, comprising: Substrate wafers corresponding to the first substrate (10), the second substrate (20) and the third substrate (30) are prepared, and for each of the first substrate (10), the second substrate (20) and the third substrate (30) on the substrate wafer The three substrates (30) are subjected to an appearance test and a double-sided electrical on-off test, and the substrates that have passed the test enter the next single-layer component micro-assembly process; passing the fourth chip (44) and the fifth chip (45) through the fourth flip-chip bumps (54) on the fourth chip (44) and the fifth flip-chip bumps (55) on the fifth chip (45), respectively ) is bonded on the third die bonding pad (17) on the upper surface of the first substrate (10), and a fourth filling material (64) and a fifth filling material (65) are applied to fill the fourth chip (44), the gap between the fifth chip (45) and the upper surface of the first substrate (10); passing the second chip (42) and the third chip (43) through the second flip-chip bumps (52) on the second chip (42) and the third flip-chip bumps (53) on the third chip (43), respectively ) is bonded on the second chip bonding pad (27) on the upper surface of the second substrate (20); and the second filling material (62) and the third filling material (63) are applied to fill the second chip (42), The gap between the third chip (43) and the upper surface of the second substrate (20); bonding the first chip (41) on the first chip bonding pad (37) on the upper surface of the third substrate (30) through the first flip chip (51) on the first chip (41), and applying a first filling material (61) for filling the gap between the first chip (41) and the upper surface of the third substrate (30); The passive device (46) is surface-mounted on the upper surface of the first substrate (30) through the passive device surface-mounting pad (39), and is located around the first chip (41); the surface-mounted passive component The highest point of (46) is lower than the backside of the first chip (41) after undercut bonding; the appearance test is performed on the single-layer functional components of the first substrate (10), the second substrate (20) and the third substrate (30). and electrical test, the single-layer components of the first substrate (10), the second substrate (20) and the third substrate (30) that have passed the test enter the ball-mounting process; Implant first solder balls (56) on the first interlayer pads (19) on the upper surface of the first substrate (10); on the second interlayer pads (29) on the upper surface of the second substrate (20) implanting the second solder ball (57); Through the bonding of the first solder balls (56) with the first pad bosses (28) on the lower surface of the second substrate (20) and the second solder balls (57) with the second solder balls (57) on the lower surface of the third substrate (30) Bonding of pad bosses (38), enabling stacking of single-layer assemblies of first substrate (10), second substrate (20) and third substrate (30), and applying sixth filling material (67) and seventh Filling material (68), for encapsulating other side surfaces and top surfaces of the lower surface of the first substrate (10) except the surface where the outer pads (18) are located with a plastic sealing compound (70) to form an encapsulation body; Thinning the top surface of the molding compound (70) to expose the substrate of the first chip (41); implanting external third solder balls (50) on the external pads (18) on the lower surface of the first substrate (10); After cutting and separation, a multi-chip three-dimensional integrated structure assembly (100) is formed.

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