CN119396834A

CN119396834A - Storage index method, storage index device, electronic equipment and storage medium

Info

Publication number: CN119396834A
Application number: CN202411500756.2A
Authority: CN
Inventors: 贾琳黎
Original assignee: Hygon Information Technology Co Ltd
Current assignee: Hygon Information Technology Co Ltd
Priority date: 2024-10-24
Filing date: 2024-10-24
Publication date: 2025-02-07

Abstract

A storage index method, storage index device, electronic device and storage medium. The storage index method comprises: receiving an access request to a storage device, the access request includes an access address, and the storage device includes multiple storage spaces; determining a target storage space corresponding to the access address in multiple storage spaces according to a space index field belonging to a tag part in the access address; and performing storage access in the target storage space according to the access address. The storage index method can improve the flexibility and adaptability of storage access, and is easy to implement without increasing hardware complexity and chip area and power consumption.

Description

Storage index method, storage index device, electronic equipment and storage medium

Technical Field

The present disclosure relates to a storage indexing method, a storage indexing device, an electronic apparatus, and a storage medium.

Background

With the advent of big data and artificial intelligence, the demand for high-performance and high-computation-power chips is also increasing, and the performance of storage is also becoming a critical one. As the number of processor cores increases, the large capacity and low latency of storage has a significant impact on improving performance in multi-core shared hardware designs.

Disclosure of Invention

At least one embodiment of the present disclosure provides a storage indexing method, including receiving an access request to a storage device, where the access request includes an access address, and the storage device includes a plurality of storage spaces, determining, according to a spatial index field belonging to a tag portion in the access address, a target storage space corresponding to the access address in the plurality of storage spaces, and performing storage access in the target storage space according to the access address.

For example, in a storage indexing method provided by at least one embodiment of the present disclosure, a total storage capacity of a storage device is not equal to an integer power of 2, and/or a storage capacity of each of a plurality of storage spaces is an integer power of 2.

For example, in a storage index method provided in at least one embodiment of the present disclosure, determining a target storage space corresponding to an access address in a plurality of storage spaces according to a spatial index field belonging to a tag portion in the access address includes determining a storage space access index according to an address bit in the spatial index field belonging to the tag portion in the access address, and determining the target storage space according to the storage space access index.

For example, in a storage index method provided in at least one embodiment of the present disclosure, determining a storage space access index according to address bits in a space index field belonging to a tag portion in an access address includes performing an operation on a value of an address bit in the space index field, and determining the storage space access index according to an operation result of the operation.

For example, in the storage indexing method provided in at least one embodiment of the present disclosure, the storage index method further includes that the plurality of storage spaces correspond to a plurality of theoretical result values determined according to the operation result, and a first ratio of a number of corresponding theoretical result values of each storage space to a total number of the plurality of theoretical result values matches a second ratio of a storage capacity of each storage space to a total storage capacity of the plurality of storage spaces.

For example, in a storage indexing method provided by at least one embodiment of the present disclosure, the operation includes a modulo operation or a hash operation.

For example, in a storage index method provided by at least one embodiment of the present disclosure, a modulo operation includes obtaining an operation result modulo-calculated a value of an address bit in a space index field using a modulus determined by proportional operation based on a plurality of storage spaces.

For example, in a storage indexing method provided in at least one embodiment of the present disclosure, a plurality of storage spaces are divided into a plurality of storage space groups, each storage space group of the plurality of storage space groups including at least one storage space, the storage indexing method further includes determining a corresponding target storage space group of an access address in a storage device according to a group index field of a spatial index field.

For example, in the storage index method provided in at least one embodiment of the present disclosure, determining, according to the spatial index field, a target storage space corresponding to the access address in the target storage space group is further included.

For example, in a storage indexing method provided by at least one embodiment of the present disclosure, each storage space of a plurality of storage spaces is mapped in a direct-associative or group-associative manner.

For example, in a storage indexing method provided in at least one embodiment of the present disclosure, an access address includes a tag portion and an index portion, and performing storage access in a target storage space according to the access address includes addressing a target storage location in the target storage space according to the index portion, and comparing with tags stored in the target storage location according to the tag portion to confirm that target access data corresponding to an access request is stored in the target storage location.

At least one embodiment of the present disclosure further provides a storage index device, which is used for a storage device, and includes a receiving unit configured to receive an access request to the storage device, where the access request includes an access address, and the storage device includes a plurality of storage spaces, and an access unit configured to determine, according to a space index field belonging to a tag part in the access address, a target storage space corresponding to the access address in the storage device, and perform storage access in the target storage space according to the access address.

The access unit comprises a modulus unit and a space selection unit, wherein the modulus unit is configured to carry out modulus operation on the numerical value of the address bit in the space index field, the storage space access index is determined according to the operation result of the modulus operation, and the space selection unit is configured to determine the corresponding target storage space of the access address in the storage device according to the index identification bit in the storage space access index and the access address.

At least one embodiment of the present disclosure further provides a storage index device, where the space selection unit includes a first and a second and, the first and second and are disposed in corresponding branches of different storage spaces, and output logic relationships of the first and second and are opposite.

At least one embodiment of the present disclosure also provides an electronic device comprising at least one memory configured to store computer-executable instructions and at least one processor configured to execute the computer-executable instructions, the computer-executable instructions when executed by the at least one processor now implementing the method of storing indices as described in any of the embodiments above.

At least one embodiment of the present disclosure also provides a non-transitory storage medium that non-transitory stores computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the storage indexing method of any of the embodiments above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 illustrates a use scenario diagram of a storage indexing method provided by at least one embodiment of the present disclosure;

FIG. 2 illustrates a flow diagram of a method of storing an index provided by at least one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of the mapping relationship of direct associativity, full associativity and set associativity in a cache;

FIG. 4 illustrates a schematic diagram of a cached group associative organization and addressing scheme provided by at least one embodiment of the present disclosure;

FIG. 5 illustrates a block diagram of a memory provided in accordance with at least one embodiment of the present disclosure;

FIG. 6 illustrates a block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure;

FIG. 7 illustrates an exemplary schematic diagram of the operational logic of a storage indexing device provided by at least one embodiment of the present disclosure;

FIG. 8 is a flow diagram of a storage indexing process for a Last Level Cache (LLC) provided by at least one embodiment of the present disclosure;

FIG. 9 shows a schematic diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure, and

Fig. 10 illustrates a schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The present disclosure is illustrated by the following several specific examples. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed description of known functions and known components. When any element of an embodiment of the present disclosure appears in more than one drawing, the element is identified by the same or similar reference numeral in each drawing.

The terms used in the present disclosure are those general terms that are currently widely used in the art in view of functions regarding technical features in the embodiments of the present disclosure, but these terms may be changed according to the intention, precedent, or new technology in the art of the person of ordinary skill in the art. Furthermore, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Accordingly, the terms used in the specification should not be construed as simple names, but rather based on the meanings of the terms and the general description of the present disclosure.

A flowchart is used in this disclosure to describe the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously, as desired. Also, other operations may be added to or removed from these processes.

As the demand for high performance and high power chips increases, the performance of memory becomes a critical aspect. For example, a Cache (Cache) is first performed before the main memory is accessed, so that the problem of higher delay in accessing the main memory is solved by using a Cache with higher storage speed. Particularly, as the number of processing cores increases, a larger-capacity cache is set in such a multi-core design, so that the access performance of the main memory is significantly improved.

Therefore, under a limited chip size, it is important to make the cache have a larger capacity as much as possible, but increasing the cache capacity within the chip to the maximum extent often results in the cache capacity not being equal to an integer power of 2.

For the above situation, an indexing method for the integer power of the cache capacity not equal to 2 is proposed, and the method can be implemented by adopting a hash algorithm or increasing the number of ways (Way) in the cache.

The complexity of the hash algorithm is high and hash collisions also exist in some cases. In such a design, therefore, not only is it necessary to set up a hash mapping for the hash algorithm itself, but also an additional set of hardware is required according to the hash collisions that may exist. This not only increases the latency of the access, but also introduces further hardware overhead due to the irreversibility of the hash algorithm that needs to be indexed by storing full address information.

For the way of increasing the number of ways in the cache, the cache index is slow due to the increase of the number of ways, and the access delay and the area and the power consumption of the chip are increased.

For this reason, in a design that realizes as large a storage capacity (e.g., a cache capacity) as possible under a limited chip size, problems of complexity of hardware design, increase in access delay, and increase in chip area and power consumption are caused due to irregularities in the storage capacity (i.e., the storage capacity is not equal to an integer power of 2).

In view of the above, the disclosure provides a storage indexing method, which includes receiving an access request to a storage device, where the access request includes an access address, and the storage device includes a plurality of storage spaces, determining a target storage space corresponding to the access address in the plurality of storage spaces according to a spatial index field belonging to a tag portion in the access address, and performing storage access in the target storage space according to the access address.

In the storage indexing method of the above embodiment of the present disclosure, by determining the target storage space corresponding to the access address in the plurality of storage spaces according to the spatial index field belonging to the tag portion in the access address, the storage indexing method can be flexibly adapted to perform index access no matter when accessing regular or irregular storage capacity, and the method is easy to implement without increasing hardware complexity and area and power consumption of a chip.

FIG. 1 illustrates a usage scenario diagram of a storage indexing method provided by at least one embodiment of the present disclosure.

As shown in fig. 1, the memory provided by the embodiments of the present disclosure is used as a cache for a computer system. As shown in FIG. 1, the requesting end 60 is communicatively coupled to a storage device 70, and the cache 70 is communicatively coupled to a main memory 202, including a storage index device or memory in accordance with at least one embodiment of the present disclosure. The request terminal 60 may be a storage device at a higher level of the storage device 70, for example, may be any device capable of directly accessing the storage device 70 using an access address and issuing an access request, such as a processor (or a processor core), various controllers (e.g., a Direct Memory Access (DMA) controller, etc.), or an input output Interface (IO), which is not limited in this disclosure.

The storage device 70 may be a higher level memory of the main memory 202 or may be a cache, for example, the storage device 70 may be a first level cache, a second level cache or a higher level cache (e.g., a Last Level Cache (LLC)) in the computer system, for improving the response speed and overall efficiency of access requests in the computer system. The Memory device 70 includes a Memory array formed of a Random-Access Memory (RAM), for example, a Random-Access Memory array including a Tag (Tag) array and a data array, for storing information such as a Tag and data information in an Access address of a stored object (for example, data or instructions), respectively. For convenience, the Tag array and the data array may also be abbreviated as Tag RAM array and SRAM array, respectively.

In some embodiments, storage device 70 includes a plurality of storage spaces, e.g., storage space 0~n (n is 1 or more). For example, each memory space may be provided as a block of independently accessible cache, e.g., each memory space contains a Tag RAM array and an SRAM array.

In some embodiments, the storage capacity of the storage device 70 may not be equal to an integer power of 2, and the storage capacity of the storage device 70 may be increased by adding SRAM arrays at design time.

Main memory 202 is also referred to as memory, and may be, for example, random access memory, such as Dynamic Random Access Memory (DRAM), and the like.

In operation, an access request issued by the requesting end 60 may be processed in response in the storage device 70, or a further access request may be issued by the storage device 70 to the main memory 202, and processed in response by the main memory 202. For example, the request terminal 60 issues an access request, and if the data requested by the access request is searched in the storage device 70, the storage device 70 processes the access request, and if the data requested by the access request is not searched in the storage device 70, the storage device 70 further sends the access request to the main memory 202, and the main memory 202 processes the access request.

Fig. 2 is a flow chart illustrating a method for storing index according to at least one embodiment of the present disclosure.

As shown in FIG. 2, in some embodiments of the present disclosure, the storage indexing method includes steps S30-S32.

For step S30, an access request to the storage device is received, the access request including an access address. Here, the storage device includes a plurality of storage spaces therein. For example, a storage index device receives an access request to a storage device.

In some embodiments of the present disclosure, the requesting end 60 issues an access request to the storage device, where the access request includes an access address (e.g., a physical address) that corresponds to a storage address in the storage device. The storage device comprises a plurality of storage spaces, the storage spaces can be divided into storage devices according to storage capacity, each storage space can be used as a buffer which can be independently accessed, for example, the sum of the storage capacity of the storage spaces is equal to the storage capacity of the storage devices.

For step S31, a target storage space corresponding to the access address in the plurality of storage spaces is determined according to the spatial index field belonging to the tag portion in the access address.

In a computer system, the access address to memory may include three parts, namely an offset, an index and a tag, from low to high. In an embodiment of the present disclosure, the tag portion of the access address further includes a spatial index field, which may include one or more address bits, and the spatial index field is used to index the storage space, so that the corresponding storage space is accessed through the spatial index field corresponding to each storage space. Each memory space has one or more values corresponding to a spatial index field, e.g., the plurality of memory spaces includes memory space 0 and memory space 1, the spatial index field includes 2 bits, and the corresponding spatial index values include 01, 00, 11, and 10, and 01, 00, and 11 may be taken as the spatial index values corresponding to memory space 0, and 10 may be taken as the spatial index values of memory space 1. It should be noted that, the spatial index value corresponding to each storage space is different, and each spatial index value can only index to the corresponding storage space. For example, if the spatial index value of the access address is 01, the target memory space to be indexed is memory space 0.

The spatial index field may be directly extracted from the tag portion of the access address, for example, the spatial index field belonging to the tag portion in the access address may be a part of the address fields in the access address. In an embodiment of the present disclosure, a portion of the address field of the tag portion in the access address is selected as the spatial index field. The spatial index field is extracted for computation to index the memory space.

For step S32, a memory access is performed in the target memory space according to the access address.

After the target storage space is determined, storage access is performed in the target storage space by using the access address. For example, the access address may be resolved, a target storage location in the target storage space determined from the resolved access address, and access data for the target storage location accessed.

In the above embodiments of the present disclosure, by determining the target storage space of the access address in the plurality of storage spaces of the storage device, and then accessing the target storage space according to the access address, such a multi-level index manner makes the flexibility of storage access to the storage device high, and such a storage access manner is easy to implement, and does not increase the complexity of hardware and the area and power consumption of the chip.

In some embodiments of the present disclosure, the total storage capacity of the storage device is not equal to an integer power of 2.

For example, where the storage device is a cache, multiple SRAM arrays may be included, e.g., each SRAM array having a capacity of an integer power of 2.

In some embodiments of the present disclosure, the storage capacity of each of the plurality of storage spaces is an integer power of 2.

For example, the total storage capacity in the storage device may be divided into a plurality of storage spaces in the storage device in accordance with a condition that an integer power of 2 is satisfied, so that the capacity of each of the plurality of storage spaces is an integer power of 2.

In some embodiments of the present disclosure, the total storage capacity of the storage device is not equal to an integer power of 2 and the storage capacity of each of the plurality of storage spaces is an integer power of 2.

In order to increase the capacity of the storage device as much as possible in a limited space, for example, the total capacity of the storage device obtained last is not equal to the integer power of 2 during the design or configuration of the storage device. If an access address were to be used to access a maximum capacity storage device, then the address bits of all tag portions of the access address would need to be calculated to route the request to the target storage bit, since the total capacity of the storage device is not equal to the integer power of 2, which would greatly increase the latency of the access and complexity of the system hardware.

The storage device having a maximum capacity whose total capacity is not equal to an integer power of 2 may be divided into a plurality of storage spaces, with the storage capacity of each storage space being an integer power of 2. For example, the capacity of the storage device is X (MB), where x+.2k and X and k are both positive integers, for example, the capacity of the storage device X (MB) may be divided into one storage space of 2n (MB) and one storage space of 2M (MB), where n and m are non-negative integers, and the relationship of the storage capacities satisfies X (MB) =2n (MB) +2m (MB).

Thus, the maximum capacity storage device can be accessed by accessing the target storage space in the storage device and then accessing the target storage bits in the target storage space. The above-described approach is suitable for access to all storage devices whose total capacity is not equal to the integer power of 2, and this approach greatly increases the flexibility of storage access, and does not require an increase in hardware complexity nor increase access latency.

In some embodiments of the present disclosure, step S31 of the above-described storage indexing method further includes step S310 and step S311.

For step S310, a memory space access index is determined from address bits in the space index field belonging to the tag portion in the access address.

For step S311, the target storage space is determined from the storage space access index.

For example, mapping or computing address bits in the space index field determines the memory space access index. For example, in at least one embodiment, a mapping relationship between the storage space and a spatial access index (spatial index value) is provided, such as a lookup table that records the mapping relationship, so that the target storage space can be determined by the storage space access index.

By determining the memory space access index from the address bits in the spatial index field belonging to the tag portion in the access address, it is possible to prevent access failure due to index conflict when access to the memory space is performed. I.e. one storage space access index will only point to one corresponding storage space and one storage index will not point to multiple storage spaces.

In some embodiments of the present disclosure, step S310 of the above-described indexing method further includes step S320.

For step S320, the numerical value of the address bit in the space index field is operated, and the storage space access index is determined according to the operation result of the operation.

For example, there is a proportional relationship between the storage capacities corresponding to the storage spaces, where the storage capacities of the storage spaces each satisfy an integer power of 2. For example, the plurality of memory spaces includes two memory spaces, for example, memory space 0 and memory space 1. The ratio of the capacities of the two storage spaces is storage space 0, storage space 1=2n (MB): 2m (MB), for example, when n=2 and m=3, the ratio is storage space 0, storage space 1=4 (MB): 8 (MB), and the ratio can be further simplified to the simplest ratio, for example, storage space 0, storage space 1=1:2, so that the number of spatial index values corresponding to storage space 0 is half of the number of spatial index values corresponding to storage space.

And calculating the numerical value of the address bit in the space index field according to the proportional relation of a plurality of storage capacities corresponding to the storage spaces. For example, according to the proportional relationship of the storage capacities being the storage space 0, the storage space 1=1:2, the total number of storage capacities in all the storage spaces is 3, and the corresponding relationship between each storage space and the spatial index value may be based on the proportional relationship between the storage capacities corresponding to the storage spaces. The spatial index field is modulo-calculated according to the total number of copies, for example, the spatial index field MOD 3. The memory space access index is determined from the possible operation results 00, 01 and 10.

For example, when the capacities of the plurality of storage spaces each satisfy the integer power of 2, the size of the index field and the number of spatial index values may be determined from the relationship between the plurality of exponents when the storage capacities of the plurality of storage spaces are expressed as the integer power of 2. For example, the plurality of memory spaces includes two memory spaces, for example, memory space 0=2n (MB) and memory space 1=2m (MB). For example, according to the formula, the value of the spatial index field is subjected to a modulo operation, that is, the spatial index value MOD (2 abs (m-n) +1), to obtain an operation result, for example, when n=2 and m=3, the spatial index value MOD (2 abs (3-2) +1) =the spatial index value MOD 3. The memory space access index is determined based on the possible operation results 00, 01, and 10.

For example, the possible operation results 00, 01 and 10 may be divided into all possible operation results according to the above-mentioned ratio of the storage capacities of the two storage spaces, namely, storage space 0: storage space 1=1:2. For example, a value of 00 is taken as an index of memory space 0, a value of 01 and a value of 10 are taken as an index of memory space 1, i.e., the operation result 00 corresponds to memory space 0, and the operation results 01 and 10 correspond to memory space 1.

It should be noted that the number of address bits in the spatial index field affects how many of the number of address bits in the spatial index field, and thus affects the index uniformity for a plurality of storage spaces. The number corresponding to the number of bits of the address bits in the spatial index field is an integer multiple of the modulus in the modulo operation, the better the index uniformity for the multiple memory spaces. For example, if the number of bits of the address bits in the spatial index field is 2, the number of bits of the address in the spatial index field is 0 at a minimum and 3 at a maximum, and if the total number of storage capacity is 3, 3 operation results 01, 10 and 00 appear in the spatial index field MOD 3. For example, if 00 is used as the index of the storage space 0 and 01 and 10 are used as the index of the storage space 1 according to the ratio of the storage capacities of the plurality of storage spaces, the ratio of the indexable storage space 0 to the indexable storage space 1 is 1:2, and the ratio of the indexable storage space 0 to the storage capacities of the plurality of storage spaces is equal, and the ratio of the indexable storage space 0 to the storage space 1=1:2. This results in better index uniformity across multiple storage spaces.

For example, when the number corresponding to the number of bits of the address bits in the spatial index field cannot be satisfied is an integer multiple of the modulus in the modulo operation, the index uniformity for a plurality of storage spaces can be improved by increasing the number of bits of the address bits in the spatial index field.

It should be noted that, although the above example of the plurality of storage space indexes is exemplified by two storage spaces, this is not limited to the number of the plurality of storage spaces, and the number of the plurality of storage spaces may be 3 or more. For example, the ratio of the storage capacities of the three storage spaces is that the total number of storage capacities of the storage space 0, the storage space 1, the storage space 2=2n (MB), the storage space 2M (MB), the storage space 2p (MB) =24 (MB): 22 (MB): 21 (MB) =8:2:1 is 11, for example, the spatial index field may include 4 address bits, and the storage space access index may be determined from the operation result of the corresponding spatial index value MOD 11. The storage space access index may also be determined from the result of the operation of the spatial index value MOD (2 abs (m-n) +2abs (n-p) +1) calculated by the formula.

Although the above description has been made with respect to the storage capacity of the plurality of storage spaces in terms of Megabytes (MB) as an example, the storage capacity of the plurality of storage spaces and the storage device is not limited to the storage capacity unit. In the present disclosure, it is described whether the storage device and the storage space are the integer powers of 2, based on the same storage capacity unit. The storage capacity units of the storage devices and the storage spaces may be kilobytes (Kilobyte, KB), megabytes (MB), gigabytes (Gigabyte, GB), terabytes (TB), beat bytes (Petabyte, PB), and mugwort bytes (Exabyte, EB), etc., which are not limited herein.

In some embodiments of the present disclosure, in the storage indexing method, the plurality of storage spaces correspond to a plurality of theoretical result values (result value spaces) determined according to operation results, and a first ratio of a number of corresponding theoretical result values to a total number of the plurality of theoretical result values for each storage space matches a second ratio of a storage capacity of each storage space to a total storage capacity of the plurality of storage spaces.

The plurality of theoretical result values that the plurality of storage spaces have may be determined by the operation result according to a proportional relationship of the plurality of storage capacities. For example, the plurality of memory spaces includes two memory spaces, for example, memory space 0 and memory space 1. The ratio of the storage capacities of the two storage spaces is storage space 0, and storage space 1=1:2. For example, according to 3 MOD3 operation results, the plurality of storage spaces corresponds to the plurality of theoretical result values determined according to the operation results being 00, 01 and 10, wherein the storage space 0 corresponds to the theoretical result value being 00, the storage space 1 corresponds to the theoretical result value being 01 and 10, i.e., 00 is used as an index of the storage space 0, and 01 and 10 are used as indexes of the storage space 1. For example, if the number of theoretical result values corresponding to the storage space 0 is 1 and the number of theoretical result values corresponding to the storage space 1 is 2, the number of theoretical result values corresponding to the storage space 0/the total number of theoretical result values (first ratio) =the storage capacity of the storage space 0/the total storage capacity of the plurality of storage spaces (second ratio) =the number of theoretical result values corresponding to the storage space 1/the total number of theoretical result values (first ratio) =the storage capacity of the storage space 1/the total storage capacity of the plurality of storage spaces (second ratio).

As another example, memory space 0 and memory space 1. The ratio of the storage capacities of the two storage spaces is 0 storage space to 1 storage space=1:3 storage space. Then MOD4 operation may be adopted, the number of operation results is 4, the number of operation theoretical result values is 00, 01, 10 and 11, then the theoretical result value corresponding to the storage space 0 is 00, the theoretical result value corresponding to the storage space 1 is 01, 10 and 11, that is, 00 is used as the index of the storage space 0, and 01, 10 and 11 are used as the index of the storage space 1. In this example, it is actually also possible to index directly using the value of the spatial index field itself having 2 bits, for example, 11 as the index of the storage space 0 and 00, 01, 10 as the index of the storage space 1.

In some embodiments of the present disclosure, the number of bits of the address bits in the spatial index field corresponds to a value that is not equal to an integer multiple of the modulus in the modulo operation. For example, the ratio of the storage capacities of the two storage spaces is storage space 0:storage space 1=2:3. For example, the storage space access index is determined according to the possible result of modulo operation of the numerical value of the address bit in the space index field according to the above-described proportional relationship, for example, the operation results 001 and 000 are used as the storage space access index of the storage space 0, and the operation results 011, 100 and 010 are used as the storage space access index of the storage space 1.

For example, in the above embodiment, if the number of bits of the address bits in the spatial index field is 3, the number of bits of the address in the spatial index field is 0 at the minimum and 7 at the maximum, the plurality of storage spaces have a total of 8 theoretical result values of 001, 010, 011, 100, 000, 001, 010, and 111, the number of theoretical result values corresponding to the storage space 0 may be determined as 3, and the number of theoretical result values corresponding to the storage space 1 may be determined as 5, then the first ratio and the second ratio may be considered to be matched, although the number of theoretical result values corresponding to the storage space 0/the total number of theoretical result values (first ratio) noteqof storage capacity of the storage space 0/the total storage capacity of the plurality of storage spaces (second ratio), the number of theoretical result values corresponding to the storage space 1/the total storage capacity of the plurality of theoretical result values (first ratio) noteqof storage capacity of the storage space 1 (second ratio). Thus, the first ratio and the second ratio are both matched within a certain reasonable deviation range, and the magnitude of the specific reasonable deviation range is not limited herein.

In some embodiments of the present disclosure, the operation of obtaining the index value may include a modulo operation or a hash operation.

For example, a hash operation is performed on the numerical value of the address bit in the space index field, a hash index table is established according to the operation result of the hash operation, and a storage space access index is determined according to the hash index table.

In some embodiments of the present disclosure, modulo arithmetic includes obtaining an arithmetic result modulo-calculated a value of an address bit in a spatial index field using a modulus determined after a proportional operation based on a plurality of memory spaces.

For example, the modulus may be determined according to a proportional relationship of storage capacities corresponding to the plurality of storage spaces. For example, if the ratio of the plurality of storage capacities is 0 storage space and 1=1:2 storage space, the total 3 copies may be determined as a modulus. For example, the ratio of the storage capacities of the plurality of storage spaces is storage space 0 to storage space 1 to storage space 2=2n (MB): 2m (MB): 2p (MB) =24 (MB): 22 (MB): 21 (MB), and the modulus may be determined according to a predetermined formula, for example, modulus=2abs (m-n) +2abs (n-p) +1, or modulus=m+n+p.

In some embodiments of the present disclosure, the plurality of storage spaces are divided into a plurality of storage space groups, each storage space group of the plurality of storage space groups includes at least one storage space, and the storage indexing method further includes the following step S33.

For step S33, a target storage space group corresponding to the access address in the storage device is determined according to the group index field in the space index field.

For example, the number of storage spaces among the plurality of storage spaces is greater than two, and there is a case where the calculation amount is excessively large when the target storage space is determined. The plurality of memory spaces may thus be further divided into a plurality of memory space groups, wherein each memory space group comprises at least one memory space. For example, the plurality of storage spaces includes storage space 0, storage space 1, and storage space 2, and storage space 0 may be divided as storage space group 0, and storage space 1 and storage space 2 may be divided as storage space group 1.

The corresponding target storage space group of the access address in the storage device can be determined according to the group index field in the space index field. For example, if the group index field in the spatial index field is 01, the target storage space group is determined to be storage space group 1 according to the group index field.

In some embodiments of the present disclosure, the above-mentioned indexing method further includes step S34.

For step S34, a target storage space corresponding to the access address in the target storage space group is determined according to the spatial index field.

After the target storage space group is determined, a target storage space corresponding to the access address in the target storage space group can be determined according to the space index field. For example, the target storage space group is storage space group 1 (including storage space 1 and storage space 2), and the target storage space may be determined as storage space 2 according to the spatial index field 10. For example, if the storage space included in the target storage space group is one, the storage space in the target storage space group may be directly determined.

It should be noted that, although in the embodiment of the present disclosure, the storage space is indexed by nesting three storage spaces in two stages, the number of stages for nesting indexing is not limited, for example, four or more storage spaces may be used to index to the target storage space by nesting three or four stages.

In some embodiments of the present disclosure, each of the plurality of storage spaces is mapped in a direct-associative or group-associative manner.

FIG. 3 shows a schematic diagram of the mapping relationship of direct associativity, full associativity and set associativity in a cache.

The storage device may be a Cache (Cache) in which a plurality of storage spaces may be accessed in a cached manner. The basic unit of caching is a cache block or cache line (CACHE LINE). The cache holds only a subset of the main memory content. In order to cache data in main memory into a cache, some function must be applied to locate the access address into the cache, which is called address mapping. After the data in the main memory is mapped into the cache according to the mapping relation, the CPU will convert the access address in the program into the cache address when executing the program. The cache address mapping modes generally include direct mapping, full associativity and set associativity mapping.

Although the storage capacity of a cache is small compared to main memory, the speed is much faster compared to main memory, so the main function of a cache is to store data that a near-term processor may need to access frequently. Thus, the processor can directly read data in the cache without frequently accessing the main memory with slower speed, thereby improving the access speed of the processor to the main memory.

For example, data stored in the main memory is similarly divided, similar to the division of a cache into a plurality of cache blocks. The partitioned blocks of data in main memory are referred to as memory blocks (or memory rows). Typically, a memory block may be 32 bytes in size, and a cache block may be 32 bytes in size. In practical application, the sizes of the main memory block and the cache line may be set to other values, and only the same size of the main memory block and the cache block needs to be ensured.

As shown in fig. 3, both main memory and cache are divided into blocks of the same size. Assume that there are 32 entries in main memory and 8 entries are cached.

As shown in fig. 3 (a), in the direct-coupled mode, each main memory block can be placed in only one location of the cache. Assuming that block 12 of main memory is to be placed in the cache, since the cache has only 8 entries, it can only be placed on entry (12 mod 8 = 4) and not elsewhere, so it is known that blocks 4, 12, 20, 28 correspond to entry 4 of the cache and can only be replaced if there is a conflict. The hardware required for the direct-connect approach is simple but inefficient.

As shown in FIG. 3 (b), in fully associative mode, each main memory block may be placed in any location in the cache, such that main memory blocks No. 4, 12, 20, 28 may be placed in the cache at the same time. The hardware required for the fully associative approach is complex but efficient.

As shown in FIG. 3 (c), group association is a compromise between direct association and full association. Taking two-way set association as an example, the 0, 2, 4 and 6 th positions in the cache are one way (referred to as the 0 th way), and the 3, 5 and 7 th positions are the other way (referred to as the 1 st way), and each way is provided with 4 blocks. Since the remainder of division of 12 by 4 is 0 for the block 12 of the main memory, the block 12 may be placed in the 0 th position of the 0 th way of the cache (i.e., the 0 th position of the cache) or in the 0 th position of the 1 st way (i.e., the 1 st position of the cache).

In some embodiments of the present disclosure, the access address includes a tag portion and an index portion, and step S32 of the above-described storage index method further includes step S320.

For step S320, a target storage location in the target storage space is addressed according to the index portion, and a comparison is made with the tag stored in the target storage location according to the tag portion to confirm that the target access data corresponding to the access request is stored in the target storage location. For example, the tag portion of the access address is compared with the tag stored in the target storage location, and if the tag portion is the same, it is confirmed that the target access data corresponding to the access request is stored in the target storage location, and otherwise, it is confirmed that the target access data corresponding to the access request is not stored in the target storage location.

FIG. 4 illustrates a schematic diagram of a cached group associative organization and addressing scheme provided by at least one embodiment of the present disclosure.

As shown in fig. 4, the caches are organized in the form of a cache line array (Set). A column of cache lines forms a Way (Way), a plurality of cache lines at the same position in a plurality of columns of cache lines form a group, and the cache comprises a plurality of cache groups. The location (Set, way, byte) of the accessed data or accessed instruction in the cache is obtained by reading access addresses, each of which may include:

(a) An Index section (Index) for selecting a Set (Set) in the cache, all cache lines in the same Set being selected by the Index.

(B) A Tag portion (Tag) for selecting a particular Cache line in a Set (Set), comparing the Tag of the physical address with the Tag of each Cache line, and if there is a match, a Cache Hit (Cache Hit) to select the Cache line, otherwise a Cache miss (CACHE MISS).

(C) An Offset portion (Offset) for selecting a corresponding address in the cache line, which represents a first Byte (Byte) of the access address in the cache line from which the corresponding data or instruction is read.

For example, for a cache, the Tag portion corresponding to the stored data may be stored in a Tag RAM array.

For a target storage space, a target storage location in the target storage space is first addressed according to an index portion in an access address, where the target storage location may be located in a target cache set in a target cache.

For example, after determining the target cache set, the tag portion of the access address is compared with a plurality of tags stored in the target cache set to confirm that the target access data corresponding to the access request is stored in a certain cache line, and the cache line is the target cache line.

If it is confirmed that the target access data corresponding to the access request is stored in the target cache line, it is determined in the target cache line that the corresponding data or instruction is read from the target byte position according to the offset portion.

For example, as shown in fig. 4, for a 32-bit access address, the tag portion is the upper portion of the access address, one or more address bits adjacent to the lowest address bits of the tag portion are the index portion, and the offset is the lower portion of the access address.

At least one embodiment of the present disclosure also provides a storage index device. The storage index device is used for a storage device and comprises a receiving unit and an access unit. The storage device includes a plurality of storage spaces, such as caches for computer systems, which are independently accessed in a cached manner.

The receiving unit is configured to receive an access request to the storage device. The access unit is configured to determine a target memory space corresponding to the access address in the memory device according to a spatial index field belonging to the tag part in the access address, and to perform memory access in the target memory space according to the access address.

Fig. 5 illustrates a block diagram of a memory provided in accordance with at least one embodiment of the present disclosure.

As shown in fig. 5, the storage index device 80 is used for the storage device 70, and the storage index device 80 includes a receiving unit 801 and an access unit 802. The memory device 70 includes a plurality of memory spaces therein, each memory space including a memory array, such as an SRAM memory array.

The receiving unit 801 is configured to receive an access request to the storage 70, the access request including an access address.

An access unit 802 is configured to determine a target storage space corresponding to the access address in the storage device 70 according to the spatial index field belonging to the tag portion in the access address, and perform storage access in the target storage space according to the access address.

For example, in one example, the access unit 802 may include a modulo unit and a space selection unit.

The modulo unit is configured to perform modulo operation on the numerical value of the address bit in the spatial index field, and determine a storage space access index according to an operation result of the modulo operation.

And the space selection unit is configured to determine a target storage space corresponding to the access address in the storage device according to the index identification bit in the storage space access index and the access address.

For example, in one example, the spatial selection unit may include a first and gate and a second and gate.

The first AND gate and the second AND gate are arranged on corresponding branches of different storage spaces, and the output logic relations of the first AND gate and the second AND gate are opposite.

The description of the corresponding storage device, storage space and spatial index field is the same as above, please refer to the above, and therefore, the description is not repeated.

The technical effects of the storage indexing device of the above embodiment of the present disclosure are the same as those of the storage indexing method described above, and therefore will not be described in detail.

At least one embodiment of the present disclosure also provides an electronic device comprising at least one memory configured to store computer-executable instructions, and at least one processor configured to execute the computer-executable instructions, which when executed by the at least one processor, implement a storage indexing method as described in any of the embodiments above.

Fig. 6 illustrates a block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

As shown in fig. 6, the electronic device 600 includes at least one memory 610 and at least one processor 620.

The at least one memory 610 is configured to store computer-executable instructions.

At least one processor 620 configured to execute computer-executable instructions that when executed by the at least one processor 620 implement a storage indexing method as described in any of the embodiments above.

FIG. 7 illustrates an exemplary schematic diagram of the operating logic of a storage indexing device provided by at least one embodiment of the present disclosure. It should be noted that, although fig. 7 illustrates an example of dividing the storage device into two storage spaces for indexing, it is not meant to limit the storage space of the index to two storage spaces in this disclosure, and all logic designs made by those skilled in the art based on the logic concept of fig. 7 of this disclosure are within the scope of protection of this disclosure.

As shown in fig. 7, the access request may be for a data read operation or for a data write operation, such as for a Last Level Cache (LLC) that includes a plurality of memory spaces, each of which may operate using a cache access manner. In the operation logic, first, the space index field in the access address (physical address) PA [ M: N ] is utilized, the modulus unit 30 performs modulus operation on the numerical value of the address bit in the space index field, and the memory space access index is determined according to the operation result of modulus operation.

The storage capacities of the storage space 0 and the storage space 1 are each an integer power of 2, for example, the storage capacity of the storage space 0 is 2n (MB), and the storage capacity of the storage space 1 is 2M (MB). Both memory space 0 and memory space 1 include an SRAM array and a Tag RAM array.

As shown in fig. 7, an index identification signal may be generated according to a storage space access index, and the index identification signal may be used as an Enable signal (Enable) for selecting a different storage space. For example, memory space 0 is selected when the index identification signal is high, and memory space 1 is selected when the index identification signal is low. For example, the signal output by the modulus unit 30 is sent to the branch where the memory space 0 is located and the branch where the memory space 1 is located, where the inverter 3 is disposed on the branch where the memory space 1 is located. The inverter 3 may invert the signal to achieve a choice between memory space 0 and memory space 1.

The index identification bit in the memory space access index may be input to the space selection unit 400 along with the access address to determine the corresponding target memory space of the access address in the memory device. Wherein the space selection unit 400 may comprise a first and gate 40 and a second and gate 41, the first and gate 40 and the second and gate 41 being arranged in corresponding branches of different memory spaces. The output logic relationship set by the first and gate 40 and the second and gate 41 is opposite, i.e., when the first and gate 40 outputs a signal, the second and gate 41 does not output a signal. For example, the output driving selection of the first and second and gates 40 and 41 by the index identification bit enables the access address PA [ M: N ] to be transferred to the branch where the corresponding target memory space is located.

Although the space selecting unit 400 includes the first and gate 40 and the second and gate 41 as an example in this embodiment, the space selecting unit 400 is not limited to the and gate implementation, and may be implemented by selecting through a multiplexer, for example, and the disclosure is not limited thereto.

After the first and gate 40 and the second and gate 41, a decoding unit 31 for decoding the access address may be provided, and the decoding unit 31 may be configured to parse the access address, for example, to parse an index portion and a tag portion in the access address.

The storage space 0 and the storage space 1 are used as caches, corresponding target cache groups are selected in the SRAM array in the target storage space according to the index part, and target cache lines are searched in the target cache groups according to the tag part.

For example, a search may be performed from the target cache line to find access data for the access address.

In some embodiments of the present disclosure, the decode unit 31 may also parse an offset portion in the access address, and determine from the offset portion that the corresponding data or instruction in the target cache line is read from the target byte location.

FIG. 8 is a flow diagram of a storage indexing process for a Last Level Cache (LLC) provided in accordance with at least one embodiment of the present disclosure. For example, when the storage device 70 is a Last Level Cache (LLC), the last level cache includes a plurality of storage spaces, such as storage space 0 and storage space 1 (described with reference to fig. 7).

An access to the LLC by an access address in the access request is received, and the value of the spatial index field belonging to the tag portion in the access address is operated, for example, modulo operation is performed on the value of the spatial index field. For example, referring to fig. 7, a modulo operation is performed by the modulo unit 30.

Whether to map to a certain memory space of the LLC is determined according to the operation result, for example, an index identification signal may be generated according to the operation result, and whether to map to a certain memory space of the LLC may be determined according to the index identification signal. For example, referring to fig. 7, according to the operation result of the modulus unit 30, mutually different index identification signals are generated by the inverter 2. For example, with continued reference to fig. 7, the index identification signal is input to the first and gate 40 corresponding to the memory space 0, and the index identification signal is input to the second and gate 41 corresponding to the memory space 1 through the inverter 3. For example, memory space 0 is selected when the index identification signal is high, and memory space 1 is selected when the index identification signal is low.

It is determined whether the operation result of the modulo operation is mapped to the memory space 0 of the LLC. For example, referring to fig. 7, it is determined whether to map to the memory space 0 of the LLC according to the outputs of the first and gate 40 and the second and gate 41, if the first and gate 40 can output the access address, it is mapped to the memory space 0, otherwise, it is mapped to the memory space 1.

For example, if the determination result is yes, the target memory space accessed by the access address is memory space 0, and the tag portion and the index portion in the access address are determined by decoding by the decoding unit (for example, decoding unit 31 in fig. 7) corresponding to memory space 0.

For example, if the determination result is no, the target memory space accessed by the access address is memory space 1, and the tag portion and the index portion in the access address are determined by decoding by the decoding unit (for example, decoding unit 31 in fig. 7) corresponding to memory space 1.

Inside the target memory space, the target memory location may be found according to the index part in the access address, e.g. memory space 0 is accessed, and then the target cache Set (Set) is found in memory space 0 according to the index part. For example, if the memory space 1 is accessed, a target cache Set (Set) is found in the memory space 1 according to the index portion. It should be noted that, each storage space may include at least one cache set, and if there is only one cache set in the target storage space, the cache set may be determined to be the target cache set.

In the target cache group, the Tag RAM array corresponding to the storage space can be searched according to the Tag part in the access address, and whether the Tag RAM array is matched with the Tag part or not is judged. By determining the match with the tag portion, it is possible to determine whether the target cache line exists. For example, memory space 0 is accessed and then the Tag RAM array of memory space 0 is looked up to determine if it matches the Tag portion. For example, memory space 1 is accessed and the Tag RAM array of memory space 1 is looked up to determine if it matches the Tag portion.

If the tag portion matches successfully, then a Cache Hit is made. The access data of the corresponding memory space may be accessed according to the index portion of the access address. For example, the Tag portion in the access address matches the Tag stored in the Tag RAM array of the target memory space (memory space 0), a Cache line of a Cache Hit (Cache Hit) is determined, and the access data in the Cache line is accessed.

If the tag portion fails to match, a cache miss (CACHE MISS) indicates that the access data of the access address is not stored in the target storage space, and an access request needs to be sent to the main memory or other caches for further searching. For example, if the Tag portion of the access address does not match the Tag stored in the Tag RAM array of the target memory space (memory space 1), then an access request is sent to main memory or other cache for continued lookup.

At least one embodiment of the present disclosure further provides a memory, and referring to fig. 5, the memory 800 includes the storage index device 80 and the storage device 70 described in the above at least one embodiment. For example, memory 800 may be used as a cache in a computer system.

The description of the corresponding storage index device and the storage device is the same as the above, please refer to the above, and the description is omitted here.

The technical effects of the memory according to the above embodiments of the present disclosure are the same as those of the above method for storing indexes, and thus will not be described again.

At least one embodiment of the present disclosure further provides an electronic device, where the electronic device includes the storage index device or the memory described in the at least one embodiment.

Fig. 9 is a schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

The electronic device 1000 in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The illustrated electronic device 1000 is merely an example and should not be taken as limiting the functionality and scope of use of embodiments of the present disclosure.

For example, referring to fig. 9, in some examples, an electronic device 1000 includes at least one processing means (e.g., a central processing unit, a graphics processor, etc.) 1001 for which a cache is provided, which is a memory (including a storage index means and a storage means) according to any of the embodiments of the present disclosure, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1002 or a program loaded from a storage means 1008 into a Random Access Memory (RAM) 1003. For example, the ROM 1002 may serve as the main memory 202, and in the RAM 1003, various programs and data required for the operation of the computer system are also stored. The processing apparatus 1001, an input/output (I/O) interface 1005, a ROM 1002, and a RAM 1003 are connected thereto through an interconnection network 1004.

For example, the following components may be connected to I/O interface 1005, including input device 1006, e.g., a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc., input device 1006 may be used as a requesting terminal 60 in embodiments of the present disclosure, including output device 1007, e.g., a Liquid Crystal Display (LCD), speaker, vibrator, etc., storage device 1008, e.g., a magnetic tape, hard disk, etc., and communication device 1009, e.g., which may also include a network interface card, e.g., a LAN card, modem, etc. The communication means 1009 may allow the electronic device 1000 to perform wireless or wired communication with other devices to exchange data, performing communication processing via a network such as the internet. The drive 1010 is also connected to the I/O interface 1005 as needed. Removable media 1011, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, or the like, is mounted on drive 1010 as needed so that a computer program read therefrom is mounted to storage 1008 as needed. While an electronic device 1000 is shown that includes various means, it is understood that not all illustrated means are required to be implemented or included. More or fewer devices may be implemented or included instead.

For example, the electronic device 1000 may further include a peripheral interface (not shown) and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, etc. The communication means 1009 may communicate with a network, such as the internet, an intranet, and/or a wireless network, such as a cellular telephone network, a wireless Local Area Network (LAN), and/or a Metropolitan Area Network (MAN), and other devices via wireless communication. The wireless communication may use any of a variety of communication standards, protocols, and technologies including, but not limited to, global System for Mobile communications (GSM), enhanced Data GSM Environment (EDGE), wideband code division multiple Access (W-CDMA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), bluetooth, wi-Fi (e.g., based on the IEEE 802.11 a, IEEE 802.11 b, IEEE 802.11 g, and/or IEEE 802.11 n standards), voice over Internet protocol (VoIP), wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.

For example, the electronic device 1000 may be any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game console, a television, a digital photo frame, a navigator, a server, or any combination of a data processing apparatus and hardware, which is not limited in the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a non-transitory storage medium that non-transitory stores computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, the storage indexing method provided by at least one embodiment of the present disclosure is implemented. Wherein the processor comprises at least one processing unit.

Fig. 10 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. As shown in fig. 10, the non-transitory storage medium 900 may non-transitory store computer-executable instructions 910, which when executed by a computer, implement a storage indexing method provided by any of the embodiments of the present disclosure.

The technical effects of the non-transitory storage medium are the same as those of the storage indexing method, and are not repeated here.

It is noted that the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises at least one executable instruction for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In general, the various example embodiments of the disclosure may be implemented in hardware or special purpose circuits, software, firmware, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

For the purposes of this disclosure, the following points are to be described:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of storing an index, comprising:

receiving an access request to a storage device, wherein the access request comprises an access address, and the storage device comprises a plurality of storage spaces;

Determining a target storage space corresponding to the access address in the plurality of storage spaces according to a space index field belonging to the tag part in the access address;

and performing storage access in the target storage space according to the access address.

2. The storage indexing method of claim 1, wherein the total storage capacity of the storage device is not equal to an integer power of 2, and/or the storage capacity of each of the plurality of storage spaces is an integer power of 2.

3. The storage indexing method as claimed in claim 1, wherein said determining, according to a spatial index field belonging to a tag part in the access address, a corresponding target storage space of the access address among the plurality of storage spaces comprises:

determining a storage space access index according to address bits in the space index field in the access address;

And determining the target storage space according to the storage space access index.

4. The storage indexing method of claim 3, wherein said determining a storage space access index from address bits in said spatial index field in said access address comprises:

and carrying out operation on the numerical value of the address bit in the space index field, and determining the storage space access index according to the operation result of the operation.

5. The storage indexing method of claim 4, wherein the plurality of storage spaces correspond to a plurality of theoretical result values determined according to the operation result;

A first ratio of the number of corresponding theoretical result values for each storage space to the total number of the plurality of theoretical result values matches a second ratio of the storage capacity of each storage space to the total storage capacity of the plurality of storage spaces.

6. The storage indexing method of claim 4, wherein the operation comprises a modulo operation or a hash operation.

7. The storage indexing method of claim 6, wherein the modulo operation comprises:

and obtaining an operation result obtained by performing modular computation on the numerical value of the address bit in the spatial index field by using a modulus determined by performing proportional operation on the basis of the plurality of storage spaces.

8. The storage indexing method of claim 1, wherein the plurality of storage spaces are divided into a plurality of storage space groups, each storage space group of the plurality of storage space groups including at least one storage space, the storage indexing method further comprising:

and determining a corresponding target storage space group of the access address in the storage device according to the group index field in the space index field.

9. The storage indexing method of claim 8, further comprising:

And determining a corresponding target storage space of the access address in the target storage space group according to the space index field.

10. The storage indexing method of any one of claims 1 to 9, wherein each of the plurality of storage spaces is mapped in a direct-associative or group-associative manner.

11. The storage indexing method of any one of claims 1 to 9, wherein the access address comprises a tag portion and an index portion;

the memory access in the target memory space according to the access address comprises:

Addressing a target storage location in the target storage space according to the index portion, and

And comparing the target access data corresponding to the access request with the tags stored in the target storage location according to the tag part to confirm that the target access data corresponding to the access request is stored in the target storage location.

12. A storage index device for a storage device, comprising:

a receiving unit configured to receive an access request to the storage device, wherein the access request includes an access address, and the storage device includes a plurality of storage spaces;

And the access unit is configured to determine a corresponding target storage space of the access address in the storage device according to the space index field belonging to the tag part in the access address, and perform storage access in the target storage space according to the access address.

13. The storage index device of claim 12, wherein the access unit comprises:

The modular unit is configured to perform modular operation on the numerical value of the address bit in the space index field, and determine a storage space access index according to the operation result of the modular operation;

14. The storage index device of claim 13, wherein the space selection unit comprises a first AND gate and a second AND gate,

15. An electronic device, comprising:

at least one memory configured to store computer-executable instructions, and

At least one processor configured to execute the computer-executable instructions,

Wherein the computer-executable instructions, when executed by the at least one processor, implement the storage indexing method of any one of claims 1-11.

16. A non-transitory storage medium storing computer-executable instructions non-transitory, wherein the storage indexing method of any one of claims 1-11 is implemented when at least one processor executes the computer-executable instructions.