CN113590506B - HMB table entry management method and solid state disk control system - Google Patents
HMB table entry management method and solid state disk control system Download PDFInfo
- Publication number
- CN113590506B CN113590506B CN202110880087.6A CN202110880087A CN113590506B CN 113590506 B CN113590506 B CN 113590506B CN 202110880087 A CN202110880087 A CN 202110880087A CN 113590506 B CN113590506 B CN 113590506B
- Authority
- CN
- China
- Prior art keywords
- address
- units
- hmb
- host
- mapping table
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000007787 solid Substances 0.000 title claims abstract description 29
- 238000007726 management method Methods 0.000 title claims abstract description 16
- 238000013507 mapping Methods 0.000 claims abstract description 102
- 238000000034 method Methods 0.000 claims abstract description 14
- 230000006870 function Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000011022 operating instruction Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000013403 standard screening design Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
Abstract
The application discloses an entry management method of HMB, which comprises the following steps: obtaining a logic address in a host operation instruction; accessing a first-level mapping table according to the logical address and acquiring a second-level index address; accessing HMB according to the secondary index address to obtain a physical address; and carrying out corresponding data operation on the memory of the solid state disk according to the physical address. The method for managing the table entries of the HMB adopts the first-level mapping or the second-level mapping to directly access the HMB address of the physical address of the corresponding data in the HMB, thereby further reducing the time expenditure caused by accessing the HMB.
Description
Technical Field
The invention relates to the technical field of SSD mapping table management, in particular to an entry management method of HMB and a control system of a solid state disk.
Background
The host memory buffer (Host Memory Buffer, HMB) function allows the SSD (Solid STATE DRIVE, solid state disk) host chip to use host DRAM as well as DRAM on the SSD (Dynamic Random Access Memory ). I.e., the host divides a piece of memory (which may be discontinuous in physical address) into SSD usage in its main memory.
Currently mainstream SSDs generally have two designs, one is with DRAM, which can be used to cache data and mapping tables; the other is without DRAM (i.e., DRAM-Less scheme), the mapping table uses a secondary mapping, the primary mapping and a small number of secondary mappings are stored in SRAM (Static Random-Access Memory), and the secondary mapping data is stored in NAND FLASH. For the DRAM-Less scheme, since most of its mapping table is stored in NAND FLASH, when it performs random reading, flash needs to be accessed twice, the first time the mapping table is obtained, and the second time the user data is actually read. If the mapping data is stored in NAND FLASH, it takes more time to read the mapping data, thereby degrading the read performance of the SSD.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide an entry management method of HMB and a control system of a solid state disk, which directly access an HMB address of a physical address of corresponding data in HMB by using a primary mapping or a secondary mapping, so as to further reduce time overhead caused by accessing HMB.
According to an aspect of the present invention, there is provided an entry management method of HMB, including: obtaining a logic address in a host operation instruction; accessing a first-level mapping table according to the logical address and acquiring a second-level index address; accessing a host HMB according to the secondary index address to acquire a physical address; and carrying out corresponding data operation on the memory of the solid state disk according to the physical address.
Optionally, accessing the primary mapping table and obtaining the secondary index address according to the logical address includes: accessing the primary mapping table in the SRAM chip of the solid state disk according to the logic address; and inquiring the primary mapping table to obtain the secondary index address of the physical address of the corresponding data in the HMB.
Optionally, accessing the primary mapping table and obtaining the secondary index address according to the logical address includes: carrying out hash function processing on the logical address to obtain a primary index address; and accessing the primary mapping table in the HMB of the host according to the primary index address and acquiring the secondary index address.
Optionally, accessing the HMB based on the secondary index address to obtain the physical address includes: and accessing a secondary mapping table in the HMB of the host according to the secondary index address, and inquiring the secondary mapping table to acquire a physical address.
According to another aspect of the present invention, there is provided a control system for a solid state disk, including: a host interface connected to the host to receive an operation instruction, the meta information of the operation instruction including a logical address of user data; a controller connected to the memory, performing a data operation based on a physical address of the user data; and the processor is connected with the host interface and the controller, wherein when the host accesses the solid state disk, the processor obtains a logical address of user data, searches a first-level mapping table according to the logical address to obtain a second-level index address, and accesses the HMB according to the second-level index address to obtain a physical address of the user data.
Optionally, the processor performs hash function processing on the logical address to obtain a primary index address, and searches a primary mapping table according to the primary index address.
Optionally, the processor searches the secondary mapping table according to the secondary index address to obtain the physical address of the user data.
Optionally, the method further comprises: and the SRAM chip is stored with a first mapping table.
Optionally, the SRAM chip includes a storage module and a link module, where the storage module is configured to store a primary mapping table, and the storage module establishes a connection with a host through the link module.
The method for managing the table entries of the HMB provided by the invention adopts the secondary mapping, the address of the primary mapping table stored in the HMB can be firstly obtained from the logical address of the operation instruction of the host, and then the logical address in the secondary mapping table is obtained according to the primary mapping table, wherein the address indicates the position of corresponding data in the memory of the solid state disk, and the time for looking up the table in the HMB of the host is far less than the time for looking up the table in the solid state disk, so that the time expenditure generated by looking up the table in the whole operation process can be shortened, and the reading performance of the solid state disk is improved.
Further, a primary mapping scheme may be adopted, and the physical address of the corresponding data mapped in the HMB may be directly obtained through the primary mapping table in the SRAM in the SSD. The number of times of accessing the HMB is reduced from original secondary access to primary access, so that the time cost caused by inquiring the mapping table is shortened again to a great extent, and the reading performance of the SSD is further improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1a shows an architecture diagram of a computer system according to an embodiment of the invention;
FIG. 1b shows a flowchart of an entry management method of HMB according to a first embodiment of the invention;
FIG. 1c illustrates a mapping relationship between logical addresses and physical addresses in the computer system shown in FIG. 1 b;
FIG. 2a shows an architecture diagram of an HMB according to a second embodiment of the invention;
fig. 2b shows a flow chart of an entry management method of HMB in accordance with a second embodiment of the invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the invention. The figures are not necessarily drawn to scale.
The flowcharts, block diagrams in the figures illustrate the possible architectural framework, functions, and operations of the systems, methods, apparatus of the embodiments of the present invention, and the blocks in the flowcharts and block diagrams may represent a module, a program segment, or a code segment, which is an executable instruction for implementing the specified logical function(s). It should also be noted that the executable instructions that implement the specified logic functions may be recombined to produce new modules and program segments. The blocks of the drawings and the order of the blocks are thus merely to better illustrate the processes and steps of the embodiments and should not be taken as limiting the invention itself.
The following terminology is used hereinafter.
Address mapping: mapping of logical addresses to physical addresses, the core function of the memory control system, is the basis for many other modules.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
FIG. 1a shows an architecture diagram of a computer system according to an embodiment of the invention; FIG. 1b shows a flowchart of an entry management method of HMB according to a first embodiment of the invention; FIG. 1c illustrates a mapping relationship between logical addresses and physical addresses in the computer system shown in FIG. 1 b.
For a DRAM-less SSD, a set of mechanism is provided by using a Host HMB (Host Memory Buffer ), so that the Solid State Disk (SSD) can use the free memory space at the Host end of the Host through the NVMe protocol, and the memory space can replace the DRAM for the L2P table access at the SSD end, thereby saving the cost while accelerating the SSD performance.
Referring to FIG. 1a, a computer system of an embodiment of the present invention includes: host 110, control system 120, and memory 130. The control system 120 and the memory 130 belong to solid state disks, and a storage medium of the memory 130 is, for example, a flash memory chip array.
The host interface 121 of the control system 120 is connected to the host 110 to transmit instructions. Host interface 121 is, for example, SATA, M.2, mSATA, and PCI-E. The processor 122 is connected to the host interface 121, the controller 124, and the SRAM chip 123. The SRAM chip 123 in the control system 120 may be used, for example, to store an L2P mapping table. The processor 122 is used to implement a core software layer of memory control, FTL (Flash Translation Layer ), so that the operating system and file system can access the memory 130 as if it were a hard disk. The FTL also has features such as supporting all SLC (SINGLE LEVEL CELL, single layer unit) and MLC (Multi-LEVEL CELL, multi-layer unit), supporting bad block management, wear leveling, garbage collection, power-down restoration, write balancing techniques, etc., and the core function of the FTL is address mapping.
Memory 130 includes an array of flash memory chips. To improve data read/write performance, the controller 124 of the control system 120 may read/write the flash memory chip of the memory 130 via multiple channels. Each channel is connected to a set of flash memory chips. Each flash memory chip includes a plurality of physical blocks, each physical block including a plurality of physical pages. Data access operations to flash memory chips include read, write, and erase. Due to the physical characteristics of the flash memory chip, a basic unit of data operation is, for example, a physical page, and a basic unit of erase operation is, for example, a physical block.
When the host 110 performs a data operation, the control system 120 receives an instruction from the host 110. The control system 120 maps logical addresses in the instructions to physical addresses that characterize locations in the memory 130, including channels, physical blocks, physical pages, and the like.
In the HMB of the host 110, a mapping table for mapping the logical address to the physical address is stored, and the SSD obtains the corresponding physical address to perform the corresponding operation according to the lookup mapping table. Because the mapping table is stored in the host 110, and the time required for looking up the table from the host is smaller than the time required for looking up the table from the solid state disk, the time overhead generated by looking up the table can be shortened, and the reading performance of the SSD can be improved.
Fig. 1b shows a flow chart of an entry management method of HMB according to a first embodiment of the invention, in which the entry management method of HMB is illustrated by way of example with a read operation, the method comprising in particular the following steps in connection with fig. 1a and 1 c:
step S01: and calculating a corresponding primary index address according to the logical address.
In this step, the host 110 sends a read operation instruction to the Solid State Disk (SSD), and the host interface 121 of the control system 120 receives the read operation instruction from the host 110, where the read operation instruction includes at least a logical address of the read data, and the processor 122 calculates according to the obtained logical address, so as to obtain a primary index address corresponding to the logical address.
In this embodiment, the logical address is processed using a hash function to obtain a primary index address.
Step S02: and searching a primary mapping table in the HMB according to the primary index address as an index and obtaining a secondary index address.
In this embodiment, the primary index address points to the location of the primary mapping table in the host HMB, so the primary mapping table 10 can be found with the primary index address as an index. Further, the primary mapping table 10 stores the addresses of the secondary mapping table 20, so that the secondary index address pointing to the secondary mapping table 20 can be obtained by querying the primary mapping table.
In this embodiment, referring to fig. 1a, in the HMB of the host, the HMB is divided into two areas, which are respectively used for storing the primary mapping table 10 and the secondary mapping table 20, and when the host sends an operation instruction to the SSD, the interface end of the SSD resolves the primary index address according to the logical address in the operation instruction.
Step S03: and searching a secondary mapping table in the HMB according to the secondary index address as an index and obtaining a physical address.
In this embodiment, the secondary index address points to the location of the secondary mapping table in the host HMB, so that the secondary mapping table 20 can be found with the secondary index address as an index. Further, the physical address of the corresponding data stored in the memory 130 of the SSD is stored in the secondary mapping table 20, and thus, the physical address pointing to the corresponding data storage can be obtained by referring to the secondary mapping table.
Step S04: the required data is read from the memory according to the physical address.
In this embodiment, the physical address points to a location in the memory in the SSD, and thus, the corresponding information stored in the memory can be read according to the physical address.
Further, referring to fig. 1c, the index of the primary mapping table is a primary index address calculated according to the logical address, and the content of the primary mapping table is a secondary index address of the secondary mapping table. The index of the secondary mapping table is a secondary index address, and the content is a physical address of the corresponding data in the memory 130. In this embodiment, when the mapping table is stored in the HMB of the host 110 and the SSD performs address mapping, the mapping table stored in the HMB of the host 110 can be accessed to find the physical address of the corresponding data more quickly than the mapping table stored in the memory 130, thereby realizing the corresponding data operation, and thus improving the performance of the SSD.
The control system 120 in the SSD calculates a primary index address according to a logical address in the host data operation instruction, searches a primary mapping table in the host HMB to obtain a secondary index address, and then searches a secondary mapping table in the host HMB based on the secondary index address to obtain a physical address of the data operation. The logical block address of the secondary index address in the primary mapping table corresponds to the block address of the secondary mapping table's own storage location, and the block address of the physical address in the secondary mapping table corresponds to the block address of the user data store in the SSD. Because the secondary mapping table is stored on a predetermined physical block in the host HMB, the logical block address of the primary mapping table need not characterize all block addresses of the entire host memory, only specific block addresses of the entire host memory, and thus the storage capacity requirements of the primary mapping table can be reduced. Further, the control system 120 in the SSD performs corresponding data operations on the memory 130 via the controller 124 based on the physical address.
In this embodiment, the second-level mapping is adopted, the address of the first-level mapping table stored in the HMB may be obtained from the logical address of the host operating instruction, and then the logical address in the second-level mapping table is obtained according to the first-level mapping table, where the address indicates the position of the corresponding data in the memory of the solid-state hard disk.
FIG. 2a shows an architecture diagram of an HMB according to a second embodiment of the invention; fig. 2b shows a flow chart of an entry management method of HMB in accordance with a second embodiment of the invention. Referring to fig. 2a and 2b, specific steps of a flowchart of an entry management method of HMB according to a second embodiment of the present invention include:
step S11: and inquiring the primary mapping table according to the logical address and acquiring the secondary index address.
In this step, the host 110 sends a read operation instruction to the Solid State Disk (SSD), the host interface 121 of the control system 120 receives the read operation instruction from the host 110, where the read operation instruction includes at least a logical address of the read data, and the processor 122 performs a query of a first-level mapping table according to the obtained logical address, where the first-level mapping table is located in the SRAM of the solid state disk, and because the memory of the SRAM is limited, the SRAM stores a storage address of a physical address of the corresponding data in the HMB, that is, a second-level index address can be obtained by querying the first-level mapping table, and the second-level index address points to an address in the HMB.
In this embodiment, referring to fig. 1a and fig. 2a, the primary mapping table is stored in the SRAM chip 123 of the SSD of the solid state disk, and the physical address of the data in the memory 130 of the solid state disk is directly stored in the HMB of the host, so that the control system 120 of the solid state disk can access the primary mapping table in the SRAM chip 123 through the logical address in the operation instruction of the host, and then directly access the physical address of the corresponding data in the memory 130 of the solid state disk stored in the HMB.
In this embodiment, the SRAM chip 123 includes two parts, one part is a memory module storing the primary mapping table, and the other part is a link module, specifically, after accessing the primary mapping table, the address of the corresponding data in the HMB is accessed through the link module. In the SRAM chip 123, the storage module and the link module are each composed of a plurality of units, wherein the primary mapping table is stored in n units SLOT (0) to SLOT (n) of the storage module, a part of the primary mapping table is stored in each unit SLOT, the link module is also divided into m units hmb_id0 to hmb_idm, n and m are natural numbers greater than 1, n of the storage module is greater than m due to the limited storage space of the SRAM chip 123, and the physical address stored in the HMB of the memory 130 is also divided into x address units DATAPHYSICAL ADDR SLOT (0) to DATA PHYSICAL ADDR SLOT (x). In the process of accessing the HMB through the SRAM chip 123, m units hmb_id0 to hmb_idm in the link module first establish connection relations with m units SLOT in the memory module and m address units in the HMB, respectively, and after the access is finished, the connection relations are disconnected, and a link relation is established with the memory module unit SLOT which is not connected before and the address unit DATA PHYSICAL ADDR SLOT in the HMB again, thereby realizing the access path between the SRAM chip 123 and the HMB.
Step S12: and inquiring the HMB according to the secondary index address and obtaining the physical address.
In this embodiment, the secondary index address points to the location in the host HMB where the physical address is located, so that the secondary mapping table 20 can be found with the secondary index address as an index. Further, the physical address of the corresponding data stored in the memory 130 of the SSD is stored in the secondary mapping table 20, and thus, the physical address pointing to the corresponding data storage can be obtained by referring to the secondary mapping table.
Step S13: the required data is read from the memory according to the physical address.
In this embodiment, the physical address points to a location in the memory in the SSD, and thus, the corresponding information stored in the memory can be read according to the physical address.
In this embodiment, a primary mapping scheme is adopted, and the physical address of the corresponding data mapped in the HMB can be directly obtained through the primary mapping table in the SRAM chip in the SSD. The number of times of accessing the HMB is reduced from original secondary access to primary access, so that the time cost caused by inquiring the mapping table is shortened again to a great extent, and the reading performance of the SSD is further improved.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (5)
1. The entry management method of the HMB is applied to a DRAM-Less solid state disk, and the DRAM-Less solid state disk comprises an SRAM chip, and is characterized in that the SRAM chip comprises a storage module and a link module, n units in the storage module store a first-level mapping table, m units in the link module store a second-level index address, wherein n is greater than m, and n and m are natural numbers greater than 1, and the method comprises the following steps:
Obtaining a logic address in a host operation instruction;
M units in the link module respectively establish connection relations with m units in the storage module and m address units in the host HMB;
Accessing a primary mapping table of not more than m units in the storage module according to the logical address to obtain a secondary index address of not more than m units in the link module;
Accessing a host HMB according to the secondary index address to acquire a physical address;
and carrying out corresponding data operation on the memory of the solid state disk according to the physical address.
2. The method of claim 1, wherein the host HMB includes x address units, x being a natural number greater than m, accessing the host HMB to obtain the physical address from the secondary index address includes:
Accessing not more than m address units in the host HMB according to the secondary index addresses of not more than m units in the link module, and accessing physical addresses in the not more than m address units;
after the physical address is obtained by accessing m address units of the host connected with m units in the link module according to the secondary index address, the method further comprises:
And disconnecting the connection relation, and establishing connection relation between m units in the link module and units in the storage module which are not connected before and host address units.
3. A control system for a solid state disk, the system comprising:
A host interface connected to the host to receive an operation instruction, the meta information of the operation instruction including a logical address of user data;
a controller connected to the memory, performing a data operation based on a physical address of the user data;
a processor connected with the host interface and the controller,
The SRAM chip comprises a storage module and a link module, n units in the storage module store a first-level mapping table, m units in the link module store a second-level index address, wherein n is greater than m, and n and m are natural numbers greater than 1;
When the host accesses the solid state disk, the processor obtains a logical address of user data, m units in the link module respectively establish a connection relationship with m units in the storage module and m address units in the host HMB, the processor accesses a first-level mapping table of not more than m units in the storage module according to the logical address to obtain a second-level index address of not more than m units in the link module, and accesses the HMB according to the second-level index address to obtain a physical address of the user data.
4. A control system according to claim 3, wherein the processor looks up the secondary mapping table in the host HMB based on the secondary index address to obtain the physical address of the user data.
5. A control system according to claim 3, wherein the host HMB comprises x address units, x being a natural number greater than m;
the processor accesses a primary mapping table of not more than m units in the storage module according to the logical address to obtain a secondary index address of not more than m units in the link module;
After the processor accesses m address units of the host connected with m units in the link module according to the secondary index address, the link module disconnects the connection relation, and the m units in the link module re-establish the connection relation with the units in the storage module which are not connected before and the host address units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110880087.6A CN113590506B (en) | 2021-08-02 | 2021-08-02 | HMB table entry management method and solid state disk control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110880087.6A CN113590506B (en) | 2021-08-02 | 2021-08-02 | HMB table entry management method and solid state disk control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113590506A CN113590506A (en) | 2021-11-02 |
| CN113590506B true CN113590506B (en) | 2024-10-18 |
Family
ID=78253590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110880087.6A Active CN113590506B (en) | 2021-08-02 | 2021-08-02 | HMB table entry management method and solid state disk control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113590506B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111831579A (en) * | 2019-04-16 | 2020-10-27 | 爱思开海力士有限公司 | Controller, method of operation, and memory system including controller |
| CN112416819A (en) * | 2020-11-05 | 2021-02-26 | 深圳电器公司 | Method and device for realizing solid state drive based on host memory buffer |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105243025B (en) * | 2015-09-25 | 2019-04-19 | 北京联想核芯科技有限公司 | A kind of formation of mapping table and loading method, electronic equipment |
| CN105205009B (en) * | 2015-09-30 | 2018-05-11 | 华为技术有限公司 | A kind of address mapping method and device based on large capacity solid-state storage |
| US10712949B2 (en) * | 2017-11-09 | 2020-07-14 | Western Digital Technologies, Inc. | Adaptive device quality of service by host memory buffer range |
| US10884947B2 (en) * | 2017-11-17 | 2021-01-05 | SK Hynix Inc. | Methods and memory systems for address mapping |
| TWI679538B (en) * | 2018-03-31 | 2019-12-11 | 慧榮科技股份有限公司 | Control unit for data storage system and method for updating logical-to-physical mapping table |
| CN110083481A (en) * | 2019-04-28 | 2019-08-02 | 深圳忆联信息系统有限公司 | The guard method of logical physical mapping table, device and solid state hard disk based on HMB |
-
2021
- 2021-08-02 CN CN202110880087.6A patent/CN113590506B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111831579A (en) * | 2019-04-16 | 2020-10-27 | 爱思开海力士有限公司 | Controller, method of operation, and memory system including controller |
| CN112416819A (en) * | 2020-11-05 | 2021-02-26 | 深圳电器公司 | Method and device for realizing solid state drive based on host memory buffer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113590506A (en) | 2021-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11789860B2 (en) | Logical to physical mapping management using low-latency non-volatile memory | |
| US10152428B1 (en) | Virtual memory service levels | |
| US10067684B2 (en) | File access method and apparatus, and storage device | |
| US20200117368A1 (en) | Method for achieving data copying in ftl of solid state drive, system and solid state drive | |
| US8909895B2 (en) | Memory apparatus | |
| US11237980B2 (en) | File page table management technology | |
| US20100312955A1 (en) | Memory system and method of managing the same | |
| CN108595349B (en) | Address translation method and device for mass storage device | |
| CN104102591A (en) | Computer subsystem and method for implementing flash translation layer therein | |
| CN113419675B (en) | Write operation method and read operation method for memory | |
| KR20130096881A (en) | Flash memory device | |
| CN116431530B (en) | CXL memory module, memory processing method and computer system | |
| US20230138215A1 (en) | Memory system controlling nonvolatile memory | |
| CN115878029A (en) | Address mapping method and control system for solid state disk | |
| US11061598B2 (en) | Optimized handling of multiple copies in storage management | |
| WO2016206070A1 (en) | File updating method and storage device | |
| KR100533683B1 (en) | Data managing device and method for flash memory | |
| CN113590506B (en) | HMB table entry management method and solid state disk control system | |
| CN117215485A (en) | ZNS SSD management method, data writing method, storage device and controller | |
| CN115344201A (en) | Data storage method, data query method and device | |
| CN110362509B (en) | Unified address conversion method and unified address space | |
| CN109165172B (en) | Cache data processing method and related equipment | |
| CN113946279A (en) | Data reading method and device in host efficiency acceleration mode | |
| US12038852B2 (en) | Partial logical-to-physical (L2P) address translation table for multiple namespaces | |
| CN116010298B (en) | Method, device, electronic device and storage medium for NAND flash memory address mapping |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 310051 room c1-604, building C, No. 459, Qianmo Road, Xixing street, Binjiang District, Hangzhou, Zhejiang Province Applicant after: Lianyun Technology (Hangzhou) Co.,Ltd. Address before: 6 / F, block C1, spotlight center, 459 Qianmo Road, Binjiang District, Hangzhou City, Zhejiang Province, 310051 Applicant before: MAXIO TECHNOLOGY (HANGZHOU) Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |