CN119325257A - Self-aligned buried gate metal MOSFET and method of manufacture - Google Patents
Self-aligned buried gate metal MOSFET and method of manufacture Download PDFInfo
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Abstract
本发明公开了一种自对准埋入式栅极金属MOSFET及制造方法，包括：设于衬底上的半导体层，半导体层中自表面向衬底方向依次设有体区和漂移区，体区中设有位于半导体层表面以下的源区；设于源区上方的半导体层表面上的一对第一侧墙；设于一对第一侧墙之间的半导体层中且穿过源区的沟槽栅；埋入在一对第一侧墙之间且连接沟槽栅的栅极金属；设于沟槽栅一侧的半导体层中的源区接触沟槽，和填充于源区接触沟槽中并连接源区的源区接触金属；栅极金属和源区接触金属分别通过导电接触孔连接金属互连层。本发明能加快导通速度，增加开关频率，并能在减少光罩和消除套刻误差的同时，缩小器件面积，减小短路电阻，改善了器件性能。
The present invention discloses a self-aligned buried gate metal MOSFET and a manufacturing method, comprising: a semiconductor layer arranged on a substrate, a body region and a drift region are arranged in sequence from the surface to the substrate in the semiconductor layer, a source region located below the surface of the semiconductor layer is arranged in the body region; a pair of first sidewalls are arranged on the surface of the semiconductor layer above the source region; a trench gate is arranged in the semiconductor layer between the pair of first sidewalls and passes through the source region; a gate metal is buried between the pair of first sidewalls and connected to the trench gate; a source region contact trench is arranged in the semiconductor layer on one side of the trench gate, and a source region contact metal is filled in the source region contact trench and connected to the source region; the gate metal and the source region contact metal are respectively connected to the metal interconnection layer through conductive contact holes. The present invention can speed up the conduction speed, increase the switching frequency, and can reduce the device area, reduce the short-circuit resistance, and improve the device performance while reducing the mask and eliminating the overlay error.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a self-aligned buried gate metal MOSFET and a manufacturing method thereof.
Background
The trench MOSFET may provide a shorter source-drain current path relative to a planar structure MOSFET, thereby reducing on-resistance, allowing more current to travel through the switch, and significantly reducing power losses. Reducing the spacing between structures in a MOSFET device, allowing for a smaller die area for the MOSFET device, can achieve further reductions in resistance per square area, and increases current density.
However, as the device area is continuously reduced, the number of processing steps and the number of masks in the manufacturing process are increased, which certainly increases the manufacturing cost. In addition, due to the existence of overlay error, the short-circuit resistance is also increased.
On the other hand, due to the continuous reduction of the area of the device, when the voltage is conducted by adopting a direct connection mode of the tungsten contact hole and the polysilicon gate in the trench gate, the voltage is not reliable any more, and the problem of lowering of the conducting speed, namely lowering of the switching frequency, is easy to occur.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a self-aligned buried gate metal MOSFET and a method of fabrication.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the invention provides a self-aligned buried gate metal MOSFET, comprising:
The semiconductor layer is arranged on a substrate, a body region and a drift region are sequentially arranged in the semiconductor layer from the surface to the substrate, and a source region below the surface of the semiconductor layer is arranged in the body region;
a pair of first side walls arranged on the surface of the semiconductor layer above the source region;
A trench gate disposed in the semiconductor layer between the pair of first sidewalls and passing through the source region;
A gate metal buried between a pair of the first sidewalls and connected to the trench gate;
A source region contact trench in the semiconductor layer at one side of the trench gate, and a source region contact metal filled in the source region contact trench and connected to the source region;
The gate metal and the source region contact metal are respectively connected with the metal interconnection layer through conductive contact holes.
Further, the trench gate is provided with a polysilicon gate, and the polysilicon gate is connected with the gate metal.
Further, the bottom of the trench gate is also located in the drift region through the body region.
Further, the bottom of the source region contact trench is located in the body region, a transition connection portion is further arranged in the semiconductor layer along the wall of the source region contact trench, and the source region contact metal is further connected with the source region and the body region through the transition connection portion.
Further, the source region and the source region contact trench are alternately connected along the surface of the semiconductor layer, a pair of first side walls are arranged on the surface of the semiconductor layer above each source region, the gate metal and the trench gate are arranged between each pair of first side walls, and the source region contact metal is embedded between two adjacent pairs of first side walls and filled in the source region contact trench.
The invention also provides a manufacturing method of the self-aligned buried gate metal MOSFET, which comprises the following steps:
Providing a substrate, and forming a semiconductor layer on the surface of the substrate;
forming a drift region in the semiconductor layer, and forming a body region positioned on the drift region below the surface of the semiconductor layer;
Forming a source region located in the body region below the surface of the semiconductor layer;
Forming a pair of first side walls on the surface of the semiconductor layer above the source region;
Forming a trench gate passing through the source region in the semiconductor layer between a pair of the first sidewalls;
forming a gate metal buried between a pair of the first sidewalls and connecting the trench gate;
forming a source region contact trench in the semiconductor layer at one side of the trench gate;
forming a source region contact metal filled in the source region contact trench and connected with the source region;
forming an interlayer dielectric layer on the top surfaces of the first side wall, the gate metal and the source region contact metal;
forming conductive contact holes with bottoms respectively connected with the gate metal and the source region contact metal in the interlayer dielectric layer;
and forming a metal interconnection layer connected with the top of the conductive contact hole on the interlayer dielectric layer.
Further, the forming a source region located in the body region below the surface of the semiconductor layer specifically includes:
Forming a plurality of first hard mask layer patterns on the surface of the semiconductor layer;
Forming a second hard mask layer on the surface of the semiconductor layer, covering the first hard mask layer pattern, carrying out back etching, forming second hard mask layer patterns on two sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the surface of the semiconductor layer between the two second hard mask layer patterns on the adjacent sides;
Forming a third hard mask layer on the surface of the semiconductor layer, covering the first hard mask layer pattern and the second hard mask layer pattern, carrying out back etching, forming a third hard mask layer pattern between the two second hard mask layer patterns positioned on the adjacent sides, and exposing the tops of the first hard mask layer pattern and the second hard mask layer pattern;
Removing the second hard mask layer pattern, and forming an injection window between the first hard mask layer pattern and the third hard mask layer pattern;
And forming a source region in the body region below the surface of the semiconductor layer below the implantation window by using the implantation window and adopting a multidirectional ion implantation process.
Further, the forming a pair of first sidewalls on the surface of the semiconductor layer above the source region, forming a trench gate penetrating the source region in the semiconductor layer between the pair of first sidewalls, forming a gate metal buried between the pair of first sidewalls and connected to the trench gate, specifically includes:
Forming first side walls on two sides of the first hard mask layer pattern and two sides of the third hard mask layer pattern respectively so as to form a pair of first side walls formed by two first side walls on adjacent sides on the surface of the semiconductor layer above the source region and expose the surface of the semiconductor layer between the pair of first side walls;
forming a gate trench penetrating through the source region downwards on the surface of the semiconductor layer between a pair of first side walls by taking the first hard mask layer pattern and the first side walls on two sides of the first hard mask layer pattern and the third hard mask layer pattern and the first side walls on two sides of the first hard mask layer pattern as common masks;
Forming a gate oxide layer on the inner wall of the gate trench, and forming a gate in the gate trench within the gate oxide layer, thereby forming a trench gate;
And filling first metal between the pair of first side walls, and carrying out back etching to form gate metal which is buried between the pair of first side walls and is connected with the trench gate.
Further, the forming a source region contact trench in the semiconductor layer at one side of the trench gate, forming a source region contact metal filled in the source region contact trench and connected with the source region, specifically includes:
removing the first hard mask layer pattern and the third hard mask layer pattern through back etching;
Forming a source region contact groove downwards on the surface of the semiconductor layer exposed between the two first side walls on the adjacent sides by taking the grid metal and the first side walls on the two sides thereof as a common mask, connecting the side walls of the source region contact groove with the source region, and enabling the bottom of the source region contact groove to be positioned in the body region;
Filling second metal between the two first side walls of the adjacent side, removing redundant second metal except the tops of the two first side walls of the adjacent side, exposing the tops of the grid metal, and forming the source region contact metal which is embedded and filled in the source region contact groove between the two first side walls of the adjacent side and is connected with the source region;
Or comprises:
removing the first hard mask layer pattern and the third hard mask layer pattern through back etching;
forming a second side wall on the outer sides of the pair of first side walls;
Forming a source region contact groove downwards on the surface of the semiconductor layer exposed between the two second side walls on the adjacent sides by taking the grid metal and the first side walls and the second side walls on the two sides as common masks, connecting the side walls of the source region contact groove with the source region, and enabling the bottom of the source region contact groove to be positioned in the body region;
And removing the second side wall, filling second metal between the two first side walls on the adjacent sides, removing redundant second metal except the tops of the two first side walls on the adjacent sides, exposing the tops of the grid metal, and forming the source region contact metal which is embedded and filled in the source region contact groove between the two first side walls on the adjacent sides and is connected with the source region.
Further, after the source region contact trench is formed, a transition connection portion is formed in the semiconductor layer along the wall of the source region contact trench by ion implantation, and then the source region contact metal filled in the source region contact trench is formed, so that the source region contact metal is connected with the source region and the body region through the transition connection portion.
According to the technical scheme, the grid metal connected with the trench gate is formed on the trench gate, so that the grid electrode (such as the polysilicon grid electrode) in the trench gate is connected with the conductive contact hole through the grid metal, and the voltage conducted by the conductive contact hole is reliably conducted to the trench gate through the grid metal, so that the contact resistance between the trench gate and the conductive contact hole can be effectively reduced, the reliability of the voltage conduction between the conductive contact hole and the trench gate is improved, the conduction speed can be increased, namely the switching frequency can be increased, and the problem that the conduction speed is easy to be reduced, namely the switching frequency is reduced when the voltage is conducted by adopting the direct connection mode of the tungsten contact hole and the polysilicon grid electrode in the trench gate is effectively solved. And, by forming a pair of first sidewalls over the source region in a self-aligned manner, a trench gate self-aligned to the source region can be formed in the semiconductor layer between the pair of first sidewalls, and a source contact trench and a source contact region self-aligned to the trench gate can be formed on one side of the pair of first sidewalls (trench gate), so that not only can the mask be reduced, but also the spacing between the structures in the MOSFET device can be reduced, so that the MOSFET device has a smaller die area, further reduction of the resistance per square area can be realized, and the current density can be increased, and overlay errors can be eliminated, thereby effectively reducing the short circuit resistance. Further, the second side wall can be formed on the outer side of the first side wall to adjust the size of the source region contact groove, the size of the source region between the source region contact groove and the groove gate can be adjusted, and after the second side wall is removed, filled source region contact metal can be connected with the source region through the top and the side of the source region, so that the contact area is increased, and therefore the requirements of good source region ohmic contact and current bearing capacity can be met, and the device performance is further improved.
Drawings
FIG. 1 is a schematic diagram of a self-aligned buried gate metal MOSFET according to a preferred embodiment of the present invention;
fig. 2-9 are process flow diagrams of a method for fabricating a self-aligned buried gate metal MOSFET in accordance with a preferred embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
The various portions of the MOSFET device can be constructed of materials well known to those skilled in the art unless specifically indicated below. The semiconductor material may include, for example, a III-V semiconductor, such as GaAs, inP, gaN, siC, and a IV semiconductor, such as Si, ge, and the like. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal, a doped polysilicon layer, or a stacked gate conductor comprising a metal and a doped polysilicon layer, or other conductive materials, such as TaC, tiN, taSiN, hfSiN, tiSiN, tiCN, taAlC, tiAlN, taN, ptSi x、Ni3 Si, pt, ru, W, combinations of the various conductive materials, and the like. The gate dielectric (gate oxide layer) may be composed of SiO 2 or a material having a dielectric constant greater than SiO 2, including, for example, oxides, nitrides, oxynitrides, silicates, aluminates, titanates, and the like. Also, the gate dielectric may be formed of not only a material known to those skilled in the art but also a material for a gate dielectric developed in the future.
The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. The N-type may be formed by implanting N-type dopants (e.g., P, as, etc.) into the semiconductor material. The P-type may be formed by implanting a P-type dopant (e.g., B, etc.) into the semiconductor material. The above may be understood by reference to known techniques.
The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings.
Reference is made to fig. 1. A self-aligned buried gate metal MOSFET of the present invention includes, from bottom to top, a substrate 10, a semiconductor layer 23, a metal layer, an interlayer dielectric layer 20 (ILD), and a metal interconnect layer 19.
The following description will take the first conductivity type as N type and the second conductivity type as P type as an example.
The substrate 10 may be a heavily doped n+ type silicon substrate 10 (n+ substrate).
The semiconductor layer 23 may be an epitaxial silicon semiconductor layer 23 provided on the surface of the substrate 10. A drift region 11 (drift) and a body region 12 are provided in the semiconductor layer 23. Wherein the body region 12 is located above the drift region 11 and below the surface of the semiconductor layer 23 remote from the substrate 10. The body region 12 may be a lightly doped P-body region 12 (P-body) and the drift region 11 may be an epitaxial N-type drift region 11 (N DRIFT EPI).
An active region 24 is provided in the body region 12, the active region 24 being located below the surface of the semiconductor layer 23. The source region 24 may be a heavily doped N + type source region 24.
The metal layer is provided with gate metal 21 and source contact metal 15. The gate metal 21 is isolated from the source contact metal 15 by a first sidewall 22.
The first side walls 22 include a pair of first side walls 22 correspondingly provided on the surface of the semiconductor layer 23 above the source region 24. The first sidewalls 22 may be disposed vertically on the surface of the semiconductor layer 23 at a distance that ensures that a pair of the first sidewalls 22 are all over the same source region 24. The first side wall 22 may be formed of a dielectric material.
A trench gate 28 is provided in the semiconductor layer 23 between the pair of first sidewalls 22, the trench gate 28 being disposed through the source region 24. The dimensions of trench gate 28 are determined by the distance between a pair of first sidewalls 22.
A gate metal 21 is buried in the gap between the pair of first sidewalls 22, and the bottom of the gate metal 21 is ohmically connected to the top of the trench gate 28.
An active region contact trench 14 is provided in the semiconductor layer 23 on the side of the trench gate 28, and an opening of the active region contact trench 14 is located on the surface of the semiconductor layer 23. The source contact trench 14 is filled with an active contact metal 15, and the source contact metal 15 is ohmically connected to the source 24 through the wall of the source contact trench 14.
An interlayer dielectric layer 20 and a metal interconnection layer 19 are sequentially provided on the metal layer. The interlayer dielectric layer 20 is provided with a plurality of conductive contact holes 16, the bottoms of the conductive contact holes 16 are respectively in ohmic connection with the tops of the gate metal 21 and the source region contact metal 15, the tops of the conductive contact holes 16 are in ohmic connection with the metal interconnection layer 19, the trench gate 28 is interconnected with the metal interconnection layer 19 through the gate metal 21 and the conductive contact holes 16, and the source region 24 is interconnected with the metal interconnection layer 19 through the source region contact metal 15 and the conductive contact holes 16.
Reference is made to fig. 1. In some embodiments, trench gates 28 are formed in gate trenches 25. A heavily doped N + type polysilicon gate 26 (poly 1) is provided in the gate trench 25, the top of the polysilicon gate 26 being ohmically connected to the bottom of the gate metal 21. A gate oxide layer 27 is provided between the inner wall of the gate trench 25 and the polysilicon gate 26, the polysilicon gate 26 being isolated from the source region 24 by the gate oxide layer 27.
In some embodiments, the bottom of trench gate 28 is located in drift region 11 through body region 12.
The top of the trench gate 28 may be disposed protruding from the surface of the semiconductor layer 23.
In some embodiments, the bottom of the source contact trench 14 is located in the body region 12, and the sidewalls of the source contact trench 14 meet the sides (end faces) of the source region 24. A transition connection 13 is also provided in the semiconductor layer 23 along the walls of the source contact trench 14, and the source contact metal 15 forms an ohmic connection with the source region 24 and the body region 12 also via the transition connection 13. The transition connection 13 may be a heavily doped p+ -type transition connection 13. The bottom of the transition connection 13 is located in the body region 12.
In some embodiments, a pair of first sidewalls 22 are located inward of both sides (both ends) of the source region 24, and the source region contact metal 15 is connected to the source region 24 by the top and the side of the source region 24 other than the pair of first sidewalls 22 at the same time to increase the contact area with the source region 24.
In some embodiments, the gate metal 21 material and/or the source contact metal 15 comprises at least one of Au, ag, pt, al, W.
An adhesion layer (not shown) may be provided between the gate metal 21 and the tops of the first side walls 22 and the trench gate 28, and between the source contact metal 15 and the first side walls 22 (including the tops of the source regions 24 other than the pair of first side walls 22) and the walls of the source contact trench 14, respectively. The bond coat material includes at least one of Ti, tiN, taN.
In some embodiments, the conductive contact hole 16 may be a tungsten contact hole.
Reference is made to fig. 1. In some embodiments, the source regions 24 and the source region contact trenches 14 are alternately connected along the surface of the semiconductor layer 23 in a plurality (2 source regions 24 and 3 source region contact trenches 14 are exemplarily shown in fig. 1). Wherein a pair of first sidewalls 22 are disposed on the surface of the semiconductor layer 23 above each source region 24, a gate metal 21 and a trench gate 28 are disposed between each pair of first sidewalls 22, and a source contact metal 15 is buried in and fills the source contact trench 14 from a gap between two adjacent pairs of first sidewalls 22.
It can be seen that each trench gate 28 is self-aligned through a pair of first sidewalls 22 formed over a source region 24 in a corresponding one of the source regions 24, and that the gate metal 21 fills between the pair of first sidewalls 22 and is self-aligned with the underlying trench gate 28 to form a buried gate metal 21. The source contact trenches 14 are self-aligned between two adjacent trench gates 28 by two adjacent pairs of first sidewalls 22, and each source contact trench 14 meets the sides of two source regions 24 on both sides simultaneously.
In some embodiments, a dielectric passivation layer 17 is provided on the metal interconnect layer 19, and a pad window 18 (for forming a pad) is provided on a surface of the passivation layer 17 to connect the metal interconnect layer 19.
A method for manufacturing a self-aligned buried gate metal MOSFET according to the present invention will be described in detail with reference to the accompanying drawings.
Reference is made to fig. 2-9. The method for manufacturing the self-aligned buried gate metal MOSFET of the present invention can be used for manufacturing the self-aligned buried gate metal MOSFET of the present invention such as that of FIG. 1, and can comprise the following steps:
Step S1, providing a substrate 10, and forming a semiconductor layer 23 on the surface of the substrate 10.
As shown in fig. 2, a heavily doped n+ type silicon substrate 10 (n+ substrate) may be employed, and an epitaxial silicon semiconductor layer 23 may be formed on the silicon substrate 10.
In step S2, a drift region 11 is formed in the semiconductor layer 23, and a body region 12 is formed below the surface of the semiconductor layer 23 and above the drift region 11.
As shown in fig. 2, the N-type epitaxial silicon semiconductor layer 23 may be formed using a doping process when the epitaxial silicon semiconductor layer 23 is formed. After forming the N-type epitaxial silicon semiconductor layer 23, a lightly doped P-body region 12 (P-body) may be formed below the surface of the semiconductor layer 23 using an ion implantation process. Thus, an epitaxial N-type drift region 11 (N DRIFT EPI) is formed in the N-type semiconductor layer 23 below the body region 12. In other words, the body region 12 is formed in the drift region 11 and is located below the surface of the semiconductor layer 23.
Step S3 is to form a source region 24 located in the body region 12 below the surface of the semiconductor layer 23.
As shown in fig. 2, a first hard mask layer material may be deposited on the surface of semiconductor layer 23. Then, a photoresist layer is formed on the first hard mask layer. Next, a plurality of first hard mask layer patterns 29 (HM 1) are formed on the surface of the semiconductor layer 23 by photolithography and etching. The formation of 2 first hard mask layer patterns 29 is exemplarily shown in fig. 2, but is not limited thereto. Thereafter, the photoresist remaining on the first hard mask layer pattern 29 is removed.
The first hard mask layer material may be a conventional hard mask layer material. For example, the first hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.
As shown in fig. 3, a conformal CVD process may be used to form a second hard mask layer over the surface of semiconductor layer 23, covering first hard mask layer pattern 29. Then, the second hard mask layer is etched back, one second hard mask layer pattern 30 (HM 2) is formed on each side of each first hard mask layer pattern 29, and the top of the first hard mask layer pattern 29 and the surface of the semiconductor layer 23 between the two second hard mask layer patterns 30 located on the adjacent sides (i.e., the two second hard mask layer patterns 30 located inside the two adjacent first hard mask layer patterns 29) are exposed.
When the second hard mask layer is deposited, the width of the third hard mask layer required to be deposited in the follow-up process can be reserved through thickness control during deposition.
The second hard mask layer material may be a conventional hard mask layer material. For example, the second hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.
As shown in fig. 3, a deposition process may be used to form a third hard mask layer on the surface of the semiconductor layer 23, cover the first hard mask layer pattern 29 and the second hard mask layer pattern 30, and completely fill the gap between the two second hard mask layer patterns 30 on the adjacent sides. Then, a third hard mask layer pattern 31 (HM 3) may be formed between two second hard mask layer patterns 30 located at adjacent sides by back-etching the third hard mask layer material, and the tops of the first hard mask layer pattern 29 and the second hard mask layer pattern 30 are exposed.
By conformally forming the second hard mask layer over the first hard mask layer pattern 29 and forming the second hard mask layer pattern 30 on both sides of the first hard mask layer pattern 29 by back etching, the third hard mask layer pattern 31 can be formed self-aligned between the second hard mask layer patterns 30, and pitch reduction is achieved while saving one mask.
The third hard mask layer material may be a conventional hard mask layer material. For example, the third hard mask layer material may be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and the like.
As shown in fig. 4, the second hard mask layer pattern 30 may then be removed using different etch selectivity between the second hard mask layer material and the first and third hard mask layer materials, exposing the surface of the semiconductor layer 23 between the first and third hard mask layer patterns 29 and 31, thereby forming a first implantation window 32 between the first and third hard mask layer patterns 29 and 31.
Then, a heavily doped n+ type source region 24 located in the body region 12 is formed below the surface of the semiconductor layer 23 under the first implantation window 32 through the first implantation window 32 and using a multi-directional ion implantation process. For example, by using an inclined implantation angle toward the periphery of the first implantation window 32, a heavily doped n+ type source region 24 located in the body region 12 below the surface of the semiconductor layer 23 below the first implantation window 32 and having a boundary larger than that of the first implantation window 32 may be formed. The formation of 2 source regions 24 is exemplarily shown in fig. 4, but is not limited thereto.
In step S4, a pair of first sidewalls 22 are formed on the surface of the semiconductor layer 23 over the source regions 24.
As shown in fig. 4, a sidewall process may be used to deposit a sidewall material on the first hard mask layer patterns 29, the third hard mask layer patterns 31, and the surface of the semiconductor layer 23 exposed between the patterns, and then back-etching is performed to form a first sidewall 22 (Spacer) structure on both sides of each first hard mask layer pattern 29 and on both sides of each third hard mask layer pattern 31. Wherein the first sidewalls 22 on two adjacent sides between the first hard mask layer pattern 29 and the third hard mask layer pattern 31 are simultaneously located on the surface of the semiconductor layer 23 above the same source region 24, a pair of first sidewalls 22 is formed.
In forming the first side walls 22, the horizontal width of the first side walls 22 formed by back etching can be adjusted by controlling the deposition thickness of the material of the first side walls 22, so as to adjust the spacing between the pair of first side walls 22, that is, the width of the surface of the semiconductor layer 23 exposed between the pair of first side walls 22, thereby adjusting the horizontal width of the gate trench 25 formed by the subsequent etching.
The first sidewall 22 material may be a conventional sidewall material having a different etch selectivity than the first hard mask layer material and the third hard mask layer material.
Step S5 of forming a trench gate 28 penetrating the source region 24 in the semiconductor layer 23 between the pair of first sidewalls 22.
As shown in fig. 5, next, with the first hard mask layer pattern 29 and the combination pattern of the first side walls 22 on both sides thereof and the third hard mask layer pattern 31 and the combination pattern of the first side walls 22 on both sides thereof as a common mask, etching is performed downward on the surface of the semiconductor layer 23 between the pair of first side walls 22, forming a gate trench 25 penetrating the source region 24 in the semiconductor layer 23. In fig. 5, 2 parallel gate trenches 25 are shown formed through the source region 24, and the bottom of the gate trench 25 is further etched through the body region 12 in the underlying drift region 11.
Then, the gate oxide layer 27 material is deposited entirely on the inner wall surface of the gate trench 25 and on the exposed surfaces of the first side walls 22 and the first and third hard mask layer patterns 29, 31, and further the gate 26 material is filled in the gate trench 25 within the gate oxide layer 27 material, so that the gap between the pair of first side walls 22 can be filled all the time, and the gate 26 material is covered on the gate oxide layer 27 material.
Next, a trench gate 28 may be formed by back-etching the gate 26 material and the gate oxide layer 27 material, forming a gate oxide layer 27 on the inner walls of the gate trench 25, and forming the gate 26 in the gate trench 25 within the gate oxide layer 27. The gate 26 may be formed as an n+ type polysilicon gate 26 (poly 1).
When the gate electrode 26 material and the gate oxide layer 27 material are etched back, the etching time can be controlled so that the top of the gate electrode 26 and the gate oxide layer 27 protrudes from the surface of the semiconductor layer 23 and is lower than the top of the first sidewall 22.
Step S6, forming a gate metal 21 buried between the pair of first sidewalls 22 and connecting the trench gate 28.
As shown in fig. 6, a first adhesive layer (not shown) may then be deposited on the exposed surfaces of the pair of first sidewalls 22 and the first and third hard mask layer patterns 29 and 31 by a deposition process. The first metal then continues to deposit on the first adhesion layer, filling the void between the pair of first sidewalls 22 and filling the void between the pair of first sidewalls 22 over the trench gate 28. Then, the first metal and the first adhesive layer are etched back or Chemical Mechanical Polishing (CMP) to remove the excessive first metal and the first adhesive layer on the top surfaces of the first sidewall 22 and the first hard mask layer pattern 29, the third hard mask layer pattern 31, thereby forming the gate metal 21 buried between the pair of first sidewalls 22 and connecting the trench gate 28.
The first metal (gate metal 21) includes at least one of Au, ag, pt, al, W.
The first bond coat material includes at least one of Ti, tiN, taN.
In step S7, a source contact trench 14 is formed in the semiconductor layer 23 on the side of the trench gate 28.
As shown in fig. 7, the first hard mask layer pattern 29 and the third hard mask layer pattern 31 are then removed by etching back, exposing the surface of the semiconductor layer 23 between the two first sidewalls 22 on the adjacent sides.
Then, a sidewall process may be used to further form a second sidewall 33 outside the pair of first sidewalls 22.
The second sidewall 33 material may be another sidewall material having a different etch selectivity than the first sidewall 22 material.
The gate metal 21 and the first side wall 22 and the second side wall 33 on two sides thereof are used as a common mask, the source region contact trench 14 is etched downwards on the surface of the semiconductor layer 23 exposed between the two second side walls 33 on two adjacent sides, the side wall of the formed source region contact trench 14 is connected with the side surface of the source region 24, and the bottom of the source region contact trench 14 is positioned in the body region 12 between the two adjacent source regions 24.
When the second side wall 33 is formed, the horizontal width of the second side wall 33 formed by back etching can be adjusted by controlling the deposition thickness of the second side wall 33 material, so as to adjust the interval between the two second side walls 33 on the adjacent sides, that is, adjust the width of the surface of the semiconductor layer 23 exposed between the two second side walls 33 on the adjacent sides, thereby realizing the adjustment of the horizontal width of the source region contact trench 14 formed by etching later.
After the source region contact trench 14 is formed, the transition connection portion 13 may be formed in the semiconductor layer 23 along the wall of the source region contact trench 14 by ion implantation using the space between the two second side walls 33 on the adjacent sides as the second implantation window 34. The source contact trench 14 region may be implanted using a P-type ion implantation, such as using ion implantation of boron and boron difluoride (BF 2), and a Rapid Thermal Anneal (RTA) may be performed to form a heavily doped P + type transition connection 13 (P + imp) in the body region 12 within a certain region of the semiconductor layer 23 along the wall of the source contact trench 14 to improve the dynamic reliability of the formed device.
Step S8 of forming source contact metal 15 filled in source contact trench 14 and connecting source 24.
As shown in fig. 8, the second side wall 33 may then be removed by etching back to expose the first side wall 22. Then, a second adhesion layer (not shown) may be deposited on the exposed surfaces of the two first sidewalls 22 and the gate metal 21 on the adjacent sides and the exposed surface of the semiconductor layer 23 (i.e., the exposed surfaces of the two sides of the source region 24 and the walls of the source region contact trench 14 after removing the second sidewall 33), and the second metal may be further deposited on the second adhesion layer to fill the gap between the two first sidewalls 22 on the adjacent sides and the gap between the two first sidewalls 22 on the adjacent sides above the source region contact trench 14. Then, the second metal and the second adhesive layer are etched back or Chemical Mechanical Polishing (CMP), and the excess second metal and the second adhesive layer on the top surfaces of the first sidewall 22 and the gate metal 21 are removed, exposing the tops of the first sidewall 22 and the gate metal 21, thereby forming the source contact metal 15 buried between the two first sidewalls 22 on the adjacent sides, and filled in the source contact trench 14 and connecting the source region 24 and the body region 12 through the transition connection portion 13.
In other embodiments, instead of forming the second sidewall 33, after removing the first hard mask layer pattern 29 and the third hard mask layer pattern 31 by back etching, the gate metal 21 and the first sidewalls 22 on both sides thereof are directly used as a common mask, and the source contact trench 14 is etched down on the surface of the semiconductor layer 23 exposed between the two first sidewalls 22 on the adjacent sides, so that the sidewalls of the source contact trench 14 are connected to the source region 24, and the bottom of the source contact trench 14 is located in the body region 12. Thereafter, a heavily doped p+ type transition connection 13 may be formed and a source contact metal 15 buried between two first sidewalls 22 on adjacent sides and filled in the source contact trench 14 and connecting the source 24 and the body 12 through the transition connection 13, using the aforementioned method. In this method, the dimensions of the first hard mask layer pattern 29 and the third hard mask layer pattern 31 need to be controlled separately, so that the process requirements are strict.
In step S9, an interlayer dielectric layer 20 is formed on the first sidewall 22, the gate metal 21 and the top surface of the source contact metal 15.
As shown in fig. 8, an interlayer dielectric layer 20 (ILD) may then be formed on the top surfaces of the first sidewall 22, the gate metal 21, and the source contact metal 15 by a deposition process. The interlayer dielectric layer 20 may be made of a conventional interlayer dielectric material.
In step S10, conductive contact holes 16 with bottoms respectively connected to the gate metal 21 and the source contact metal 15 are formed in the interlayer dielectric layer 20.
As shown in fig. 9, next, a contact hole may be formed in the interlayer dielectric layer 20 by photolithography and etching processes, and the bottom of the contact hole is located on top surfaces of the gate metal 21 and the source contact metal 15, respectively. Then, by performing a planarization process of filling the contact hole metal and removing the excess contact hole metal, conductive contact holes 16 having bottoms connected to the gate metal 21 and the source contact metal 15, respectively, are formed in the interlayer dielectric layer 20. For example, the tungsten conductive contact hole 16 may be formed by tungsten filling and planarizing the contact hole.
In step S11, a metal interconnection layer 19 connected to the top of the conductive contact hole 16 is formed on the interlayer dielectric layer 20.
As shown in fig. 9, a metal interconnection layer 19 connected to the top of the conductive contact hole 16 may then be formed on the surface of the interlayer dielectric layer 20 through an interconnection process.
Finally, a dielectric Passivation layer 17 (Passivation) may be formed on the metal interconnection layer 19 through a deposition process, and a pad window 18 connecting the metal interconnection layer 19 may be formed on the surface of the Passivation layer 17 through a photolithography and etching process, and the pad window 18 may be pad metal filled and planarized to form a pad (not shown).
In summary, the gate metal 21 connected to the trench gate 28 is formed on the trench gate 28, so that the gate 26 (for example, the polysilicon gate 26) in the trench gate 28 is connected to the conductive contact hole 16 through the gate metal 21, so that the voltage conducted by the conductive contact hole 16 is reliably conducted to the trench gate 28 through the gate metal 21, thereby effectively reducing the contact resistance between the trench gate 28 (polysilicon gate 26) and the conductive contact hole 16, improving the reliability of the voltage conduction between the conductive contact hole 16 and the trench gate 28, and accelerating the conduction speed, namely, increasing the switching frequency, so that the problem that the conduction speed is easily reduced, namely, the switching frequency is reduced when the conventional direct connection mode of the tungsten contact hole and the polysilicon gate in the trench gate is adopted to conduct the voltage is effectively solved. Also, by forming a pair of first sidewalls 22 over the source region 24 in a self-aligned manner, a trench gate 28 self-aligned to the source region 24 may be formed in the semiconductor layer 23 between the pair of first sidewalls 22, and a source contact trench 14 and a source contact metal 15 self-aligned to the trench gate 28 may be formed on one side of the pair of first sidewalls 22 (trench gate 28), thereby not only reducing the mask, but also reducing the pitch between the structures in the MOSFET device, allowing the MOSFET device to have a smaller die area, allowing further reduction in resistance per square area, and increasing current density, and also eliminating the overlay error, thereby effectively reducing the short circuit resistance. Further, the second side wall 33 may be formed on the outer side of the first side wall 22 to adjust the size of the source region contact trench 14 (including the implantation size of the transition connection portion 13), so that not only the size of the source region 24 located between the source region contact trench 14 and the trench gate 28 may be adjusted, but also the filled source region contact metal 15 may be connected to the source region 24 from the top and the side of the source region 24 after the second side wall 33 is removed, thereby increasing the contact area, so as to meet the requirements of good ohmic contact and current carrying capability of the source region, and further improving the device performance.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
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