CN119274493A - Display device and control method - Google Patents

Abstract

The embodiment of the present application provides a display device and a control method. A plurality of pixel driving circuits are provided on a display panel of the display device. The fourth transistor in the pixel driving circuit is removed, and its ability to provide a second power supply signal to a first capacitor is replaced by a conduction loop composed of a seventh transistor and a third transistor, so that the second power supply signal can still be used to reset the first capacitor in the pixel driving circuit. When the first capacitor provides driving data after threshold voltage compensation to the first transistor, only the leakage current of the third transistor affects the data stored in the first capacitor, thereby reducing the leakage path and the influence of the leakage current on the data stored in the first capacitor, which is beneficial to improving the stability of the driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor.

Description

Display device and control method

Technical Field

The embodiment of the application relates to the technical field of display, in particular to a display device and a control method.

Background

In recent years, display panels constructed based on organic light emitting diodes or micro diodes have the characteristics of light weight, power saving and self-luminescence, and are becoming a hot spot for research in the display field.

The display panel is internally provided with a plurality of pixel circuits which are arranged in an array mode, and the light-emitting element in each pixel circuit is driven to emit light through one pixel driving circuit. The pixel driving circuit comprises a reset stage, a data writing stage and a display driving stage in the operation process of a display period, and when the driving transistor in the pixel driving circuit generates a driving signal according to the threshold value-compensated driving data stored in the grid electrode of the driving transistor in the display driving stage, the transistor electrically connected with the grid electrode of the driving transistor can generate leakage current, so that the stability of the current value of the driving signal generated by the driving transistor is affected.

Therefore, how to maintain the stability of the driving current has become an important point of research.

Disclosure of Invention

The application provides a display device and a control method, which are used for solving the technical problem that a pixel driving circuit is affected by leakage current and the current value of a generated driving signal is unstable.

In a first aspect, an embodiment of the present application provides a display apparatus, including:

a display panel provided with a power line, a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixel circuits;

Each of the sub-pixel circuits includes a pixel driving circuit and a light emitting element;

the pixel driving circuit includes:

A seventh transistor having a first terminal electrically connected to the power line, a control terminal electrically connected to the gate line, configured to acquire a first scan signal and a second power signal, the first scan signal controlling a conductive state thereof, and outputting the second power signal from a second terminal thereof when the first scan signal is conductive;

A sixth transistor having a first terminal electrically connected to the second terminal of the seventh transistor, a control terminal electrically connected to the gate line, a second terminal electrically connected to the first terminal of the light emitting element, configured to acquire a second light emission control signal and the second power supply signal, control a turn-on state thereof by the second light emission control signal, output the second power supply signal from the second terminal thereof when turned on, and reset the first terminal of the light emitting element;

A third transistor having a first terminal electrically connected to the second terminal of the seventh transistor, a control terminal electrically connected to the gate line, configured to acquire a second scan signal and the second power signal, to control a turn-on state thereof by the second scan signal, and to output the second power signal from the second terminal thereof when turned on;

a first capacitor having a first terminal electrically connected to the second terminal of the third transistor and configured to reset the first terminal thereof with the second power signal.

In the above technical solution, the pixel driving circuit transmits the second power signal to the light emitting element through the loop formed by the seventh transistor and the sixth transistor, resets the light emitting element, maintains the reset function of the seventh transistor on the light emitting element, and simultaneously transmits the second power signal to the first capacitor through the loop formed by the seventh transistor and the third transistor, resets the first capacitor, so as to replace the function of the fourth transistor in the traditional pixel driving circuit, and when the first capacitor provides the driving data after the threshold voltage compensation for the first transistor, only the leakage current of the third transistor affects the data stored in the first capacitor, thereby reducing the leakage path, reducing the influence of the leakage current on the data stored in the first capacitor, and being beneficial to improving the stability of the driving current generated by the first transistor in the driving signal based on the data stored in the first capacitor.

In one possible embodiment, a display period includes a reset phase, a data writing phase, and a display phase in this order;

The reset phase comprises a reset sub-phase;

in the resetting sub-stage, the first scanning signal, the second scanning signal and the second light-emitting control signal are of a first level, and the third scanning signal and the first light-emitting control signal are of a second level;

The seventh transistor is turned on according to the first light emitting control signal, and transmits a second power signal obtained from a first terminal thereof to the first terminal of the sixth transistor and the first terminal of the third transistor;

The sixth transistor is conducted according to the second light-emitting control signal, and transmits a second power signal obtained from the first end of the sixth transistor to the first end of the light-emitting element;

the third transistor is conducted according to the second scanning signal, and transmits a second power signal obtained from the first end of the third transistor to the first capacitor;

the first capacitor resets the first end of the first capacitor by using the second power supply signal;

The light emitting element resets its first end according to the second power signal.

In the above technical solution, in the reset sub-stage, the loop formed by the seventh transistor and the third transistor between the first end of the first capacitor and the power line is turned on by the first scan signal and the second scan signal, the first capacitor can still acquire the second power signal from the power line according to the loop to perform the reset operation without using the fourth transistor for providing the second power signal to the fourth transistor in the original pixel driving circuit, so that the first transistor is turned on according to the second power signal after the reset stage, generates the driving data compensated by the threshold voltage by using the driving data, and generates the driving signal according to the driving data.

In addition, since the number of transistors electrically connected with the first end of the first capacitor is reduced, when the first capacitor drives the first transistor to generate a driving signal, the first end of the first capacitor reduces a leakage path due to the elimination of the fourth transistor, so that the stability of the voltage value of the first end of the first capacitor is improved, the stability of the current value of the driving signal generated according to the potential value of the first end of the first capacitor is improved, and the phenomenon of the display panel based on the luminous element is relieved.

In a second aspect, the present application provides a control method of a display device, for the display device as claimed in the first aspect, the method comprising:

Controlling the seventh transistor and the third transistor to be conducted in the same period of time, so that the seventh transistor and the third transistor transmit a second power supply signal to the first capacitor, and resetting the first end of the first capacitor;

and controlling the seventh transistor and the sixth transistor to be conducted in the same period, so that the seventh transistor and the sixth transistor transmit the second power supply signal to the light-emitting element, and resetting the first end of the light-emitting element.

In the above technical solution, the seventh transistor and the third transistor are controlled to be turned on simultaneously, so that the second power signal is used as a reset signal to reset the first capacitor, instead of controlling the process of turning on the fourth transistor electrically connected to the power line and the first capacitor to reset the first capacitor, the fourth transistor can be simplified in the original pixel driving circuit, the leakage path of the first capacitor is reduced, the influence of leakage current on the data stored in the first capacitor is reduced, and the stability of driving current in the driving signal generated by the first transistor based on the data stored in the first capacitor is improved.

The embodiment of the application provides a display device and a control method, wherein the display device comprises a display panel, a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged on the display panel, each sub-pixel circuit comprises a pixel driving circuit and a light emitting element, the pixel driving circuit comprises a seventh transistor, a sixth transistor, a third transistor and a first capacitor, the first end of the seventh transistor is electrically connected with the power line, the second end of the second transistor is electrically connected with the first end of the third transistor, the second end of the third transistor is electrically connected with the first end of the first capacitor, the first end of the seventh transistor acquires a second power signal from the power line, and when the seventh transistor and the third transistor are all conducted, the second power signal is transmitted to the first capacitor, the first end of the first capacitor is reset, a single transistor connected between the power line and the first capacitor is not required to be arranged in the pixel driving circuit, when the first capacitor provides driving data subjected to threshold voltage compensation, only leakage current affecting the first capacitor is reduced, and leakage current affecting in the first capacitor is reduced, and the driving data is generated, and the storage stability of the driving signal is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural view of a display device according to an exemplary embodiment of the present application;

fig. 2 is a schematic structural view of a display device according to another exemplary embodiment of the present application;

Fig. 3 is a schematic diagram of a conventional pixel driving circuit according to an exemplary embodiment of the present application;

Fig. 4 is a schematic diagram of a P-type pixel driving circuit according to an exemplary embodiment of the present application;

FIG. 5 is a timing diagram of driving signals of a P-type pixel driving circuit according to an exemplary embodiment of the present application;

Fig. 6 is a timing diagram of driving signals of a P-type pixel driving circuit according to another exemplary embodiment of the present application;

Fig. 7 is a timing diagram of driving signals of a P-type pixel driving circuit according to another exemplary embodiment of the present application;

Fig. 8 is a timing diagram of driving signals of a P-type pixel driving circuit according to another exemplary embodiment of the present application;

Fig. 9 is a schematic diagram of a scan signal generating circuit according to an exemplary embodiment of the present application;

FIG. 10 is a timing diagram of input/output signals of a scan signal generation circuit according to an exemplary embodiment of the present application;

fig. 11 is an input-output signal timing diagram of a scan signal generating circuit according to another exemplary embodiment of the present application;

Fig. 12 is a schematic diagram of a structure of a light emission control signal generation circuit according to an exemplary embodiment of the present application;

Fig. 13 is an input/output signal timing diagram of a light emission control signal generation circuit according to an exemplary embodiment of the present application.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element(s) defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other like elements in different embodiments of the application having the same meaning as may be defined by the same meaning as they are explained in this particular embodiment or by further reference to the context of this particular embodiment. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups.

In the description of the present disclosure, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The terms "or" and/or "are to be construed as inclusive, or mean any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of A, B, C, A and B, A and C, B and C, A, B and C". An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In recent years, display panels constructed based on organic light emitting diodes or micro diodes have the characteristics of light weight, power saving and self-luminescence, and are becoming a hot spot for research in the display field.

As shown in fig. 1, the display device includes a control circuit 10, a data driving circuit 20, a gate driving circuit 30, a display panel 40, and a power supply circuit 70. The control circuit 10 and the data driving circuit 20, the control circuit 10 and the gate driving circuit 30 are electrically connected, and the display panel 40 and the data driving circuit 20, the gate driving circuit 30 and the power supply circuit 70 are electrically connected.

The display panel 40 includes a display area AA in which a plurality of pixel units 80 are disposed and a non-display area NA outside the display area. In the display area AA, a power line 90, a plurality of gate lines 60, and a plurality of data lines 50 are provided, and a plurality of pixel units 80 are distributed in an array in the display area AA, each pixel unit 80 being located at an area where the gate line 60 and the data line 50 intersect.

The gate driving circuit 30 is electrically connected to the gate lines 60, and the gate driving circuit 30 is configured to obtain a clock signal and a trigger signal from the control circuit 10, generate a gate driving signal according to the clock signal and the trigger signal, and transmit the gate driving signal to the corresponding pixel unit 80 through the gate lines 60 to control the on or off of the transistors in the pixel unit 80.

More specifically, the Gate driving Circuit 30 may be manufactured as a separate Gate driver integrated Circuit (GATE DRIVER INTEGRATED Circuit, abbreviated as GDIC), and the Gate driving Circuit 30 may also be integrated within the display Panel, and the manner in which the Gate driving Circuit 30 is integrated within the display Panel is referred to as Gate-in-Panel (GIP). In some cases, the GDIC may be electrically connected to the display panel 40 through a COG process (Chip on Glass), and the GDIC may be electrically connected to the display panel 40 through a COF process (Chip on Film). In the COF process, the element is electrically connected to the display panel 40 through a flexible circuit board (Flexible Printed Circuit, abbreviated as FPC).

The data driving circuit 20 is a circuit that drives the data lines 50, and is configured to acquire display data from the control circuit 10, convert it into analog data voltages (Vdata) that are transmitted to the corresponding pixel units 80 through the data lines 50, so that the light emitting elements 813 in the pixel units 80 emit light according to the analog data voltages. The magnitude of the analog data voltage determines the light emission luminance of the light emitting element 813.

The data driving Circuit 20 may include one or more Source driver integrated circuits (Source DRIVER INTEGRATED Circuit, abbreviated as SDIC). Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

The power supply circuit 70 is a circuit that supplies a stable electric signal, and is configured to supply a corresponding required power supply signal to the display panel 40, the control circuit 10, the data driving circuit 20, and the gate driving circuit 30.

In one case, each pixel unit 80 includes three pixel circuits 810 for displaying red light, blue light, and green light, respectively. In another case, four pixel circuits 810 are included in each pixel unit 80 for displaying red light, blue light, green light, and white light, respectively. The present invention is not particularly limited herein.

The emission color of each pixel unit 80 is determined by the property of the light emitting element 813 therein. The light emitting element 813 can be any device capable of emitting light including, but not limited to, an OLED, a micro LED.

The micro LED is a micro light emitter manufactured using an inorganic semiconductor layer. The micro LED may generally include a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The structure of such a micro LED may be various, such as a vertical type, a horizontal type, a flip chip type, etc., and is not particularly limited to a specific structure.

More specifically, as shown in fig. 2, one pixel circuit 810 includes a pixel driving circuit 814 and a light emitting element 813, the pixel driving circuit 814 is electrically connected to the light emitting element 813, and the pixel driving circuit 814 is configured to drive the light emitting element 813 to emit light. The signals required for the pixel driving circuit 814 include a driving signal, a Scan signal (Scan), and a light Emission control signal (Emission, abbreviated as an EM control signal).

The drive signal may be generated by the control circuit 10 or may be externally obtained. Including but not limited to a start pulse signal, a clock signal, and an enable signal. The light emission control signal may be a global signal supplied from the control circuit 10 or a signal generated by the gate driving circuit 30, and is not particularly limited here. The scanning signal is a successive shift signal generated by the gate driving circuit 30.

If the EM control signal is a global signal generated by the control circuit 10, the gate driving circuit 30 acquires the EM control signal from the control circuit 10 and transmits the EM control signal to the corresponding pixel driving circuit 814 through the gate line 60.

If both the EM control signal and the scanning signal are generated by the gate driving circuit 30, the gate driving circuit 30 includes a scanning signal generating circuit 301 and an EM control signal generating circuit 302. The scanning signal is output from the scanning signal generating circuit 301, and the EM control signal is output from the EM control signal generating circuit 302.

Fig. 3 is a schematic structural diagram of a conventional pixel driving circuit according to an exemplary embodiment of the present application, and as shown in fig. 3, the conventional pixel driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first capacitor C1.

The fourth transistor M4 has a first terminal electrically connected to the power line 90, a control terminal electrically connected to the gate line 60, and is configured to have a control terminal acquiring the first scan signal S1 from the gate line 60, a first terminal acquiring the second power signal Vref from the power line 90, and an on state when the first scan signal S1 is at a low level, and an output of the second power signal Vref from a second terminal.

The first terminal of the first capacitor C1 is electrically connected to the second terminal of the fourth transistor M4, and is configured to obtain the second power signal Vref from the fourth transistor M4, and reset the first terminal thereof with the second power signal Vref.

The second transistor M2 has a first terminal electrically connected to the data line 50, a control terminal electrically connected to the gate line 60, and is configured to have a control terminal acquiring the second scan signal S2 from the gate line 60, a first terminal acquiring the driving data Vdata from the data line 50, and an on state when the second scan signal S2 is at a low level, and an output of the driving data Vdata from a second terminal.

The third transistor M3 has a first terminal electrically connected to the second terminal of the first transistor M1, a second terminal electrically connected to the control terminal of the first transistor M1, a control terminal electrically connected to the gate line 60, and a control terminal configured to obtain the second scan signal S2 from the gate line 60, and turn on when the second scan signal S2 is at a low level, shorting the second terminal of the first transistor M1 to the control terminal.

The first terminal of the first transistor M1 is electrically connected to the second terminal of the second transistor M2, the second terminal thereof is electrically connected to the first terminal of the third transistor M3, the control terminal thereof is electrically connected to the first terminal of the first capacitor C1, and the control terminal thereof is configured to obtain the second power signal Vref from the first capacitor C1, in this embodiment, the first transistor M1 is a p-type transistor, and the second power signal Vref is at a low level.

The first transistor M1 is turned on according to the second power signal Vref, and obtains the driving data for threshold voltage compensation from the control terminal thereof according to the driving data Vdata and the threshold voltage obtained from the first terminal thereof when the second terminal and the control terminal are short-circuited.

The first capacitor C1 is further configured to obtain and store the driving data after the threshold voltage compensation from the control terminal of the first transistor M1.

The fifth transistor M5 has a first terminal electrically connected to the power line 90, a second terminal electrically connected to the first terminal of the first transistor M1, a control terminal electrically connected to the gate line 60, and configured to have a control terminal receiving the light emission control signal EM from the gate line 60, a first terminal receiving the first power signal VDD from the power line 90, and turned on when the light emission control signal EM is at a low level, and a second terminal outputting the first power signal VDD.

The first transistor M1 is further configured such that when the third transistor M3 is turned off, the second terminal and the control terminal thereof are turned off, the control terminal thereof obtains the threshold voltage compensated driving data from the first capacitor C1, the first terminal thereof obtains the first power supply signal VDD, and the driving signal is generated according to the threshold voltage compensated driving data and the first power supply signal VDD, wherein the driving current value in the driving signal is determined by the first transistor M1 according to the threshold voltage, the first power supply signal VDD, and the threshold voltage compensated driving data.

In the process of generating the driving signal by the first transistor M1, the fourth transistor M4 and the third transistor M3 are turned off to generate a leakage current, which affects the charge stored in the first capacitor C1, thereby affecting the stability of the driving data after the threshold voltage compensation stored in the first terminal of the first capacitor C1, and thus affecting the stability of the driving current in the driving signal generated according to the driving data after the threshold voltage compensation.

In order to solve the problems, the present application provides a display device and a control method. The application has the technical conception that in the display device, the fourth transistor in the pixel driving circuit is removed, the capacity of providing the second power supply signal for the first capacitor is replaced by a conduction loop formed by the seventh transistor and the third transistor, so that the first capacitor can still be reset by using the second power supply signal in the pixel driving circuit, when the first capacitor provides the driving data subjected to threshold voltage compensation for the first transistor, only the leakage current of the third transistor influences the data stored in the first capacitor, the leakage path is reduced, the influence of the leakage current on the data stored in the first capacitor is reduced, the stability of the driving current generated by the first transistor in the driving signal based on the data stored in the first capacitor is improved, meanwhile, the number of devices in the pixel driving circuit is reduced, the space for arranging each pixel driving circuit is reduced, the pixel density of the display panel constructed based on the pixel driving circuit is increased, and the display device is improved for displaying the details of the display picture.

The specific circuit configuration of the pixel driving circuit provided by the present application is explained below.

Fig. 4 is a circuit configuration diagram of a pixel driving circuit according to an exemplary embodiment of the present application, and as shown in fig. 4, includes a first transistor M1, a second transistor M2, a third transistor M3, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first capacitor C1. The transistors referred to in fig. 4 are all P-type transistors.

The second transistor M2 has a first terminal electrically connected to the data line 50, a control terminal electrically connected to the gate line 60, and configured to have a first terminal acquiring the driving data Vdata from the data line 50, a control terminal acquiring the third scan signal S3 from the gate line 60, and controlling a conductive state thereof according to the third scan signal S3.

The second transistor M2 is configured to be turned on when the third scan signal S3 is at a low level, transmit the driving data Vdata obtained at the first end thereof to the second end, so that the S point obtains the driving data Vdata, and turn off when the third scan signal S3 is at a high level, and stop transmission of the electrical signal.

The first terminal of the third transistor M3 and the second terminal of the first transistor M1 are electrically connected to the point D, the second terminal thereof is electrically connected to the control terminal of the first transistor M1, the control terminal thereof is electrically connected to the gate line 60, and the control terminal thereof is configured to obtain the second scan signal S2 from the gate line 60 and control the conductive state thereof according to the second scan signal S2.

The third transistor M3 is configured to be turned on when the second scan signal S2 is at a low level, short-circuit the second terminal and the control terminal of the first transistor M1 and transmit an electric signal obtained from the first terminal thereof to the second terminal thereof, and turned off when the second scan signal S2 is at a high level, turn off the second terminal and the control terminal of the first transistor M1 and stop the transmission of the electric signal between the first terminal and the second terminal thereof.

A first terminal of the fifth transistor M5 is electrically connected to the power line 90, and a control terminal is electrically connected to the gate line 50, and is configured such that the first terminal thereof acquires the first power signal VDD from the power line 90, and the control terminal thereof acquires the first light emission control signal EM1 from the gate line 50, and controls the conductive state thereof according to the first light emission control signal EM 1. In the present embodiment, the first power supply signal VDD is at a high level.

The fifth transistor M5 is configured to be turned on when the first light emitting control signal EM1 is at a low level, transmit the first power signal VDD obtained at the first terminal thereof to the second terminal so that the S point obtains the first power signal VDD, and turn off when the first light emitting control signal EM1 is at a high level, stop transmission of the electrical signal.

The second terminal of the first capacitor C1 is electrically connected to the power line 90, and the first terminal thereof is electrically connected to the control terminal of the first transistor M1 through the point G, and is configured to store the electric signal obtained from the first terminal thereof and to maintain the electric potential value of the first terminal until the first terminal thereof obtains a new electric signal.

The first end and the S point of the first transistor M1 are electrically connected, and are configured to determine the driving data Vdata compensated by the threshold voltage of the first transistor M1 from the control end thereof when the first end and the second end are in short circuit and the first end thereof obtains the driving data Vdata from the S point, and store the driving data Vdata compensated by the threshold voltage in the first end of the first capacitor C1, and to obtain the driving data Vdata compensated by the threshold voltage from the second end of the first capacitor C1 through the G point when the first end and the second end thereof are in short circuit and the first end thereof obtains the first power signal VDD from the S point, generate the driving signal according to the electric signals obtained by the control end and the first end thereof and output the driving signal from the second end thereof.

The seventh transistor M7 has a first terminal electrically connected to the power line 90, a control terminal electrically connected to the gate line 60, and a second terminal electrically connected to the point D, and is configured to have a first terminal receiving the second power signal Vref from the power line 90, a first scan signal S1 from the gate line 60, and a conductive state thereof controlled according to the first scan signal S1.

The seventh transistor M7 is configured to be turned on when the first scan signal S1 is at a low level, output the second power signal Vref obtained at the first terminal thereof from the second terminal thereof to the point D, and turned off when the first scan signal S1 is at a high level, stopping the transmission of the electric signal.

The first terminal of the sixth transistor M6 is electrically connected to the second terminal of the first transistor M1 and the second terminal of the seventh transistor M7 through the point D, the second terminal thereof is electrically connected to the first terminal of the light emitting element LED, the control terminal thereof is electrically connected to the gate line 60, and the control terminal thereof is configured to obtain the second light emission control signal EM2 from the gate line 60, and to control the on state thereof according to the second light emission control signal EM 2.

The sixth transistor M6 is configured to be turned on when the second light emission control signal EM2 is at a low level, to transmit the second power signal Vref, the first terminal of which is obtained from the second terminal of the seventh transistor M7, to the second terminal thereof, or to transmit the driving signal, the first terminal of which is obtained from the second terminal of the first transistor M1.

The light emitting element LED is configured to obtain a driving signal from a first end thereof, emit light according to the driving signal, or obtain a second power signal Vref from a first end thereof, and reset according to the second power signal Vref.

When the control system comprising the controller, the gate driving circuit, the data driving circuit and the power circuit is used for controlling the pixel driving circuit, the seventh transistor M7 and the third transistor M3 need to be controlled to be turned on in the same period, so that the seventh transistor M7 and the third transistor M3 transmit the second power signal Vref to the first capacitor C1, and the first end of the first capacitor C1 is reset.

The seventh transistor M7 and the sixth transistor M6 are controlled to be turned on in the same period, so that the seventh transistor M7 and the sixth transistor M6 transmit the second power signal Vref to the light emitting element LED, resetting the first terminal of the light emitting element LED.

After the first capacitor C1 is reset, the third transistor M3 and the second transistor M2 are controlled to be turned on in the same period, and the second transistor M2 transmits the driving data, so that the first capacitor C1 stores the driving data Vdata after the threshold voltage compensation of the first transistor M1 determined by the control end of the first transistor M1.

After the first capacitor C1 stores the driving data Vdata after the threshold voltage compensation of the first transistor M1, the fifth transistor M5 and the sixth transistor M6 are controlled to be turned on in the same period and the fifth transistor M5 transmits the first power signal VDD, so that the first transistor M1 generates a driving signal by using the driving data Vdata after the threshold voltage compensation of the first transistor M1 and the first power signal VDD stored in the first capacitor C1, and drives the light emitting element LED to emit light.

Next, a circuit configuration for generating each of the scanning signals and the light emission control signals will be explained, respectively, in accordance with a plurality of drive signal timing charts of the pixel drive circuits.

Fig. 5 is a timing chart of driving signals for driving the pixel driving circuit shown in fig. 4 according to an exemplary embodiment of the present application.

The operation of the pixel driving circuit is explained below.

A display period T includes a reset phase T1, a data writing phase T2 and a display phase T3.

The reset phase t1 is divided into four periods, namely a t11 period, a t12 period, a t13 period and a t14 period.

In the periods t11 and t12 in the driving signal timing chart, the first scan signal S1, the second scan signal S2, the third scan signal S3, and the first emission control signal EM1 are at high level, and the second emission control signal EM2 is at low level.

Since the second emission control signal EM2 is low, the sixth transistor M6 is turned on, but since the first terminal of the sixth transistor M6 does not obtain an electrical signal, the sixth transistor M6 does not transmit an electrical signal, and the light emitting element LED does not receive an electrical signal.

In a period t13 in the driving signal timing chart, the first scan signal S1, the second scan signal S2, and the second emission control signal EM2 are low, and the third scan signal S3 and the first emission control signal EM1 are high.

Since the first scan signal S1 is at a low level, the seventh transistor M7 is turned on to transmit the second power signal Vref obtained at the first terminal thereof to the point D.

Since the second light emission control signal EM2 is at a low level, the sixth transistor M6 is turned on, and transmits the second power signal Vref, which is obtained from the point D at the first end thereof, to the first end of the light emitting element LED, which is an input end in this embodiment.

The first end of the light emitting element LED is reset according to the second power signal Vref.

Since the second scan signal S2 is at a low level, the third transistor M3 is turned on to transmit the second power signal Vref obtained at the first terminal thereof to the first terminal of the first capacitor C1.

The first end of the first capacitor C1 stores the second power signal Vref.

The data writing phase t2 is divided into three periods, namely a t21 period, a t22 period and a t23 period.

In a period t21 in the driving signal timing chart, the first scan signal S1, the first emission control signal EM1, and the second emission control signal EM2 are at high level, and the second scan signal S2 and the third scan signal S3 are at low level.

Since the first scan signal S1 is at a high level, the seventh transistor M7 is turned off, stopping the transmission of the second power signal Vref.

Since the second light emission control signal EM2 is at a high level, the sixth transistor M6 is turned off, stopping transmitting the electric signal.

Since the first light emitting control signal EM1 is at a high level, the fifth transistor M5 is turned off, and the first power signal VDD cannot be transmitted to the first terminal of the first transistor M1.

Since the second scan signal S2 is low, the third transistor M3 is turned on, shorting the second terminal and the control terminal of the first transistor M1.

Since the third scan signal S3 is at a low level, the second transistor M2 is turned on to transmit the driving data Vdata obtained at the first terminal thereof to the first terminal of the first transistor M1.

Since the first end of the first capacitor C1 stores the second power signal Vref, and the second power signal Vref is at a low level, the control end of the first transistor M1 obtains the second power signal Vref from the first end of the first capacitor C1, and is turned on according to the second power signal Vref, and obtains the driving data Vdata compensated by the threshold voltage Vth1 from the control end according to the driving data Vdata obtained from the first end thereof, and the compensated data is vdata+vth1.

The first end of the first capacitor C1 obtains the compensated driving data vdata+vth1 from the control end of the first transistor M1, and stores the data.

In the periods t22 and t23 in the driving signal timing chart, the first scan signal S1, the second scan signal S2, the third scan signal S3, the first light emission control signal EM1, and the second light emission control signal EM2 are all at high level.

Since each signal is high, each transistor is turned off and does not transmit an electrical signal.

The light emitting element LED does not acquire a driving signal in this period and does not emit light.

The display period t3 is divided into eight periods, t31 to t 38.

In the period from t31 to t33 in the driving signal timing chart, the first scan signal S1, the second scan signal S2, the third scan signal S3, and the second emission control signal EM2 are at high level, and the first emission control signal EM1 is at low level.

Since the first light emitting control signal EM1 is at a low level, the fifth transistor M5 is turned on to transmit the first power signal VDD obtained at the first terminal thereof to the first terminal of the first transistor M1.

Since the third scan signal S3 is at a high level, the second transistor M2 is turned off, the driving data Vdata is not transmitted, and the potential value of the first terminal of the first transistor M1 is not affected by the driving data Vdata.

Since the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the control terminal and the second terminal of the first transistor M1 are turned off.

The control terminal of the first transistor M1 obtains the compensated data vdata+vth1 from the first terminal of the first capacitor C1, and is turned on according to the data.

The first transistor M1 outputs a driving signal having a current value of k|vdata+vth1-VDD-Vth 1|=k|vdata-vdd| from its second terminal according to the electric signal obtained at its control terminal and the electric signal obtained at its first terminal, the driving signal having a current value independent of the threshold voltage.

Since the first scan signal S1 is at a high level, the seventh transistor M7 is turned off, the second power signal Vref is not transmitted, and the electrical signal generated at the point D is not affected by the second power signal Vref.

Since the second emission control signal EM2 is at a high level, the sixth transistor M6 is turned off and cannot transmit the driving signal obtained at the first terminal thereof to the first terminal of the light emitting element LED.

Since the light emitting element LED does not acquire a driving signal, the light emitting element LED does not emit light.

In the period t34 to t38 in the driving signal timing chart, the first scan signal S1, the second scan signal S2, and the third scan signal S3 are at high level, and the first light emission control signal EM1 and the second light emission control signal EM2 are at low level.

Since the level states of the first scan signal S1, the second scan signal S2, the third scan signal S3, and the first light emitting control signal EM1 and the level states in the period T31 to T33 remain unchanged, the states of the seventh transistor M7, the third transistor M3, the fifth transistor M5, the second transistor M2, and the first transistor M1 remain unchanged.

Since the second emission control signal EM2 is at a low level, the sixth transistor M6 is turned on, and transmits the driving signal obtained at the first terminal thereof to the first terminal of the light emitting element LED.

The light emitting element LED emits light according to the drive signal obtained from the first end thereof.

In the above technical solution, in the reset stage, the loop formed by the seventh transistor and the sixth transistor between the light emitting element and the power line, where the first scan signal and the second light emitting control signal EM2 are used to ensure that the light emitting element can be reset, and meanwhile, the loop formed by the seventh transistor and the third transistor between the first end of the first capacitor and the power line is made to be conductive by the first scan signal and the second scan signal, so that the first capacitor does not need to use the fourth transistor in the original pixel driving circuit for providing the second power signal thereto, and still can obtain the second power signal from the power line according to the loop to perform the reset operation, so that after the reset stage, the first transistor is made to be conductive according to the second power signal, the driving data of threshold voltage compensation is generated by using the driving data, and the driving signal is generated according to the driving data.

In addition, since the number of transistors electrically connected with the first end of the first capacitor is reduced, when the first capacitor drives the first transistor to generate a driving signal, the first end of the first capacitor reduces a leakage path due to the elimination of the fourth transistor, so that the stability of the voltage value of the first end of the first capacitor is improved, the stability of the current value of the driving signal generated according to the potential value of the first end of the first capacitor is improved, and the phenomenon of the display panel based on the luminous element is relieved.

Fig. 6 is a timing chart of driving signals according to another exemplary embodiment of the present application, where the driving signal timing chart is different from that of fig. 5 only in the period t11, and the signal status remains unchanged in other periods.

The signal state and the operation of the pixel driving circuit in the period t11 are explained below.

In a period t11 in the driving signal timing chart, the first scan signal S1 and the second emission control signal EM2 are at low level, and the second scan signal S2, the third scan signal S3 and the first emission control signal EM1 are at high level.

Since the first scan signal S1 is at a low level, the seventh transistor M7 is turned on to transmit the second power signal Vref obtained at the first terminal thereof to the point D.

Since the second light emission control signal EM2 is at a low level, the sixth transistor M6 is turned on, and transmits the second power signal Vref, the first terminal of which is obtained from the point D, to the first terminal of the light emitting element LED.

The first end of the light emitting element LED is reset according to the second power signal Vref.

Since the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the second power signal Vref is not transmitted to the first capacitor C1 during the period, and resets the first terminal of the first capacitor C1.

Since the signal states of other periods are the same as those shown in fig. 5, the operation process of the pixel driving circuit is the same, and will not be described here again.

Fig. 7 is a timing chart of driving signals according to another exemplary embodiment of the present application, where the driving signal timing chart is different from that of fig. 5 only in the period t23, and the signal status remains unchanged in other periods.

The signal state and the operation of the pixel driving circuit in the period t23 are explained below.

In a period t23 in the driving signal timing chart, the first scan signal S1, the second scan signal S2, the first emission control signal EM1, and the second emission control signal EM2 are at high level, and the third scan signal S3 is at low level.

Since the third scan signal S3 is at a low level, the second transistor M2 is turned on to transmit the driving data Vdata transmitted from the first terminal thereof to the first terminal of the first transistor M1.

Since the second scan signal S2 is at a high level, the third transistor M3 is turned off, and the circuit between the second terminal and the control terminal of the first transistor M1 is opened.

The control terminal of the first transistor M1 obtains the compensated data vdata+vth1 from the first terminal of the first capacitor C1, and is turned on according to the compensated data.

Since the first terminal of the first transistor M1 acquires the driving data Vdata from the second transistor M2, when a current value of the driving signal is determined based on the data acquired at the first terminal and the control terminal thereof, the current value is k (vdata+vth 1-Vdata-Vth 1) =0, and thus the second terminal of the first transistor M1 does not output the driving signal.

Meanwhile, since the second emission control signal EM2 is at a high level, the sixth transistor M6 is turned off and does not transmit an electrical signal.

The light emitting element LED does not acquire a driving signal in this period and does not emit light.

Since the signal states of other periods are the same as those shown in fig. 5, the operation process of the pixel driving circuit is the same, and will not be described here again.

Fig. 8 is a timing chart of driving signals according to another exemplary embodiment of the present application, where the driving signal timing chart is different from that of fig. 7 only in the period t11, and the signal status remains unchanged in other periods.

Since the waveform of the t11 period of fig. 8 is the same as the waveform of the t11 period of fig. 6, the operation process of the pixel driving circuit in the t11 period has been explained in detail in the corresponding embodiment of fig. 6, and will not be described again here.

The scanning signal in the driving process is supplied from the scanning signal generating circuit, and the circuit configuration of the scanning signal generating circuit is explained below as shown in fig. 9.

The scanning signal generating circuit includes a plurality of driving signal generating units, a first driving signal generating unit D1, a second driving signal generating unit D2, an.

The input terminal of the first driving signal generating unit D1, the first clock signal input terminal CLK1, the second clock signal input terminal CLK2 are electrically connected to the control circuit 10, configured to acquire the first trigger signal STV1 or the second trigger signal STV2 from the input terminal, acquire the first clock signal CK from the first clock signal input terminal CLK1, acquire the second clock signal CB from the second clock signal input terminal CLK2, and output the first signal s1 according to the two clock signals and the first trigger signal STV1 or the second trigger signal STV 2.

More specifically, the first driving signal generating unit D1 is configured to output, as the first signal s1, a signal in accordance with the waveform of the second clock signal CB in the second period when the signal obtained at the input terminal thereof coincides with the waveform of the first clock signal CK in the first period. The second time period is the next time period adjacent to the first time period.

The input terminal of the second driving signal generating unit D2 is electrically connected to the output terminal of the first driving signal generating unit D1, and the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are electrically connected to the control circuit 10.

The second driving signal generating unit D2 is configured to acquire the first signal s1 from its input terminal, acquire the second clock signal CB from the first clock signal input terminal CLK1, acquire the second clock signal CK from the first clock signal input terminal CLK2, and output the second signal s2 based on both the clock signals and the first signal s 1.

More specifically, the second driving signal generating unit D2 is configured to output, as the second signal s2, a signal in accordance with the waveform of the first clock signal CK in the third period when the signal acquired at the input terminal thereof coincides with the waveform of the second clock signal CB in the second period. The third time period is the next time period adjacent to the second time period.

Similarly, the output terminal of the N-1 th driving signal generating unit DN-1 and the input terminal of the N-th driving signal generating unit DN are electrically connected.

In the driving signal generating units whose arrangement order is odd, the first clock signal input terminals CLK1 are each configured to acquire the first clock signal CK, the second clock signal input terminals CLK2 are each configured to acquire the second clock signal CB, and the input terminals of each driving signal generating unit acquire the scanning signal generated by the previous driving signal generating unit or the first trigger signal STV 1/the second trigger signal STV2 output by the control circuit 10, and generate the corresponding scanning signal according to the operation principle of the first driving signal generating unit D1.

In the drive signal generation units of which the arrangement order is even, the first clock signal input terminals CLK1 are each configured to acquire the second clock signal CB, and the second clock signal input terminals CLK2 are each configured to acquire the first clock signal CK. The input end of each driving signal generating unit acquires the scanning signal generated by the previous driving signal generating unit and generates a corresponding scanning signal according to the operation principle of the second driving signal generating unit D2.

Based on the above circuit configuration, the scanning signal generation circuit 301 generates a plurality of signals s1 to sN.

Fig. 10 is an input/output signal timing chart of the scan signal generating circuit shown in fig. 9 for obtaining the first trigger signal STV1, fig. 11 is an input/output signal timing chart of the scan signal generating circuit shown in fig. 9 for obtaining the second trigger signal STV2, and an operation procedure of the scan signal generating circuit is explained based on the input/output signal timing chart. The display period T comprises a plurality of display periods, and the time length of each display period is the same. In the signal timing diagrams shown in fig. 10 and 11, a display period T includes N display periods T0 to tN.

When the trigger signal obtained by the first drive signal generating unit D1 is the first trigger signal STV1, the state change of the input/output signal of the scan signal generating circuit is as follows:

in the t0 period, the first trigger signal STV1 is low, the first clock signal CK is low, and the second clock signal CB is high. In the t1 period, the second clock signal CB is low.

Since the waveform of the first trigger signal STV1 and the first clock signal CK are both at low level, the first driving signal generating unit D1 outputs the same waveform as the second clock signal CB, i.e., outputs the low level, in the period corresponding to t1, and the first signal s1 is at low level.

In the period corresponding to t1, the first trigger signal STV1 is at low level, the first clock signal CK is at high level, and the second clock signal CB is at low level. In the period corresponding to t2, the first clock signal CK is low level.

Since the first trigger signal STV1 is low and the second clock signal CK is high in the period t1, the signal output from the first driving signal generating unit D1 in the period t2 is a default signal and is high, and the first signal s1 is high.

Since the first signal s1 is low in the period t1 and the second clock signal CB is low, the second driving signal generating unit D2 outputs the same waveform as the first clock signal CK, i.e., outputs the low level in the period t2, and the second signal s2 is low.

In the period t2, the first trigger signal STV1 is low, the first clock signal CK is low, and the second clock signal CB is high. In the period t3, the second clock signal CB is low.

In the period t2, since the first trigger signal STV1 is low, the first clock signal CK is low, and the first driving signal generating unit D1 outputs the same waveform as the second clock signal CB, i.e., outputs low, in the period corresponding to t3, and the first signal s1 is low.

In the period t2, since the first signal s1 is at a high level and the second clock signal CB is at a low level, the signal output by the second driving signal generating unit D2 in the period t3 is a default signal and is at a high level, and the second signal s2 is at a high level.

In the period t2, since the second signal s2 is low, the first clock signal CK is low, and the third driving signal generating unit D3 outputs the same waveform as the second clock signal CB, i.e., outputs the low, in the period t3, and the third signal s3 is low.

In the period t3, the first trigger signal STV1 is at a high level, the first clock signal CK is at a high level, and the second clock signal CB is at a low level. In the period t4, the second clock signal CB is high.

In the period t3, since both the first trigger signal STV1 and the first clock signal CK are at a high level, the first driving signal generating unit D1 outputs the same waveform as the second clock signal CB at a high level, i.e., the first signal s1 is at a high level, in the period t 4.

In the period t3, since the first signal s1 is low and the second clock signal CB is low, the second driving signal generating unit D2 outputs the same waveform as the first clock signal CK to be low, i.e., the second signal s2 is low, in the period t 4.

In the period t3, since the second signal s2 is at a high level and the first clock signal CK is at a high level, the third driving signal generating unit D3 outputs the same waveform as the second clock signal CB at a high level, that is, the third signal s3 is at a high level, in the period t 4.

In the period t3, since the third signal s3 is low, the second clock signal CB is low, and the fourth driving signal generating unit D4 outputs the same waveform as the first clock signal CK in the period t4, the fourth signal s4 is low.

Similarly, it can be known that in the period from T0 to tN, according to the first trigger signal STV1 from T0 to T2, and from T3 to tN, the square wave pulse signals of two low levels are generated in a display period T. And the period of time for each driving signal generating unit to generate the first square wave pulse signal is later than the period of time for each driving signal generating unit connected with the input end to generate the first square wave pulse signal.

When the trigger signal obtained by the first drive signal generating unit D1 is the second trigger signal STV2, the state change of the input/output signal of the scan signal generating circuit is as follows:

In the t0 period, the second trigger signal STV2 is low, the first clock signal CK is low, and the second clock signal CB is high. In the t1 period, the second clock signal CB is low.

Since the waveform of the second trigger signal STV2 and the first clock signal CK are both at low level, the first driving signal generating unit D1 outputs the same waveform as the second clock signal CB, i.e., outputs the low level, in the period corresponding to t1, and the first signal s1 is at low level.

In the period corresponding to t1, the second trigger signal STV2 is at a high level, the first clock signal CK is at a high level, and the second clock signal CB is at a low level. In the period corresponding to t2, the second clock signal CB is at a high level and the first clock signal CK is at a low level.

Since the second trigger signal STV2 is at a high level and the second clock signal CK is at a high level in the t1 period, the first driving signal generating unit D1 outputs the same waveform as the second clock signal CB at a high level and the first signal s1 is at a high level in the t2 period.

Since the first signal s1 is low in the period t1 and the second clock signal CB is low, the second driving signal generating unit D2 outputs the same waveform as the first clock signal CK, i.e., outputs the low level in the period t2, and the second signal s2 is low.

In the period t2, the second trigger signal STV1 is at a high level, the first clock signal CK is at a low level, and the second clock signal CB is at a high level.

In the period t2, since the second trigger signal STV2 is at a high level and the first clock signal CK is at a low level, the first driving signal generating unit D1 outputs a default electric signal, i.e., outputs a high level, in a period corresponding to t3 and the first signal s1 is at a high level.

Since the second trigger signals STV2 from the period t3 to the period tN are all at the high level, the generation process of the first signal s1 is the same as the generation process in the period t1 in the period t2k+1 from the period t3 to the period tN, the generation process of the first signal s1 is at the high level in the period t2k, and the generation process of the first signal s1 is the same as the generation process in the period t2, and the first signal s1 is at the high level. Wherein k is a positive integer.

In the period t2, since the first signal s1 is at a high level and the second clock signal CB is at a high level, the second driving signal generating unit D2 outputs the same waveform as the first clock signal CK in the period t3 and is at a high level and the second signal s2 is at a high level.

In the period t2, since the second signal s2 is low, the first clock signal CK is low, and the third driving signal generating unit D3 outputs the same waveform as the second clock signal CB, i.e., outputs the low, in the period t3, and the third signal s3 is low.

Similarly, it can be known that in the period from T0 to tN, according to the second trigger signal STV2 having the low level from T0 to tN, each driving signal generating unit generates a low level square wave pulse having the time length of one display period in one display period T. And the time period of each driving signal generating unit generating the square wave pulse signal is later than the time period of the driving signal generating unit connected with the input end thereof generating the square wave pulse signal.

The circuit configuration of the light emission control signal generation circuit is as shown in fig. 12, and the circuit configuration of the light emission control signal generation circuit is explained below.

The light emission control signal generation circuit includes a plurality of em signal generation units, a first em signal generation unit d1, a second em signal generation unit d2, and a Nem signal generation unit dN.

The connection relationship of each em signal generating unit is the same as that of each trigger signal generating unit in the scanning signal generating circuit, and will not be described here again.

The process of generating d 1-dN signals by the light-emitting control signal generating circuit is the same as the process of generating s 1-sN signals by the scanning signal generating circuit, and the description thereof is omitted.

Fig. 13 is a timing chart of input/output signals of the light emission control signal generating circuit, as shown in fig. 12 and 13, the third trigger signal STV3 is at a high level from a period T0 to a period T7, and is at a low level from a period T8 to a period tN in a display period T.

The first signal em1 generated by the first em signal generating unit d1 is at a high level for a period T1 to a period T8 in a display period T, and at a low level for the remaining period.

The second signal em2 generated by the second em signal generating unit d2 is at a high level for a period T2 to a period T9 in a display period T, and at a low level for the remaining period.

Similarly, the em signals generated by the em signal generating units are high in seven adjacent time periods in a display period, the rest time periods are low, and the time for the em signals to jump from low to high is later than the time for the input ends of the em signals to acquire signals from low to high.

When the trigger signal obtained at the input terminal of the first scanning signal generating circuit is the first trigger signal STV1, the trigger signal obtained at the input terminal of the second scanning signal generating circuit is the second trigger signal STV2, and the clock signals of the scanning signal generating circuits and the light emission signal generating circuits are synchronized, the waveforms shown in fig. 5 are configured by using the third signal S3 generated by the second scanning signal generating circuit as the first scanning signal S1, the fifth signal S5 as the third scanning signal S3, the third signal S3 generated by the first scanning signal generating circuit as the second scanning signal S2, the first signal EM1 generated by the light emission control signal generating circuit as the first light emission control signal EM1, and the fourth signal EM4 as the second light emission control signal EM2 for the pixel driving circuits of the first row in the display panel 40.

According to the logic of the row-by-row driving, the fourth signal S4 generated by the second scanning signal generating circuit is used as the first scanning signal S1, the sixth signal S6 is used as the third scanning signal S3, the fourth signal S4 generated by the first scanning signal generating circuit is used as the second scanning signal S2, the second signal EM2 generated by the light emission control signal generating circuit is used as the first light emission control signal EM1, and the fifth signal EM5 is used as the second light emission control signal EM2 for the pixel driving circuits of the second row in the display panel 40.

And so on until the corresponding first scan signal S1, second scan signal S2, third scan signal S3, first light emission control signal EM1 and second light emission control signal EM2 are provided to the pixel driving circuits of all rows in the display panel 40, so as to implement the driving process as shown in fig. 5.

When the trigger signal obtained at the input terminal of the first scanning signal generating circuit is the first trigger signal STV1, the trigger signal obtained at the input terminal of the second scanning signal generating circuit is the second trigger signal STV2, and the clock signals of the scanning signal generating circuits and the light emission signal generating circuits are synchronized, the waveforms shown in fig. 6 are configured by using the first signal S1 generated by the first scanning signal generating circuit as the first scanning signal S1, the third signal S3 as the second scanning signal S2, the fifth signal S5 generated by the second scanning signal generating circuit as the third scanning signal S3, the first signal EM1 generated by the light emission control signal generating circuit as the first light emission control signal EM1, and the fourth signal EM4 as the second light emission control signal EM2 for the pixel driving circuits of the first row in the display panel 40.

In accordance with the logic of the row-by-row driving, the second signal S2 generated by the first scanning signal generating circuit is used as the first scanning signal S1, the fourth signal S4 is used as the second scanning signal S2, the sixth signal S6 generated by the second scanning signal generating circuit is used as the third scanning signal S3, the second signal EM2 generated by the light emission control signal generating circuit is used as the first light emission control signal EM1, and the fifth signal EM5 is used as the second light emission control signal EM2 for the pixel driving circuits of the second row in the display panel 40.

And so on until the corresponding first scan signal S1, second scan signal S2, third scan signal S3, first light emission control signal EM1 and second light emission control signal EM2 are provided to the pixel driving circuits of all rows in the display panel 40, so as to implement the driving process as shown in fig. 6.

When the trigger signal obtained at the input terminal of the first scanning signal generating circuit is the first trigger signal STV1, the trigger signal obtained at the input terminal of the second scanning signal generating circuit is the second trigger signal STV2, and the clock signals of the scanning signal generating circuits and the light emission signal generating circuits are synchronized, the waveforms shown in fig. 7 are configured by using the third signal S3 generated by the second scanning signal generating circuit as the first scanning signal S1, the third signal S3 generated by the first scanning signal generating circuit as the second scanning signal S2, the fifth signal S5 as the third scanning signal S3, the first signal EM1 generated by the light emission control signal generating circuit as the first light emission control signal EM1, and the fourth signal EM4 as the second light emission control signal EM2 for the pixel driving circuits of the first row in the display panel 40.

According to the logic of the row-by-row driving, the fourth signal S4 generated by the second scanning signal generating circuit is used as the first scanning signal S1, the fourth signal S4 generated by the first scanning signal generating circuit is used as the second scanning signal S2, the sixth signal S6 is used as the third scanning signal S3, the second signal EM2 generated by the light emission control signal generating circuit is used as the first light emission control signal EM1, and the fifth signal EM5 is used as the second light emission control signal EM2 for the pixel driving circuits of the second row in the display panel 40.

And so on until the corresponding first scan signal S1, second scan signal S2, third scan signal S3, first light emission control signal EM1 and second light emission control signal EM2 are provided to the pixel driving circuits of all rows in the display panel 40, so as to implement the driving process as shown in fig. 7.

When the trigger signal obtained at the input terminal of the first scanning signal generating circuit is the first trigger signal STV1, and the clock signals of the scanning signal generating circuits and the light-emitting signal generating circuits are synchronized, the waveforms shown in fig. 7 are configured by using the first signal S1 generated by the first scanning signal generating circuit as the first scanning signal S1, the third signal S3 as the second scanning signal S2, the fifth signal S5 as the third scanning signal S3, the first signal EM1 generated by the light-emitting control signal generating circuit as the first light-emitting control signal EM1, and the fourth signal EM4 as the second light-emitting control signal EM2 for the pixel driving circuits of the first row in the display panel 40.

In accordance with the logic of the row-by-row driving, the second signal S2 generated by the first scanning signal generating circuit is used as the first scanning signal S1, the fourth signal S4 is used as the second scanning signal S2, the sixth signal S6 is used as the third scanning signal S3, the second signal EM2 generated by the light emission control signal generating circuit is used as the first light emission control signal EM1, and the fifth signal EM5 is used as the second light emission control signal EM2 for the pixel driving circuits of the second row in the display panel 40.

Until the corresponding first scan signal S1, second scan signal S2, third scan signal S3, first light emission control signal EM1 and second light emission control signal EM2 are supplied to the pixel driving circuits of all rows in the display panel 40, to implement the driving process as shown in fig. 8.

Due to multiplexing of the scanning signal generating circuit and the light-emitting control signal generating circuit, the space of the grid driving circuit is reduced, and the narrow frame characteristic of the display device is guaranteed.

The above circuits are all described on the basis of the circuit connection relation and the driving process of the P-type transistors in the pixel driving circuit, and when the transistors in the pixel driving circuit are all N-type transistors, the electric signal obtained from the power line 90 at the first end of the fifth transistor M5 is the first power signal VSS, and the first power signal VSS is low level. The second power signal Vref obtained from the power line 90 at the first terminal of the seventh transistor M7 is at a high level.

Due to the characteristics of the N-type transistors, each transistor in the pixel driving circuit is turned on when a high level is obtained and turned off when a low level is obtained. Accordingly, the driving signal timing chart obtained by the pixel driving circuit based on the N-type transistor is opposite in level to the driving signal timing chart shown in fig. 5 to 8 in each period.

Accordingly, the levels of the trigger signals obtained by the scan signal generation circuit and the light emission control signal generation circuit are opposite in each period.

Based on the above-described scanning signal and light emission control signal, the driving process of the pixel driving circuit is similar to that shown in fig. 5 to 8, and will not be described here again.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (14)

1. A display device, comprising: A display panel, wherein a power line, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixel circuits are arranged on the display panel; Each of the sub-pixel circuits includes a pixel driving circuit and a light-emitting element; Characterized in that the pixel driving circuit comprises: a seventh transistor, a first end of which is electrically connected to the power line, a control end of which is electrically connected to the gate line, and configured to obtain a first scan signal and a second power signal, to control its conduction state by the first scan signal, and to output the second power signal from its second end when it is turned on; a sixth transistor, a first end of which is electrically connected to the second end of the seventh transistor, a control end of which is electrically connected to the gate line, a second end of which is electrically connected to the first end of the light-emitting element, and configured to obtain a second light-emitting control signal and the second power supply signal, and to control its conduction state by the second light-emitting control signal, and to output the second power supply signal from its second end when it is turned on, so as to reset the first end of the light-emitting element; a third transistor, a first end of which is electrically connected to the second end of the seventh transistor, a control end of which is electrically connected to the gate line, and configured to obtain a second scanning signal and the second power supply signal, to control its conduction state by the second scanning signal, and to output the second power supply signal from its second end when it is turned on; The first capacitor has a first terminal electrically connected to the second terminal of the third transistor and is configured to reset the first terminal thereof using the second power signal. 2. The display device according to claim 1, wherein the display panel further comprises: a second transistor and a first transistor; The first end of the second transistor is electrically connected to the data line, and the control end thereof is electrically connected to the gate line, and is configured to obtain a third scanning signal and driving data, and its conduction state is controlled by the third scanning signal, and the driving data is output from the second end thereof when it is turned on; The first end of the first transistor is electrically connected to the second end of the second transistor, the control end is electrically connected to the first end of the first capacitor, and the second end is electrically connected to the first end of the third transistor, and is configured to obtain the driving data and the second power supply signal, control its conduction state by the second power supply signal, and determine the driving data after threshold voltage compensation from its control end when it is turned on and its second end and the control end are short-circuited; The third transistor is further configured to short-circuit the second terminal and the control terminal of the first transistor when the third transistor is turned on; The first capacitor is further configured to store the threshold voltage compensated driving data. 3. The display device according to claim 2, wherein the display panel further comprises a fifth transistor; The first terminal of the fifth transistor is electrically connected to the power line, and the control terminal thereof is electrically connected to the gate line, and is configured to obtain a first light-emitting control signal and a first power signal, and control its conduction state by the first light-emitting control signal, and output the first power signal from its second terminal when it is turned on; The first end of the first transistor is electrically connected to the second end of the fifth transistor, and is further configured to obtain the first power signal and the driving data after the threshold voltage is compensated, and output a driving signal from its second end according to the first power signal and the driving data after the threshold voltage is compensated; The sixth transistor is further configured to obtain the driving signal from its first terminal when it is turned on, and transmit the driving signal to the first terminal of the light emitting element; The light emitting element is configured to emit light according to the driving signal. 4. The display device according to claim 3, characterized in that the display device further comprises a gate driving circuit, and the gate driving circuit comprises a scanning signal generating circuit; The scanning signal generating circuit is electrically connected to the gate line and configured to generate a plurality of scanning sub-signals, wherein three adjacent scanning sub-signals with an interval of a first preset number are transmitted to a row of pixel driving circuits through the gate line; Wherein, within a display period, the phase of each scanning sub-signal is shifted backward successively, and the three adjacent scanning sub-signals with a first preset number of intervals are respectively used as the first scanning signal, the second scanning signal and the third scanning signal of the pixel driving circuit; Wherein, a display cycle includes a plurality of display time periods. In a display cycle, each scanning sub-signal is at a first level in two display time periods whose interval number is a first preset number, and is at a second level in the remaining display time periods. 5. The display device according to claim 3, characterized in that the display device further comprises a gate driving circuit, and the gate driving circuit comprises a first scanning signal generating circuit and a second scanning signal generating circuit; The first scanning signal generating circuit is electrically connected to the gate line and configured to generate a plurality of first scanning sub-signals, wherein two adjacent first scanning sub-signals with an interval of a third preset number are transmitted to a row of pixel driving circuits through the gate line; The second scanning signal generating circuit is electrically connected to the gate line and is configured to generate a plurality of second scanning sub-signals, each of which is transmitted one by one to the pixel driving circuit of the corresponding row through the gate line; In one display period, the phase of each first scanning sub-signal is shifted backward successively. 6. The display device according to claim 5, characterized in that a display cycle includes a plurality of display time periods; In a display cycle, the two adjacent first scanning sub-signals whose interval is a third preset number are respectively used as the first scanning signal and the third scanning signal of the pixel driving circuit, and the second scanning sub-signal is used as the second scanning signal of the pixel driving circuit; wherein each first scanning sub-signal is at the first level in one display period, and at the second level in the remaining display period of the display cycle, and each second scanning sub-signal is at the first level in two display periods whose interval is a third preset number, and at the second level in the remaining display period of the display cycle; or In a display cycle, the two adjacent first scanning sub-signals whose interval is a third preset number are respectively used as the first scanning signal and the second scanning signal of the pixel driving circuit, and the second scanning sub-signal is used as the third scanning signal of the pixel driving circuit; wherein each first scanning sub-signal is at the first level in two display time periods whose interval is the third preset number, and is at the second level in the remaining display time periods of the display cycle, and each second scanning sub-signal is at the first level in one display time period; or In a display cycle, the two adjacent first scanning sub-signals whose interval is a third preset number are respectively used as the second scanning signal and the third scanning signal of the pixel driving circuit, and the second scanning sub-signal is used as the first scanning signal of the pixel driving circuit; wherein, each first scanning sub-signal is at the first level in two display time periods whose interval is the third preset number, and is at the second level in the remaining display time periods of the display cycle, and each second scanning sub-signal is at the first level in one display time period. 7. The display device according to claim 4 or 6, characterized in that the gate driving circuit further comprises a light emitting control signal generating circuit; The light emitting control signal generating circuit is electrically connected to the gate line and configured to generate a plurality of light emitting control signals, wherein two adjacent light emitting control signals with an interval of a second preset number are transmitted to a row of pixel driving circuits through the gate line; Wherein, within a display cycle, the phases of the light-emitting control signals are shifted backward successively, and the two adjacent light-emitting control signals with an interval of a second preset number serve as the first light-emitting control signal and the second light-emitting control signal of the pixel driving circuit. 8. The display device according to claim 7, characterized in that a display cycle comprises a reset phase, a data writing phase and a display phase in sequence; The reset phase includes a reset sub-phase; In the reset sub-phase, the first scanning signal, the second scanning signal and the second light-emitting control signal are at a first level, and the third scanning signal and the first light-emitting control signal are at a second level; The seventh transistor is turned on according to the first light emitting control signal, and the second power supply signal obtained at the first end thereof is transmitted to the first end of the sixth transistor and the first end of the third transistor; The sixth transistor is turned on according to the second light emitting control signal, and transmits the second power supply signal obtained at the first end thereof to the first end of the light emitting element; The third transistor is turned on according to the second scanning signal, and transmits the second power signal obtained at the first end thereof to the first capacitor; The first capacitor resets its first end using the second power signal; The light emitting element resets its first end according to the second power signal. 9. The display device according to claim 8, characterized in that the data writing phase includes a data writing sub-phase; In the data writing sub-phase, the first scanning signal, the first light emitting control signal and the second light emitting control signal are at the second level, and the second scanning signal and the third scanning signal are at the first level; The second transistor is turned on according to the third scanning signal, and transmits the driving data obtained at the first end thereof to the first end of the first transistor; The third transistor is turned on according to the second scanning signal to short-circuit the second end and the control end of the first transistor; The first transistor obtains a second power supply signal from the first capacitor, is turned on according to the second power supply signal, and obtains driving data after threshold voltage compensation from its control terminal according to the driving data; The first capacitor stores the driving data after the threshold voltage is compensated. 10. The display device according to claim 9, characterized in that the display stage includes a non-luminous stage and a luminous stage; In the display stage, the first scanning signal, the second scanning signal, and the third scanning signal are at the second level, and the first light emitting control signal is at the first level; In the non-light-emitting stage, the second light-emitting control signal is at a second level; The fifth transistor is turned on according to the first light emitting control signal, and transmits the first power signal obtained at the first end thereof to the first end of the first transistor; The control terminal of the first transistor obtains the driving data after the threshold voltage compensation from the first capacitor, and transmits a driving signal to the sixth transistor according to the first power signal, the driving data after the threshold voltage compensation and its threshold voltage; The sixth transistor is turned off according to the second light emitting control signal and does not transmit the driving signal; The light emitting element does not emit light. 11. The display device according to claim 10, characterized in that in the light emitting stage, the second light emitting control signal is at a first level; The sixth transistor is turned on according to the second light emitting control signal, and transmits the driving signal obtained at the first end thereof to the light emitting element; The light emitting element emits light according to the driving signal. 12. A method for controlling a display device, used for the display device according to any one of claims 1 to 11, characterized in that the method comprises: Controlling the seventh transistor and the third transistor to be turned on in the same period, so that the seventh transistor and the third transistor transmit the second power supply signal to the first capacitor, and reset the first end of the first capacitor; The seventh transistor and the sixth transistor are controlled to be turned on in the same period, so that the seventh transistor and the sixth transistor transmit the second power supply signal to the light emitting element, and reset the first end of the light emitting element. 13. The method according to claim 12, characterized in that the method further comprises: After resetting the first capacitor, the third transistor and the second transistor are controlled to be turned on in the same period and the second transistor transmits driving data, so that the first capacitor stores driving data after the threshold voltage of the first transistor is compensated determined by the control terminal of the first transistor. 14. The method according to claim 13, characterized in that the method further comprises: After the first capacitor stores the driving data after the threshold voltage of the first transistor is compensated, the fifth transistor and the sixth transistor are controlled to be turned on in the same period and the fifth transistor transmits a first power signal, so that the first transistor generates a driving signal using the driving data after the threshold voltage of the first transistor stored in the first capacitor and the first power signal to drive the light-emitting element to emit light.