CN119232154B - Multi-acquisition-module synchronous time sequence calibration method, device, equipment and medium - Google Patents
Multi-acquisition-module synchronous time sequence calibration method, device, equipment and medium Download PDFInfo
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Abstract
The application discloses a method, a device, equipment and a medium for calibrating synchronous time sequences of multiple acquisition modules, which comprise the steps of determining a plurality of synchronous window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip, and determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the plurality of synchronous window sets of each acquisition module, wherein a processor of each acquisition module performs data sampling according to the optimal synchronous window position. The application realizes the synchronous time sequence calibration of the multiple acquisition modules by calibrating the acquisition time sequence synchronization between two analog-digital conversion chips in each module and keeping the phase relation between the multiple modules consistent under different environmental temperatures.
Description
Technical Field
The application relates to the technical field of high-speed signal acquisition modules, in particular to a method, a device, equipment and a medium for calibrating synchronous time sequences of multiple acquisition modules.
Background
In the process of multipath signal acquisition, it is important to maintain the stability of the signal acquisition system, which requires good synchronization between chips and modules. However, the hardware difference of the signal acquisition system, the environmental changes (such as temperature, humidity and pressure) during the acquisition, and other factors may cause metastable state phenomenon, so that the synchronization of the signal acquisition system is invalid, that is, the setup time (ts) and the hold time (th) between the synchronization signal and the clock are unstable, and thus the signal acquisition phenomenon across clock cycles may occur.
If a signal acquisition system with two interleaved analog-to-digital conversion chips is used, a saw-tooth waveform may be generated, so that for a multi-module synchronous signal acquisition system, a phase difference of multiple clock cycles may occur between different modules.
The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present application and is not intended to represent an admission that the foregoing is prior art.
Disclosure of Invention
The application mainly aims to provide a multi-acquisition-module synchronous time sequence calibration method, device, equipment and medium, which aim to solve the technical problem of time sequence synchronous failure of an acquisition system caused by factory difference of hardware in the signal acquisition system and change of environmental factors in the acquisition process.
The application provides a synchronous time sequence calibration method for multiple acquisition modules, which is applied to measuring equipment, wherein the measuring equipment comprises multiple acquisition modules, each acquisition module comprises multiple analog-to-digital conversion chips, the method is executed by synchronous time sequence calibration equipment in communication connection with each acquisition equipment, the method is executed by a processor and comprises the steps of determining multiple synchronous window sets of each acquisition module based on window information provided by each analog-to-digital conversion chip and used for synchronous sampling, determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronous window sets of each acquisition module, and the processor of each acquisition module performs data sampling according to the optimal synchronous window position.
Optionally, the determining the multiple synchronous window sets of each acquisition module includes calculating multiple optional positions included in window information provided by each analog-to-digital conversion chip for synchronous sampling, and determining the multiple synchronous window sets of each acquisition module based on the multiple optional positions of each analog-to-digital conversion chip in each acquisition module.
Optionally, the calculating the plurality of optional positions included in the window information for synchronous sampling provided by each analog-to-digital conversion chip comprises determining at least one optional interval of each analog-to-digital conversion chip based on the window information for synchronous sampling provided by each analog-to-digital conversion chip, and determining the plurality of optional positions of each analog-to-digital conversion chip based on each optional interval.
The method comprises the steps of determining a position combination sequence of each acquisition module according to a plurality of synchronous window sets of each acquisition module, supplementing the position combination sequence of each acquisition module based on the data number difference of the position combination sequences of different acquisition modules, and determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module based on the position combination sequence supplemented by each acquisition module.
Optionally, the determining the position combination sequence of each acquisition module according to the plurality of synchronization window sets of each acquisition module includes determining, for any acquisition module, a phase difference between a plurality of analog-to-digital conversion chips under each synchronization window set, determining a plurality of position combination values of the acquisition module based on the synchronization window set corresponding to the phase difference being smaller than a preset threshold, and forming the position combination sequence of each acquisition module from the plurality of position combination values of each acquisition module.
Optionally, the step of supplementing the position combination sequences of the acquisition modules based on the data number difference of the position combination sequences of the different acquisition modules comprises the steps of determining the acquisition module corresponding to the position combination sequence with the largest data number as a reference acquisition module, and supplementing the position combination sequence of each acquisition module according to the data number difference of the position combination sequences of each acquisition module and the reference acquisition module.
Optionally, the determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the position combination sequence after the alignment of each acquisition module comprises calculating standard deviations of a plurality of same position data in the position combination sequence after the alignment of all the acquisition modules, and determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the difference of the standard deviations.
In addition, in order to achieve the purpose, the application further provides a multi-acquisition-module synchronous time sequence calibration device, which comprises a synchronous window set determining module, an optimal sampling position determining module and a synchronous time sequence calibration module, wherein the synchronous window set determining module is used for determining a plurality of synchronous window sets of each acquisition module, the synchronous window sets are used for representing optional positions of analog-to-digital conversion chips in the acquisition modules, the optimal sampling position determining module is used for determining optimal sampling positions of the acquisition modules according to the synchronous window sets of the acquisition modules, and the synchronous time sequence calibration module is used for completing synchronous time sequence calibration of the multi-acquisition modules based on the optimal sampling positions of the acquisition modules.
The application also provides multi-acquisition module synchronous time sequence calibration equipment which comprises at least one processor and a memory in communication connection with the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the multi-acquisition module synchronous time sequence calibration method.
The application also provides a computer readable storage medium, which comprises a computer program stored therein, wherein the computer program realizes the multi-acquisition module synchronous time sequence calibration method when being executed by a processor.
According to the multi-acquisition module synchronous time sequence calibration method, device, equipment and medium, the problems that in the multi-channel signal acquisition process, due to the fact that the delivery difference of hardware and the environmental factors change, the time sequence of the multi-acquisition module is synchronous and deviation occurs in the process of multi-channel signal acquisition are solved, the acquisition time sequence of two analog-to-digital conversion chips in each module is synchronous through calibration at different environmental temperatures, and the phase relation among the multi-modules is kept consistent are solved, so that the synchronous time sequence calibration of the multi-acquisition module is achieved.
Drawings
FIG. 1 is a flow chart of a method for multi-acquisition module synchronous timing calibration according to one embodiment of the present application;
FIG. 2 is a diagram illustrating metastability phenomena;
FIG. 3 is a schematic diagram of an acquisition system according to an embodiment of the present application;
FIG. 4 is a schematic diagram of sampling positions of two analog-to-digital conversion chips according to an embodiment of the present application;
FIG. 5 is a graph showing the effects of interleaved sampling when two analog-to-digital conversion chips have a phase difference of 200ps according to an embodiment of the present application;
FIG. 6 is a diagram showing the optimal synchronization window positions of the analog-to-digital conversion chips according to an embodiment of the present application;
FIG. 7 is a diagram showing the optimal synchronization window positions of the analog-to-digital conversion chips according to another embodiment of the present application;
FIG. 8 is a block diagram of a multi-acquisition module synchronous timing calibration apparatus according to one embodiment of the present application;
fig. 9 is a schematic structural diagram of a multi-acquisition module synchronous timing calibration apparatus according to an embodiment of the present application.
The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Since it is critical to maintain the stability of the signal acquisition system during the multipath signal acquisition process, this requires good synchronization between the chips and between the modules. However, the metastable phenomenon may occur due to factors such as hardware differences of the signal acquisition system and environmental changes (such as temperature, humidity and pressure) during acquisition, as shown in fig. 2, fig. 2 is a schematic diagram of the metastable phenomenon occurring when the synchronizing signal deviates, in which ts represents the setup time between the synchronizing signal and the sampling clock, th represents the hold time between the synchronizing signal and the sampling clock, and the metastable phenomenon may cause synchronization failure of the signal acquisition system, that is, the setup time and the hold time between the synchronizing signal and the clock are unstable, so that the signal acquisition phenomenon across clock periods may occur.
In order to solve the above problems, the present application provides a method for calibrating synchronous timing of multiple acquisition modules, and the following detailed description of the scheme of the present application is provided.
Fig. 1 is a flowchart of a multi-acquisition module synchronous timing calibration method according to an embodiment of the present application, which may be applied to a measurement device, in particular, to fields of electronic test measurement instruments, radars, communications, electronic countermeasures, etc., wherein the measurement device may include a plurality of acquisition modules, each acquisition module includes a plurality of analog-to-digital conversion chips, the measurement device may further include a synchronous timing calibration device having data processing capability and communicatively connected to each acquisition device, the multi-acquisition module synchronous timing calibration method may be performed by the synchronous timing calibration device, and the synchronous timing calibration device may be, for example, a multi-acquisition module synchronous timing calibration device, and referring to fig. 1, the multi-acquisition module synchronous timing calibration method may include the following steps:
step S1, a plurality of synchronous window sets of each acquisition module are determined based on window information for synchronous sampling provided by each analog-to-digital conversion chip.
Referring to fig. 3, fig. 3 is a schematic diagram of a system structure of a signal acquisition system according to an exemplary embodiment, where the signal acquisition system may include a measurement device, the number of acquisition modules is 4, and the acquisition modules are a first acquisition module B1, a second acquisition module B2, a third acquisition module B3, and a fourth acquisition module B4, respectively, and each acquisition module includes two analog-to-digital conversion chips Adc1 and Adc2, and the two analog-to-digital conversion chips perform interleaved acquisition.
It should be noted that the acquisition module may be used to acquire and process various types of signals, and may be capable of converting physical quantities in the environment (such as temperature, pressure, light intensity, etc.) into digital signals that may be used for subsequent processing. The analog-to-digital conversion chip (ADC chip) in the acquisition module is a key component in the acquisition module, and the input analog signal is converted into a corresponding digital value by sampling and quantizing the analog signal, so that the discrete representation of the continuous signal is realized. Two analog-to-digital conversion chips (ADC chips) are used for interweaving and collecting in one collecting module, so that the sampling rate and the data precision of the signal collecting system can be remarkably improved. By alternately using two ADC chips, more sampling operations can be completed in a shorter time, thereby achieving higher time resolution, especially advantageous in high frequency signal acquisition or multichannel signal processing. However, when two analog-to-digital conversion chips (ADC chips) are used for interleaved acquisition, the signal acquisition system needs to precisely synchronize the two ADC chips to avoid timing errors or signal deviations that ultimately affect the quality of the final data. Therefore, synchronous timing calibration of the acquisition module is required to ensure accuracy and reliability of the data.
In one embodiment, in step S1, determining the plurality of synchronization window sets of each acquisition module based on the window information for synchronous sampling provided by each analog-to-digital conversion chip may specifically include:
S11, calculating a plurality of optional positions contained in window information provided by each analog-to-digital conversion chip and used for synchronous sampling;
s12, determining a plurality of synchronous window sets of each acquisition module based on a plurality of optional positions of each analog-to-digital conversion chip in each acquisition module.
In step S11, the synchronous timing calibration device may determine at least one optional area of each analog-to-digital conversion chip based on the window information provided by each analog-to-digital conversion chip for synchronous sampling, and then determine a plurality of optional positions of each analog-to-digital conversion chip based on each optional area.
In a specific implementation process, setting a continuous threshold value as P, collecting window information of each analog-digital conversion chip for synchronous sampling, traversing from low level to high level, recording the number of continuously appeared 0, starting recording when the combination of the front bit and the rear bit is 10, continuously counting the number of continuously appeared 0 when the combination of the front bit and the rear bit is 00, ending recording when the combination of the front bit and the rear bit is 01, and recording the interval of continuously appeared 0 as a selectable interval when the number of continuously appeared 0 is more than or equal to the continuous threshold value P.
Further, a plurality of optional positions of each analog-to-digital conversion chip are determined based on each optional interval, wherein the optional positions are the position average value of each optional interval, and the optional positions can be calculated by using the following formula (1), for example:
Wherein, Indicating the end position of each selectable interval,Indicating the starting position of each alternative position.
In an exemplary embodiment, the window information for synchronous sampling of the first analog-to-digital conversion chip b1.adc1 and the second analog-to-digital conversion chip b1.adc2 in the first acquisition module, the first analog-to-digital conversion chip b2.adc1 and the second analog-to-digital conversion chip b2.adc2 in the second acquisition module, the first analog-to-digital conversion chip b3.adc1 and the second analog-to-digital conversion chip b3.adc2 in the third acquisition module, the first analog-to-digital conversion chip b4.adc1 and the second analog-to-digital conversion chip b4.adc2 in the fourth acquisition module may be expressed as b1.adc1= >1001_1000_0001_1000_0000 1101 in order
B1.Adc2=>1110_0000_0011_0000_0001_1001
B2.Adc1=>1001_1000_0001_1000_0001_1001
B2.Adc2=>1100_0000_0110_0000_0011_0001
B3.Adc1=>1000_1100_0000_0110_0000_0111
B3.Adc2=>1000_1100_0000_1100_0000_0111
B4.Adc1=>1000_1100_0000_0110_0000_0011
B4.Adc2=>1000_0110_0000_0110_0000_0011
The analog-digital conversion chips are 24 bits from low level to high level, 1 represents foul, and 0 th bit to 15 th bit can be selected from various optional positions. The middle position of the continuous 0 interval is a preferable sampling position, and the higher the sampling clock frequency is, the shorter the number of bits for obtaining continuous 0 is, and the present exemplary embodiment takes a 5GHz clock as an example.
Specifically, taking the first analog-to-digital conversion chip b1.adc1 in the first acquisition module as an example, the continuous threshold P takes 3, two selectable intervals can be obtained through traversing from low level to high level, and then the 7 th bit and the 15 th bit are obtained through calculation by using the formula (1) based on the two selectable intervals.
Taking the second analog-digital conversion chip b1.adc2 in the first acquisition module as an example, the optional position of b1.adc2 is the 8 th position.
Referring to fig. 4, fig. 4 is a schematic diagram showing optional positions of a first analog-to-digital conversion chip b1.adc1 in the first acquisition module and a second analog-to-digital conversion chip b1.adc2 in the first acquisition module in the present exemplary embodiment.
Further, determining the plurality of synchronization window sets for each of the plurality of acquisition modules based on the plurality of selectable positions for each of the analog-to-digital conversion chips in each of the plurality of acquisition modules in step S12 may specifically include combining the plurality of selectable positions for different analog-to-digital conversion chips in each of the plurality of acquisition modules to obtain the plurality of synchronization window sets.
Specifically, taking the optional positions of the first analog-to-digital conversion chip B1.adc1 in the first acquisition module as the 7 th bit and the 15 th bit and the optional position of the second analog-to-digital conversion chip B1.adc2 in the first acquisition module as the 8 th bit as an example, the synchronization window set of the first acquisition module B1 is {7,8} and {15,8}.
And S2, determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to a plurality of synchronous window sets of each acquisition module, wherein a processor of each analog-to-digital conversion chip performs data sampling according to the optimal synchronous window position.
It should be noted that, in general, the analog-to-digital conversion chip provides window information of synchronous sampling, and can calculate a suitable sampling position through analysis of the window information, set to a register, and keep stable sampling. However, for the embodiment, the two analog-to-digital conversion chips in the acquisition module perform interleaved acquisition, so that the embodiment also needs to ensure that the two analog-to-digital conversion chips perform interleaved phase requirement, taking a 5GHz clock as an example, that is, one clock period is 200ps, please refer to fig. 5, fig. 5 is an interleaved sampling effect diagram when the phase difference of the two analog-to-digital conversion chips is 200ps, that is, the two analog-to-digital conversion chips sample effect diagram across the clock period, and TI-ADC in fig. 5 represents an analog-to-digital converter of TI model, so that, as shown in fig. 5, when the phase difference of the two analog-to-digital conversion chips is too large, distortion of a signal waveform is caused, and thus, instability of the whole signal sampling system is caused.
In one embodiment, in step S2, determining, according to the plurality of synchronization window sets of each acquisition module, an optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module may specifically include:
s21, determining a position combination sequence of each acquisition module according to a plurality of synchronous window sets of each acquisition module;
S22, supplementing the position combination sequences of the acquisition modules based on the data number difference of the position combination sequences of the different acquisition modules;
S23, determining the optimal synchronous window position of each analog-digital conversion chip in each acquisition module based on the position combination sequence after the compensation of each acquisition module.
In step S21, for any acquisition module, the synchronous timing calibration device may determine the phase differences between the multiple analog-to-digital conversion chips under each synchronous window set, determine multiple position combination values of the acquisition module based on the synchronous window set corresponding to the phase differences smaller than the preset threshold, and then form the multiple position combination values of the acquisition module into the position combination sequence of the acquisition module.
In a specific implementation, any currently available calculated phase difference algorithm may be used to determine the phase difference between the multiple analog-to-digital conversion chips under each synchronization window set, such as a sine-three parameter error algorithm and FFT.
In an exemplary embodiment, for any acquisition module, the signals acquired by the two analog-to-digital conversion chips under each synchronization window set may be first subjected to fast fourier transform, that is, FFT, to calculate a phase value of a designated frequency point, and then the two phase values are subtracted, so as to obtain a phase difference of the two analog-to-digital conversion chips under each synchronization window set.
Specifically, the signal source outputs a 1GHz sinusoidal signal to the signal acquisition system, the amplitude of the signal is adjusted to within ±3div of the full range of the analog-to-digital conversion chip, the two analog-to-digital conversion chips acquire the signal based on optional positions corresponding to any one of the synchronization window sets, and perform FFT calculation on the acquired signal, in this embodiment, the sampling frequency of the analog-to-digital conversion chip is set10Gsa/s, and is based on the sampling frequencyCalculating a frequency point index of frequency 1GHz, so that an imaginary part I and a real part R corresponding to frequency 1GH are indexed out from FFT calculation results of signals through the frequency point index of frequency 1GHz, and further, a phase angle of a waveform of a first analog-to-digital conversion chip and a phase angle of a waveform of a second analog-to-digital conversion chip are calculated through an arctangent function based on the imaginary part I and the real part R, so that a difference value of the two phase angles is a phase difference of the first analog-to-digital conversion chip and the second analog-to-digital conversion chip under the synchronous window set.
Further, all synchronization window sets corresponding to the phase differences smaller than the preset threshold are obtained, and the average value of two data in each synchronization window set is calculated to obtain each position combination value, for example, the position combination value can be calculated by using the following formula (2)Wherein, the preset threshold value can be 200ps of one clock period:
Wherein, Representing the first bit of data in each set of synchronization windows as an optional location of the first analog-to-digital conversion chip,Representing the last bit of data in each set of synchronization windows, i.e., the optional location of the second analog-to-digital conversion chip.
Specifically, taking {7,8}, and {15,8} as examples of the synchronization window set of the first acquisition module B1, the synchronization window set of the first acquisition module B1 meeting the conditions is {7,8}, and averaging the 7 and 8 values to obtain the position combination value 7.5 of the first acquisition module B1.
Further, a plurality of position combination values of each acquisition module form a position combination sequence of each acquisition module.
Specifically, taking the position combination values 5.5 and 14 of the second acquisition module B2 as an example, the position combination sequence of the second acquisition module B2 is {5.5,14}.
In one embodiment, in step S22, the step of filling the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules may specifically include:
S221, determining an acquisition module corresponding to the position combination sequence with the largest data number as a reference acquisition module;
S222, according to the data number difference of the position combination sequences of the acquisition modules and the reference acquisition module, the position combination sequences of the acquisition modules are complemented.
It should be noted that, because the number of data in the obtained position combination sequences of the collecting modules is different, the number of data in the position combination sequences of the collecting modules is the same by firstly taking the position combination sequence containing the maximum number of data as a reference and supplementing the number of data in other position combination sequences.
In a specific implementation process, an acquisition module corresponding to the position combination sequence with the largest data number is determined as a reference acquisition module, and the data in the position combination sequences of other acquisition modules are supplemented to be equal to the data in the position combination sequence of the reference acquisition module in number. If the number of the position combination sequences with the largest data number is greater than 1, an acquisition module corresponding to any position combination sequence with the largest data number is selected as a reference acquisition module.
Further, calculating the absolute value of the difference between the first data in the position combination sequence of each other acquisition module and the first data in the position combination sequence of the reference acquisition module, calculating the absolute value of the difference between the last data in the position combination sequence of each other acquisition module and the last data in the position combination sequence of the reference acquisition module, comparing the two absolute values of the difference, if the absolute value of the difference between the first data is larger, adding M data with the same value as the first data before the first data in the position combination sequence of each other acquisition module, and if the absolute value of the difference between the last data is larger, adding M data with the same value as the last data after the last data in the position combination sequence of each other acquisition module. M is the absolute value of the data number difference value in the position combination sequence of other acquisition modules and the position combination sequence of the reference acquisition module.
In an exemplary embodiment, the position combination sequence of the first acquisition module B1 is {5.5,14}, the position combination sequence of the second acquisition module B2 is {5.5,14}, the position combination sequence of the third acquisition module B3 is {3.5,13}, the position combination sequence of the fourth acquisition module B4 is {3,12,15}, since the number of data in the position combination sequence of the fourth acquisition module B4 is the largest, the fourth acquisition module B4 is the reference acquisition module, for the first acquisition module B1, the absolute value of the difference between the calculated first data and the absolute value of the difference between the last data are respectively 2.5 and 1, and since 2.5 is greater than 1, the first data is added in a supplementary order, and the position combination sequence of the first acquisition module B1 after the supplementary is {5.5, 5.5,14 }. Similarly, the sequence of position combinations after the second acquisition module B2 is complemented is {5.5, 5.5,14}, and the sequence of position combinations after the third acquisition module B3 is complemented is {3.5,13, 13}.
In one embodiment, in step S23, the step of filling the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules may specifically include:
s231, calculating standard deviations of a plurality of same position data in the position combination sequence after the supplement of all the acquisition modules;
S232, determining the optimal synchronous window position of each analog-digital conversion chip in each acquisition module based on the size difference of each standard deviation.
In a specific implementation process, standard deviations of the same position data in the position combination sequence after the filling of all the acquisition modules are respectively calculated, wherein the number of the calculated standard deviations is the number of the data in the position combination sequence after the filling. It should be noted that the standard deviation may be used to characterize the degree of dispersion of the data.
In an exemplary embodiment, the position combination sequences after the filling of all the acquisition modules may first form a matrix, where the column number of the matrix is the data number in each position combination sequence after the filling, and the row number of the matrix is the number of the acquisition modules. And then, respectively calculating the standard deviation of each column of data in the matrix, namely, the standard deviation of a plurality of same position data in the position combination sequence after the compensation of all the acquisition modules.
In an exemplary embodiment, the sequence of position combinations after the first acquisition module B1 is aligned is {7.5,7.5}, the sequence of position combinations after the second acquisition module B2 is aligned is {8,8}, the sequence of position combinations after the third acquisition module B3 is aligned is {5.5,14}, the sequence of position combinations after the fourth acquisition module B4 is aligned is {5,13.5}, and the constituent matrices of the 4 acquisition modules are:
wherein, the standard deviation is calculated for two rows of data of the matrix to obtain 1.27 and 3.01 respectively.
Further, the position combination value of the acquisition module corresponding to the smallest standard deviation is selected, so that a synchronization window set of each acquisition module corresponding to each position combination value is obtained, and the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module is determined based on the synchronization window set of each acquisition module.
With reference to fig. 6, fig. 6 is a schematic diagram illustrating the optimal synchronization window positions of the analog-to-digital conversion chips in the above embodiment, and since 1.27 is smaller in 1.27 and 3.01, the position combination value of each acquisition module corresponding to the column in which 1.27 is located is selected first, for example, the first acquisition module B1 selects 7.5, and then the optimal synchronization window position of the first analog-to-digital conversion chip in the first acquisition module B1 and the optimal synchronization window position of the second analog-to-digital conversion chip are determined to be the 7 th bit and the 8 th bit respectively based on the position combination value 7.5. Fig. 7 is a schematic diagram of another embodiment of the optimal synchronization window position of each adc chip in each acquisition module, where in the window information shown in fig. 7, standard deviations obtained based on the above method are 0.83 and 1.14, and taking 0.83, the optimal synchronization window position of each adc chip in each acquisition module shown in the figure is obtained.
It should be noted that, the optimal synchronization window positions of the analog-to-digital conversion chips in each acquisition module obtained in this embodiment can meet the phase requirement of interleaving two analog-to-digital conversion chips in the same acquisition module, and meanwhile, the phase differences of the plurality of acquisition modules can be ensured to be consistent under different environments, for example, at different temperatures, so that the optimal synchronization window positions can be selected through calibration at different environmental temperatures, the acquisition time sequence synchronization between the two analog-to-digital conversion chips in each module and the phase relation between the multiple modules are ensured to be consistent, and the synchronization time sequence calibration of the multiple acquisition modules is realized.
On the basis of the above examples, fig. 8 is a block diagram of a multi-acquisition module synchronous timing calibration apparatus according to an embodiment of the present application, and as shown in fig. 8, the multi-acquisition module synchronous timing calibration apparatus may include a synchronization window set determining module 210, an optimal synchronization window position determining module 220, wherein,
The synchronization window set determining module 210 is configured to determine a plurality of synchronization window sets of each acquisition module based on window information provided by each analog-to-digital conversion chip for synchronous sampling;
the optimal synchronization window position determining module 220 is configured to determine an optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to a plurality of synchronization window sets of each acquisition module, where a processor of each acquisition module performs data sampling according to the optimal synchronization window position.
In an exemplary embodiment, the synchronization window set determining module 210 may be further configured to calculate a plurality of selectable positions included in the window information provided by each analog-to-digital conversion chip for synchronous sampling, and determine a plurality of synchronization window sets of each acquisition module based on the plurality of selectable positions of each analog-to-digital conversion chip in each acquisition module.
In an exemplary embodiment, the synchronization window set determining module 210 may be further configured to determine at least one selectable interval of each analog-to-digital conversion chip based on window information provided by each analog-to-digital conversion chip for synchronous sampling, and determine a plurality of selectable positions of each analog-to-digital conversion chip based on each selectable interval.
In an exemplary embodiment, the optimal synchronization window position determining module 220 may be further configured to determine a position combination sequence of each acquisition module according to a plurality of synchronization window sets of each acquisition module, supplement the position combination sequence of each acquisition module based on a data number difference of the position combination sequences of different acquisition modules, and determine an optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the position combination sequence of each acquisition module after supplement.
In an exemplary embodiment, the optimal synchronization window position determining module 220 may be further configured to determine, for any one of the acquisition modules, a phase difference between a plurality of analog-to-digital conversion chips under each of the synchronization window sets, determine a plurality of position combination values of the acquisition modules based on the synchronization window set corresponding to the phase difference being less than a preset threshold, and form the plurality of position combination values of each of the acquisition modules into a position combination sequence of each of the acquisition modules.
In an exemplary embodiment, the optimal synchronization window position determining module 220 may be further configured to determine an acquisition module corresponding to the position combination sequence with the largest number of data as a reference acquisition module, and fill in the position combination sequence of each acquisition module according to the difference in the number of data of the position combination sequences of each acquisition module and the reference acquisition module.
In an exemplary embodiment, the optimal synchronization window position determining module 220 may be further configured to calculate standard deviations of a plurality of identical position data in the position combination sequence after the position combination sequence is complemented by all the acquisition modules, and determine the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the magnitude difference of each standard deviation.
It should be understood by those skilled in the art that the division of each module in the embodiment is merely a division of a logic function, and may be fully or partially integrated onto one or more actual carriers in practical application, and the modules may be fully implemented in a form called by a processing unit through software, may be fully implemented in a form of hardware, or may be implemented in a form combining software and hardware, and it should be noted that each module in a multi-acquisition module synchronous timing calibration apparatus in the embodiment is in one-to-one correspondence with each step in a multi-acquisition module synchronous timing calibration method in the foregoing embodiment, so that a specific implementation of the embodiment may refer to an implementation of the foregoing multi-acquisition module synchronous timing calibration method and will not be repeated herein.
Based on the above embodiment, fig. 9 is a schematic structural diagram of a multi-acquisition module synchronous timing calibration apparatus according to an embodiment of the present application, as shown in fig. 9, the electronic apparatus may include a processor (processor) 310, a communication interface (Communications Interface) 320, a memory (memory) 330, and a communication bus 340, where the processor 310, the communication interface 320, and the memory 330 complete communication with each other through the communication bus 340. The processor 310 may invoke logic instructions in the memory 330 to perform a method for calibrating synchronous timing of multiple acquisition modules, where the method includes determining multiple synchronous window sets of each acquisition module based on window information provided by each analog-to-digital conversion chip for synchronous sampling, and determining an optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronous window sets of each acquisition module, where the processor of each acquisition module performs data sampling according to the optimal synchronous window position.
Further, the logic instructions in the memory 330 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.
On the basis of the embodiment, in another aspect, the invention further provides a computer program product, which comprises a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and when the computer program is executed by a processor, the computer program can execute the multi-acquisition-module synchronous time sequence calibration method provided by the method, and the method comprises the steps of determining a plurality of synchronous window sets of each acquisition module based on window information provided by each analog-to-digital conversion chip and used for synchronous sampling, determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the plurality of synchronous window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronous window position.
On the basis of the embodiment, in yet another aspect, the invention further provides a non-transitory computer readable storage medium, on which a computer program is stored, the computer program being implemented when executed by a processor to perform the method for calibrating synchronous timing of multiple acquisition modules provided by the methods, the method comprising determining multiple synchronous window sets of each acquisition module based on window information provided by each analog-to-digital conversion chip for synchronous sampling, determining an optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronous window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronous window position.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
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| CN104980156A (en) * | 2015-05-21 | 2015-10-14 | 熊猫电子集团有限公司 | Field programmable gate array (FPGA) based high-speed analog-digital converter (ADC) synchronous acquisition system |
| CN107425854A (en) * | 2017-09-04 | 2017-12-01 | 中国电子科技集团公司第四十研究所 | A kind of method for lifting multi-channel A/D C interleave samples system synchronization resetting stabilities |
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| JPH0628340B2 (en) * | 1985-12-24 | 1994-04-13 | ソニ−・テクトロニクス株式会社 | Calibration method for analog / digital converter |
| CN114024549B (en) * | 2022-01-04 | 2022-04-15 | 普源精电科技股份有限公司 | Time domain interleaving analog-to-digital converter synchronization device and method |
| CN118971880B (en) * | 2024-08-19 | 2025-04-08 | 成都玖锦科技有限公司 | Automatic synchronous time sequence calibration method, device, storage medium and equipment |
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| CN104980156A (en) * | 2015-05-21 | 2015-10-14 | 熊猫电子集团有限公司 | Field programmable gate array (FPGA) based high-speed analog-digital converter (ADC) synchronous acquisition system |
| CN107425854A (en) * | 2017-09-04 | 2017-12-01 | 中国电子科技集团公司第四十研究所 | A kind of method for lifting multi-channel A/D C interleave samples system synchronization resetting stabilities |
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