Detailed Description
Embodiments of the present application will be described in detail below, examples of which are illustrated in the accompanying drawings, but unnecessary detailed description may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of the actual same structure may be omitted. This is to avoid that the following description becomes unnecessarily lengthy, facilitating the understanding of those skilled in the art. Furthermore, the drawings and the following description are provided for a full understanding of the present application by those skilled in the art, and are not intended to limit the subject matter recited in the claims.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs, and the terms used herein are used for the purpose of describing particular embodiments only and are not intended to limit the application, and unless otherwise indicated, the numerical values of the various parameters set forth herein may be measured by various methods of measurement commonly used in the art (e.g., may be tested according to the methods set forth in the embodiments of the application).
The terms "comprising" and "having" and any variations thereof, as used in the description and claims, are intended to be open-ended, i.e., to encompass the pointed out aspects of the application, and not to exclude other aspects.
In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "width", "thickness", etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The "first feature" and "second feature" may include one or more of the features.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In the description of the present application, unless expressly stated or limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present application, "plurality" means two or more.
In the description of the present application, "a and/or B" may include any of the cases of a alone, B alone, a and B, wherein A, B is merely for example, which may be any technical feature of the present application that uses "and/or" connection.
In the description of the present application, "parasitic absorption" means that in a solar cell, a portion of light is absorbed without being effectively converted into electric energy due to the characteristics of materials. This phenomenon may reduce the photoelectric conversion efficiency of the battery.
In the description of the present application, by "ohmic contact" is meant a contact between two different materials, the resistance of which is very small and through which a current can pass. In solar cells, good ohmic contact helps to reduce the contact resistance of the cell and improve the cell performance.
All embodiments of the application and alternative embodiments may be combined with each other to form new solutions, unless otherwise specified.
TOPCon (tunnel oxide passivation contact) cell is a novel solar cell technology with high efficiency and excellent performance. However, for TOPCon cells, there is a problem of high parasitic absorption in the back side tunnel oxide passivation contact structure.
In order to overcome the problem, the application prepares the tunneling oxide passivation contact structure of the silicon oxide layer/the doped polysilicon layer/the transparent conductive layer by sequentially depositing the silicon oxide layer, the doped polysilicon layer and the transparent conductive layer on the silicon substrate of the solar cell, thereby reducing parasitic absorption, improving current density and further improving the performance of the solar cell.
Based on this, in a first aspect of the present application, the present application proposes a tunneling oxide passivation contact structure. According to an embodiment of the present application, referring to fig. 1, the tunneling oxide passivation contact structure 102 includes a silicon oxide layer 2, a doped polysilicon layer 3, the doped polysilicon layer 3 being disposed on one side of the silicon oxide layer 2, and a transparent conductive layer 5, the transparent conductive layer 5 being disposed on a side of the doped polysilicon layer 3 remote from the silicon oxide layer 2. Therefore, the transparent conductive layer in the tunneling oxide passivation contact structure can reduce parasitic absorption due to high transparency, allows more light to penetrate through the cell and be absorbed by the active region, and provides an effective current collection path, so that the current density is improved, and the transmittance, the current density, the carrier concentration and the photoelectric conversion efficiency of the solar cell are further improved.
In some embodiments, the transparent conductive layer is made of a material selected from at least one of tin dioxide and zinc dioxide. According to the tunneling oxide passivation contact structure provided by the embodiment of the application, the tin dioxide and the zinc dioxide can form the transparent conductive layer and can be burnt through by the low-temperature silver paste, so that the low-temperature silver paste and the doped polysilicon layer form ohmic contact. Therefore, the tunneling oxide passivation contact structure can improve the transmittance, current density, carrier concentration and photoelectric conversion efficiency of the solar cell.
In some embodiments, the transparent conductive layer has a thickness of 50nm to 200nm, for example 50nm、51nm、55nm、56nm、57nm、58nm、59nm、60nm、61nm、62nm、63nm、64nm、65nm、70nm、80nm、90nm、100nm、120nm、140nm、160nm、180nm、190nm、193nm、195nm、196nm、197nm、198nm、199nm、200nm and any range between any two of them, such as 50nm to 199nm, 50nm to 198nm, 50nm to 197nm, 50nm to 196nm. According to the tunneling oxide passivation contact structure provided by the embodiment of the application, the thickness of the transparent conductive layer is moderate, the parasitic absorption is reduced, more light is allowed to penetrate through the cell and be absorbed by the active region, and an effective current collection path is provided, compared with the doped polysilicon layer which can be burnt through by low-temperature silver paste, so that ohmic contact is formed between the low-temperature silver paste and the doped polysilicon layer. Therefore, the tunneling oxide passivation contact structure can improve the transmittance, current density, carrier concentration and photoelectric conversion efficiency of the solar cell.
In some embodiments, the doped polysilicon layer has a thickness no greater than 10nm, such as 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or ranges therebetween, ranging from 1 to 9nm, 1 to 8nm, and 1 to 7nm. In the range, according to the tunneling oxide passivation contact structure, the excessively thick doped polysilicon layer can increase light absorption, so that the light quantity reaching an active area of a battery is reduced, the resistance of current in a transmission process is increased, the photoelectric conversion efficiency of the battery is affected, the excessively thin doped polysilicon layer can not provide sufficient electrical contact, the collection efficiency of holes is affected, the insufficient surface passivation is caused by the excessively thin doped polysilicon layer, the surface state density is increased, and the surface recombination of carriers is increased. Therefore, the doped polycrystalline silicon layer with moderate thickness can improve the transmittance, current density, carrier concentration and photoelectric conversion efficiency of the solar cell.
In some embodiments, the doped polysilicon layer is a p-type doped polysilicon layer for collecting and transporting holes.
In some embodiments, the silicon oxide layer thickness is 1-2 nm or a range between them. In this range, according to the embodiment of the application, too thick silicon oxide layer can increase the difficulty of hole tunneling, reduce tunneling efficiency, reduce hole collection, increase the resistance of back contact, affect the series resistance and overall performance of the battery, and affect the absorption of light by the battery, and too thin silicon oxide layer can not provide sufficient surface passivation to increase the surface state density, thereby increasing the surface recombination of carriers and not effectively protecting the silicon substrate from corrosion of environmental factors (such as moisture and oxygen) and affecting the long-term stability of the battery. Therefore, the silicon oxide layer with moderate thickness can provide good interface passivation performance of the tunneling oxide layer passivation contact structure, reduce the surface recombination rate of the structure and improve the transmittance, current density, carrier concentration and photoelectric conversion efficiency of the solar cell.
In a second aspect of the present application, a method for preparing the aforementioned tunneling oxide passivation contact structure is provided. According to an embodiment of the application, the method comprises the steps of performing a silicon oxide deposition process to form a silicon oxide layer, performing a doped polysilicon deposition process on one side of the silicon oxide layer to form a doped polysilicon layer, and performing a transparent conductive layer deposition process on the side of the doped polysilicon layer away from the silicon oxide layer to form a transparent conductive layer. According to the method provided by the embodiment of the application, the tunneling oxide passivation contact structure for improving the mobility, carrier concentration, transmittance and photoelectric conversion efficiency of the solar cell can be prepared.
According to an alternative embodiment of the present application, the specific preparation method may refer to fig. 2, and fig. 2 includes the steps of preparing and forming a silicon oxide layer in step S100, preparing and forming a doped polysilicon layer on the silicon oxide layer in step S200, and depositing a transparent conductive layer on the doped polysilicon layer in step S300.
In some embodiments, after the transparent conductive layer deposition process, further comprising annealing the transparent conductive layer.
In some embodiments, the annealing is performed at a temperature of 150-250 ℃.
In some embodiments, the annealing is performed at a treatment time of 10 to 30 minutes.
In some embodiments, the material of the transparent conductive layer is selected from tin dioxide, which is provided in the form of a tetra (dimethylamino) tin source.
In some embodiments, the transparent conductive layer deposition process is performed at a temperature of 70-150 ℃, a flow rate of tetra (dimethylamino) tin source of 90-110 slm, and a cycle number of not less than 500.
In some embodiments, the transparent conductive layer is prepared by at least one of chemical vapor deposition or physical vapor deposition. Illustratively, tin dioxide is deposited on the surface of the silicon wafer by chemical reaction. Illustratively, the tin dioxide layer is formed by depositing tin dioxide on the surface of the silicon wafer by a physical process, such as thermal evaporation or sputtering, or a chemical process, such as Atomic Layer Deposition (ALD).
In some embodiments, the silicon oxide deposition process is performed at a temperature of 530-570 ℃, an oxygen flow of 8-12 slm, and a time of 8-12 min.
In some embodiments, the silicon oxide layer is prepared by at least one of thermal oxidation, plasma enhanced chemical vapor deposition, and low pressure vapor deposition. Illustratively, a silicon oxide layer is formed on the surface of a silicon oxide wafer by high temperature. Illustratively, the silicon oxide layer is deposited in a plasma environment. Illustratively, a silicon oxide layer is deposited on the surface of a silicon wafer by chemical reaction. Illustratively, the silicon oxide layer is deposited in a low pressure environment.
In some embodiments, the doped polysilicon deposition process is performed at a temperature of 550-590℃, siH 4 at a flow rate of 90-110 slm for 10-30 minutes.
In some embodiments, the method of preparing the doped polysilicon layer is at least one of chemical vapor deposition or physical vapor deposition. Illustratively, doped polysilicon is deposited on the surface of the silicon wafer by chemical reaction. Illustratively, doped polysilicon is deposited on the surface of the silicon wafer by a physical process, such as thermal evaporation or sputtering, or a chemical process, such as Low Pressure Chemical Vapor Deposition (LPCVD).
In a third aspect of the present application, the present application provides a solar cell, including the tunnel oxide passivation contact structure according to the first aspect of the present application. The mobility, carrier concentration, transmittance and photoelectric conversion efficiency of the solar cell according to the embodiment of the application are improved.
In some embodiments, the solar cell is TOPCon cells. The TOPCon battery according to the embodiment of the application has improved mobility, carrier concentration, transmittance and photoelectric conversion efficiency.
In some embodiments, the solar cell is an n-type TOPCon cell.
In some embodiments, TOPCon cells of the present application may employ structures known in the art on the light-receiving side.
According to an alternative embodiment of the present application, referring to fig. 3, the structure of TOPCon battery 100 of the present application includes:
The light-receiving surface of the crystalline silicon substrate 1 is sequentially laminated with an emitter layer 12, a front passivation layer 13, a front antireflection layer 14 and a front electrode 15, and the backlight surface of the crystalline silicon substrate 11 is sequentially laminated with a silicon oxide layer 2, a doped polysilicon layer 3, a transparent conductive layer 5, a back antireflection layer 18 and an electrode 4, wherein the electrode 4 penetrates the back antireflection layer 18 and the transparent conductive layer 5 to be in contact with the doped polysilicon layer 3, and the front electrode 15 penetrates the front antireflection layer 14 and the front passivation layer 13 to be in contact with the emitter layer 12.
The emitter layer 12, the front passivation layer 13, the front anti-reflection layer 14 and the front electrode 15 may all be provided using materials or thicknesses known in the art.
In some embodiments, the silicon substrate in TOPCon cells comprises n-type crystalline silicon. The n-type crystalline silicon has higher electron mobility, which is helpful for improving the mobility of electrons in the material, has lower resistivity, is helpful for reducing the loss of current, is sensitive to light, and has wide application in photoelectric devices, such as solar cells. The silicon substrate may be, but is not limited to, a monocrystalline silicon wafer. The silicon substrate may be doped with N-type dopant such as phosphorus (P) dopant or P-type dopant such as boron (B) dopant. In one example, the silicon substrate is N-doped.
The crystalline silicon substrate 1 may be N-type monocrystalline silicon or textured N-type monocrystalline silicon. Those skilled in the art will appreciate that when the crystalline silicon substrate has a textured structure, the other layers on the solar cell are also textured.
In a fourth aspect of the application, the application proposes a photovoltaic module comprising at least one cell string comprising at least two of the aforementioned solar cells.
In some embodiments, the solar cells may be connected together by series welding, so that the electrical energy generated by the individual solar cells is collected for subsequent delivery.
In some embodiments, the solar cells may be arranged at intervals, or may be stacked together in a shingle manner.
The photovoltaic module further comprises an encapsulation layer for covering a surface of the cell string, and a cover plate for covering a surface of the encapsulation layer remote from the cell string.
In a fifth aspect of the present application, the present application provides a photovoltaic system comprising the aforementioned photovoltaic module.
The photovoltaic system can be applied to a photovoltaic power station, such as a ground power station, a roof power station, a water surface power station and the like, and can also be applied to equipment or devices for generating power by utilizing solar energy, such as a user solar power supply, a solar street lamp, a solar automobile, a solar building and the like. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system may be applied to all fields where solar energy is required to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system can comprise a photovoltaic array, a confluence box and an inverter, wherein the photovoltaic array can be an array combination of a plurality of photovoltaic modules, for example, the photovoltaic modules can form a plurality of photovoltaic arrays, the photovoltaic arrays are connected with the confluence box, the confluence box can confluence currents generated by the photovoltaic arrays, and the confluence currents flow through the inverter to be converted into alternating currents required by a commercial power grid and then are connected with the commercial power network so as to realize solar power supply.
The following description of the present application is made by way of specific examples, which are given for illustration of the present application and should not be construed as limiting the scope of the application. The examples are not to be construed as limiting the specific techniques or conditions described in the literature in this field or as per the specifications of the product. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
Example 1
This example shows the preparation process of TOPCon cell with transparent conductive layer being tin dioxide layer, the preparation process is as follows:
The back surface preparation step:
(1) And (3) alkali etching, namely alkali etching the n-type monocrystalline silicon by a wet method to remove surface residues and pollutants, so that the surface of the silicon wafer is leveled.
(2) RCA cleaning-the surface residues and contaminants are further removed using a standard RCA (Radio Corporation of America) cleaning procedure to obtain a clean and planar silicon substrate.
(3) And (3) thermal oxidation, namely forming a silicon oxide layer with the thickness of 1.5nm on a silicon substrate in a thermal oxidation mode, wherein the condition is 550 ℃, the high-purity oxygen is 10slm, and the process time is 10 minutes.
(4) And (3) depositing a doped polysilicon layer, namely depositing the doped polysilicon layer on the silicon oxide layer, wherein the thickness is 10nm, the temperature is 570 ℃, the flow rate of SiH 4 is 100sccm, and the deposition time is 20 minutes.
(5) And (3) screen printing, namely printing silver paste on the doped polysilicon layer through screen printing to form the metal gate line electrode.
(6) And (3) fluorine-containing gas etching, namely etching the doped polysilicon layer of the non-metal area by using the fluorine-containing gas, and removing the doped polysilicon layer of the non-metal area or reserving 1-20 nm.
(7) And (3) depositing a transparent conductive layer, namely depositing a tin dioxide layer on the doped polycrystalline silicon layer by an ALD (atomic layer deposition) method, wherein the deposition condition is 100 ℃ and 500 times of circulation, so as to prepare the tin dioxide transparent conductive layer with the thickness of 60nm, and then annealing for 20 minutes at 200 ℃.
Front preparation step:
(8) And (3) surface polishing, namely mechanically polishing the surface of the silicon wafer to ensure no damage and flatness.
(9) And (3) chemically cleaning, namely removing cutting fluid residues and surface dirt on the surface of the silicon wafer.
(10) And (3) texturing treatment, namely alkaline texturing.
(11) Surface oxidation, forming a thin silicon oxide layer as a passivation layer on the front surface.
(12) And nitriding, namely forming a silicon nitride layer on the silicon oxide layer to serve as a passivation layer on the front surface.
(13) Front electrode formation the front electrode area is defined using photolithographic and etching techniques.
(14) And (5) metallization, namely depositing a metal layer in the front electrode area to form a metal grid line electrode.
(15) Sintering, namely sintering the metal grid electrode to improve the adhesive force and the conductivity.
(16) And (3) depositing a silicon nitride anti-reflection layer on the front surface.
Through the steps, the TOPCon battery with excellent performance is prepared, the back surface is provided with a tunneling oxide layer passivation contact structure, and the front surface is provided with an optimized electrode and a passivation layer, so that high-efficiency photoelectric conversion is realized.
Example 2
Example 2 was essentially the same as example 1 except that the doped polysilicon layer was 5nm thick and the other preparation processes were the same as example 1.
Example 3
Example 3 the experimental procedure is essentially the same as example 1, except that tetra (dimethylamino) tin is replaced as a precursor chemical with diethyl zinc precursor chemical, the tin dioxide layer prepared becomes a zinc dioxide layer, and the other preparation procedures are the same as example 1.
Example 4
Example 4 was essentially the same as the experimental procedure of example 1, except that the doped polysilicon layer had a thickness of 20nm, and the other preparation procedures were the same as example 1.
Example 5
Example 5 was essentially the same as the experimental procedure of example 1, except that the doped polysilicon layer had a thickness of 50nm, and the other preparation procedures were the same as example 1.
Example 6
Example 6 was essentially the same as example 1 except that the doped polysilicon layer was 100nm thick and the other preparation processes were the same as example 1.
Example 7
Example 7 was substantially the same as the experimental procedure of example 1, except that the transparent conductive layer had a thickness of 50nm, and the other preparation procedures were the same as example 1.
Example 8
Example 8 was substantially the same as the experimental procedure of example 1, except that the transparent conductive layer had a thickness of 200nm, and the other preparation procedures were the same as example 1.
Comparative example 1
Comparative example 1 the experimental procedure was essentially the same as example 1, except that the doped polysilicon layer had a thickness of 200nm, no tin dioxide transparent conductive layer was deposited, and the other preparation processes were the same as example 1.
The solar cells obtained in examples 1 to 8 and comparative example 1 were subjected to transmittance, current density, carrier concentration, and photoelectric conversion efficiency tests using a UV-visible spectrophotometer, current density, carrier concentration were tested using a hall effect tester, and photoelectric conversion efficiency was tested using SintonFCT-650, and the test results are shown in table 1, following the IEC 61730 standard.
TABLE 1
Example 1 compared with example 3, the prepared tin dioxide layer becomes a zinc dioxide layer by replacing tetra (dimethylamino) tin as a precursor chemical with diethyl zinc precursor chemical, and the transmittance, current density, carrier concentration and photoelectric conversion efficiency of both solar cells are higher.
Compared with examples 4-6, the thickness of the doped polysilicon layer in examples 1 and 2 is increased, the transmittance tends to be obviously decreased, and the current density is also reduced, and the parasitic absorption is more serious mainly because the doped polysilicon layer is thickened, thereby affecting the capture of photons by the silicon substrate, further affecting the current and the electrical performance of the battery, and indicating that the thickness of the doped polysilicon layer not more than 10nm is more beneficial to improving the transmittance, the current density, the carrier concentration and the photoelectric conversion efficiency of the solar battery.
In example 1, example 7 and example 8, the transmittance, current density, carrier concentration and photoelectric conversion efficiency of the solar cell were higher when the thickness of the transparent conductive layer was 50nm to 200 nm.
Example 1 has higher transmittance, current density, carrier concentration and photoelectric conversion efficiency than those of the solar cell prepared without tin dioxide deposition on the doped polysilicon layer compared with comparative example 1, which demonstrates that depositing a transparent conductive layer on the doped polysilicon layer can reduce parasitic absorption and thus improve the performance of the solar cell.
The photovoltaic module provided by the embodiment of the application comprises the passivation contact solar cell provided by the embodiment. Since the photovoltaic module includes the passivation contact solar cell provided by the above embodiment, it has the same beneficial effects and will not be described herein.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.