CN119173876A - Method and apparatus for electronic design automation - Google Patents

Abstract

Embodiments of the present disclosure relate to the field of electronic design automation and provide methods and apparatus for electronic design automation. Logic optimization is performed on boolean logic representing the circuit to obtain optimized boolean logic. The boolean logic is process mapped to obtain a netlist representing the circuit. And performing netlist optimization on the netlist to obtain an optimized netlist. In response to determining that the optimized netlist is better than the locally optimal netlist representing the circuit, the locally optimal netlist is replaced with the optimized netlist, and the optimized netlist is process mapped. In this way, the efficiency of logic synthesis can be significantly improved.

Description

Method and apparatus for electronic design automation Technical Field

Embodiments of the present disclosure relate to electronic design automation (Electronic Design Automation, EDA), and more particularly to methods and apparatus for electronic design automation.

Background

In the design flow of integrated circuits, logic synthesis is a key link in terms of circuit performance (smaller, faster, and more energy-efficient). Logic synthesis converts the high-level abstract description of the designed digital circuit into a logic gate-level circuit connection netlist after Boolean function simplification and optimization. The existing logic synthesis process is optimized on the premise of meeting design constraint after a register conversion stage circuit described by a hardware description language is converted into a Boolean circuit. The delay and area of the circuit are two important optimization objectives, and the delay and area are closely related to the circuit level and the number of nodes, respectively.

The optimization process of logic synthesis typically includes logic optimization, mapping, and netlist optimization. The optimization is a problem that NP is difficult, and the existing method realizes the optimization purpose of each stage by iteratively calling different local or global optimization operators. The operators are designed differently, and the optimization target effect is also different. The final logic comprehensive optimization effect is very dependent on the operator sequence and parameters thereof, and the arrangement and combination space of the operators and the parameters thereof is huge.

Disclosure of Invention

Embodiments of the present disclosure provide an electronic design automation scheme, and in particular, a logic synthesis scheme.

In a first aspect of the present disclosure, a method of electronic design automation is provided. In the method, a boolean logic representing a circuit is logically optimized to obtain optimized boolean logic. The boolean logic is process mapped to obtain a netlist representing the circuit. And performing netlist optimization on the netlist to obtain an optimized netlist. In response to determining that the optimized netlist is better than the locally optimal netlist representing the circuit, the locally optimal netlist is replaced with the optimized netlist, and the optimized netlist is process mapped.

Besides the outer layer iteration of the traditional logic optimization, process mapping and netlist optimization, the convergence speed can be increased and the optimization effect of logic synthesis can be improved through the process mapping and netlist optimization inner layer iteration facing the final netlist performance.

In each iteration, the operator sequence may be specified through expert experience, or operator combinations and parameters may be dynamically recommended by means of algorithms such as data driving. Meanwhile, refined circuit features are designed to accurately model the circuit state and are used for operator dynamic recommendation.

In a second aspect of the disclosure, the disclosure provides an apparatus. The apparatus includes a processor and a memory coupled to the processor and containing instructions stored thereon that, when executed by the processor, cause the apparatus to perform the method in the first aspect of the disclosure.

In a third aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program/instruction which when executed by a processor implements the steps of the method in the first aspect of the present disclosure.

In a fourth aspect of the present disclosure, there is provided a computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method in the first aspect of the present disclosure.

The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the disclosure.

Fig. 1 illustrates a flow chart of a method for designing an integrated circuit according to some embodiments of the present disclosure.

Fig. 2 illustrates a schematic flow diagram of a logic synthesis method according to some embodiments of the present disclosure.

Fig. 3 illustrates a schematic flow diagram of a logic synthesis method according to some embodiments of the present disclosure.

Fig. 4 illustrates a schematic flow diagram of a logic synthesis method according to some embodiments of the present disclosure.

Fig. 5 shows a schematic block diagram of an apparatus that may be used to implement embodiments of the present disclosure.

The various features shown in the drawings may not be drawn to scale according to common practice. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some figures may not depict all of the components of a given system, method, or apparatus. Finally, like reference numerals may be used to denote like features throughout the specification and figures.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below.

In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.

Fig. 1 illustrates a flow chart of a method 100 for designing a semiconductor chip according to some embodiments of the present disclosure. The method 100 may be implemented at least in part by an electronic design automation (Electronic Design Automation, EDA) tool. At block 102, the functional requirements of the chip are defined. The Chip may be a processor, a memory Chip, or a System on Chip (SoC) having multiple components. Functional requirements may include the nature of the chip and the performance goals of the chip.

At block 104, an Electronic system level (Electronic SYSTEM LEVEL, ESL) description is generated based on the functional requirements of the chip. The electronic system level description focuses on a higher level of abstraction without regard to lower level implementations. The goal of ESL description is to increase the likelihood of successful implementation of the function. An appropriate abstraction is used to generate a global level of understanding of the chip to be designed.

At block 106, a register conversion stage (REGISTER TRANSFER LEVEL, RTL) description is generated from the ESL description. The RTL description is a description of the semiconductor chip design in terms of its operation. Specifically, the behavior of the circuit is defined in terms of the signal flow between hardware registers in the RTL description. For example, a hardware description language (Hardware Description Language, HDL) may be used to create a high-level representation of the circuit from which low-level representations and ultimately the actual discrete devices and wiring may be derived.

At block 108, the RTL description of the chip is logically integrated, e.g., the RTL description in HDL form of the chip is converted to a gate level description of the chip. Specifically, the gate level description is a discrete netlist of logic gate primitives, i.e., netlist 110. After netlist 110 is obtained, netlist 110 may be simulated to determine whether the design fulfills a predetermined function or design intent, also referred to as "pre-simulation" or "pre-layout simulation".

At block 112, the chip is physically designed based on netlist 110 to construct a physical layout of the chip. For example, components such as logic gates may be placed and wired to provide interconnections between the signal and power terminals of the components. In this way, a chip layout 114 may be constructed.

At block 116, the layout 114 is physically verified. For example, a design rule check (Design Rule Check, DRC) may be performed on the layout 114. The layout is drawn according to design rules, which may be provided by a wafer fab. In the design rule check, it is checked whether the drawing of the layout 114 satisfies the corresponding design rule.

After the layout 114 passes the design rule check, there may be errors in the layout 114 that are not caused by violating the design rule, but may be caused by inconsistencies with the circuit diagram. For example, the layout 114 may lack a wire, and such a small defect may be fatal to the entire chip. Thus, a layout-to-schematic comparison (Layout Versus Schematic, LVS), also known as a consistency check, may also be performed on the layout 114. In the correspondence check, a netlist is extracted from the layout 114 and the extracted netlist is compared to the netlist 110 to ensure that the extracted netlist is consistent with the netlist 110. In addition, parasitic parameter extraction (PARASITIC EXTRACTION, PEX) may also be performed on the layout 114. In the parasitic parameter extraction, parasitic parameters such as resistance and capacitance may be extracted from the layout 114, and a netlist including the parasitic parameters, also referred to as a parasitic parameter netlist, may be output.

At block 118, a simulation, also referred to as a "post-simulation" or "post-layout simulation," is performed on the netlist containing the parasitic parameters. Thus, the parasitic parametric netlist for post simulation is also referred to as a post-simulated netlist. In post-simulation, the response of the actual digital circuit and/or analog circuit is simulated by constructing an accurate analog model of the circuit.

At block 118, layout 114 may be post-processed. For example, a structure such as a seal ring may be added, and resolution enhancement techniques may be applied. After layout post-processing, mask data 120 may be generated for final chip fabrication.

It should be understood that fig. 1 only shows a schematic flow chart of an IC design. In some embodiments, steps may be added, deleted, or the order of some of the steps may be modified.

Fig. 2 illustrates a schematic flow diagram of a logic synthesis method 200 according to some embodiments of the present disclosure. For example, the logic synthesis method 200 may be implemented at block 108 as shown in fig. 1.

The initial netlist 202 may be an RTL description of the chip, e.g., a representation of the HDL language. For example, the initial netlist 202 may be determined from an RTL description (e.g., HDL description) of the chip.

At block 204, a logic optimization is performed on the initial netlist 202. Logic optimization means that logic of the Boolean circuit is optimized, simplified and the like, and belongs to process independent optimization. For example, the logic of a boolean circuit may be represented by a boolean function, a logic graph, etc., wherein examples of logic graphs include a nand graph (nd-INVERTER GRAPH, AIG), a Majority inverter graph (Majority-INVERTER GRAPH, MIG), etc.

In performing logic optimization on the initial netlist 202, the initial netlist 202 may first be converted into a representation of logic of a boolean circuit, e.g., a representation of a boolean function, a logic graph, etc. The logic of the boolean circuit is then optimized using one or more logic optimization operators.

In some embodiments, at block 204, a logic optimization operator sequence may be invoked to optimize a logic diagram. Operators may represent optimization methods and their parameters. For example, the logically optimized operator sequence may be empirically set, or may be dynamically determined by means of algorithms such as random search, simulated annealing, reinforcement learning, bayesian optimization, etc., given the operator set and parameter ranges.

At block 206, a process map is performed on the Boolean logic representing the circuit to determine a netlist representing the circuit. The process map maps the logical structure equivalence of the boolean circuit into an achievable gate level circuit structure. For example, the process map may be a look-up Table (LUT) map, a standard cell map, or the like. In some embodiments, a sequence of process mapping operators may be invoked to perform process mapping. For example, the process map operator sequence may be empirically set, or may be dynamically determined by means of algorithms such as random search, simulated annealing, reinforcement learning, bayesian optimization, etc., given the operator set and parameter ranges.

At block 208, netlist optimization is performed on the netlist representing the circuit to obtain an optimized netlist. In some embodiments, a netlist optimization operator sequence may be invoked to perform netlist optimization. For example, the netlist optimization operator sequence may be empirically set, or may be dynamically determined by means of algorithms such as random search, simulated annealing, reinforcement learning, bayesian optimization, etc., given a set of operators and a range of parameters.

At block 210, a determination is made as to whether a mapping iteration is to be performed. For example, it may be determined whether to continue the iterative loop of process map-netlist optimization based on preset configurations such as historical circuit features, operator operating states, and iteration termination conditions. This cycle is also referred to as the inner layer cycle.

In the inner layer circulation, the Performance, power and Area (PPA) of the mapped netlist are taken as main optimization targets, so that the convergence speed is increased. In performing the inner loop of process mapping and netlist optimization, if the netlist obtained after performing blocks 206 or 208 is better than the local optimal netlist 216, the netlist is used in place of the local optimal netlist 216 to update the local optimal netlist 216.

At block 210, the circuit features of the final netlist and the current netlist from the previous inner-layer iteration may be analyzed to determine whether to continue performing the inner-layer iteration. If it is determined at block 210 to continue with the inner layer iteration, the current netlist is passed to block 206 and the inner layer loop is continued to be executed. If it is determined at block 210 that no more inner layer iterations are to be performed, then the locally optimal netlist is passed to block 212.

In some embodiments, at block 210, the search deterioration times or the pre-set number of loops may be advanced by counting the current netlist differences from the local optimal netlist. If the search deterioration times or the circulation times reach the threshold value, the output is no, otherwise, the output is yes.

At block 212, it is determined whether to continue executing the outer loop based on preset configurations such as historical circuit characteristics, operator run state, and iteration termination conditions. In some embodiments, it is determined whether to continue performing the outer layer iteration by analyzing circuit features of the locally optimal netlist and the current locally optimal netlist of previous outer layer iterations. If the current local optimal netlist is better than the global optimal netlist, replacing the global optimal netlist with the current local optimal netlist. If its output is, then the globally optimal netlist is passed to a block 204. If not, the globally optimal netlist is output as a final synthesized netlist 214.

In some embodiments, all of the operational profiles required to perform process-independent logical synthesis, in particular operator and parameter settings, constraints, process libraries 220, and optimization objectives and iteration termination conditions 222, may be contained in the configuration file 218. Operator and parameter settings, constraints, and process libraries 220 comprise operator pools for logic optimization, process mapping, and netlist optimization stages, and their associated parameters, approximate correspondence of associated parameters with optimization effects, constraints such as maximum area, maximum delay, etc., and process device libraries required for mapping and netlist optimization. The optimization objectives and iteration termination conditions 222 include weights of key optimization objectives such as delay, area, run time, etc., run time, iteration number, optimization objective constraints, sag to constraint conflicts, etc., and the like.

Feature extraction and operator recommendation 224 may obtain the current circuit state from blocks 204, 206, or 208 and determine the operator sequence at the next iteration based on the optimization results of the historical operator sequences to recommend to blocks 204, 206, or 208, respectively. The refined circuit features comprise circuit node number, critical path length and other circuit statistical features, fine granularity operator profit distribution and the like. In determining the operator sequence, feature extraction and operator recommendation 224 may obtain relevant configuration information in configuration file 218, such as operator and parameter settings, constraints, process library 220, and optimization objectives and iteration termination conditions 222. In one embodiment, the feature extraction and operator recommendation 224 may dynamically determine the operator sequence at the next iteration by means of algorithms such as random search, simulated annealing, reinforcement learning, bayesian optimization, etc., given the operator set and parameter ranges.

Fig. 3 illustrates a schematic flow diagram of a logic synthesis method 300 according to some embodiments of the present disclosure. Method 300 may be a particular embodiment of method 200.

In fig. 3, the logic optimization includes block 303 and block 304, wherein in block 303, an area-first logic optimization is performed, e.g., the area-first logic optimization optimizes the boolean logic of the circuit using an area-first logic optimization operator sequence, and in block 304, a hierarchy-first logic optimization is performed, e.g., the hierarchy-first logic optimization optimizes the boolean logic of the circuit using a hierarchy-first logic optimization operator sequence. For example, block 303 may optimize the logic diagram area without deteriorating the hierarchy. In some cases, block 303 may optimize both the area and the hierarchy of the logic diagram. For example, block 304 may optimize the logic diagram hierarchy, but may exacerbate the logic diagram area. In some cases, block 304 may optimize both the area and the hierarchy of the logic diagram.

In fig. 3, the process map includes blocks 305 and 306, wherein in block 305, an area-first process map is performed, e.g., the area-first process map uses an area-first process map operator sequence to perform the process map, and in block 306, a hierarchy-first process map 306 is performed, e.g., the hierarchy-first process map uses a hierarchy-first process map operator sequence to perform the process map. For example, block 305 may be an area-first LUT netlist process map, but may corrupt the hierarchy. Block 306 may be a hierarchical priority LUT netlist process map, but may deteriorate area. In some cases, block 306 may optimize both area and hierarchy.

In FIG. 3, netlist optimization includes block 307 and block 308, wherein in block 307, area-first netlist optimization is performed, e.g., area-first netlist optimization is performed using an area-first netlist optimization operator sequence, and in block 308, hierarchical-first netlist optimization is performed, e.g., hierarchical-first netlist optimization is performed using a hierarchical-first netlist optimization operator sequence.

In blocks 303-308, operator combinations may be set according to expert experience, or operator sequences in any of blocks 303-308 may be dynamically searched for given operator sets and parameter ranges, invoking algorithms such as random search, simulated annealing, reinforcement learning, bayesian optimization, and the like.

In method 300, the outer loop includes logic optimization, process mapping, and netlist optimization, wherein the optimization objective of the logic optimization is the correlation index of the logic diagram, and the optimization objective of the process mapping and netlist optimization is the PPA of the netlist. In other words, the process map and netlist optimized inner loop is oriented towards the final optimization target, i.e., PPA of the netlist. The outer loop of logic optimization, process mapping and netlist optimization (blocks 303-308) adjusts the starting optimization points of the process mapping and netlist optimization by means of logic optimization modification logic diagrams, thereby introducing a certain randomness or robustness, skipping out the local minima at the time of search. Moreover, in method 300, area optimization and hierarchical optimization may be performed alternately to find further advantages.

Fig. 4 illustrates a flow chart of a logic synthesis method 400 according to some embodiments of the present disclosure. At block 402, operator and parameter settings, constraints, process library modules, and optimization objectives, iteration termination conditions, etc. are set in the configuration file.

At block 404, the circuit file is entered, automatically searching the generator sequence and the final circuit netlist file.

At block 406, the final circuit netlist file and report are analyzed. If it is determined at block 408 that various constraints are satisfied, method 400 ends and the netlist is passed to the next stage. If it is determined at block 408 that the partial constraint cannot be met, the method 400 proceeds to block 410, and if it is determined at block 410 that the conflict is acceptable or the upper run-time limit is reached, the next phase is entered. If it is determined at block that the conflict is unacceptable and the runtime upper limit is not reached, then returning to block 402, the configuration file is adjusted for targeting.

Fig. 5 shows a schematic block diagram of an apparatus 500 that may be used to implement embodiments of the present disclosure. The methods 100-400 as shown in fig. 1-4 may be implemented by the apparatus 500.

As shown in fig. 5, the apparatus 500 includes a central processing unit (Central Processing Unit, CPU) 501, which can perform various appropriate actions and processes according to computer program instructions stored in a Read-Only Memory (ROM) 502 or computer program instructions loaded from a storage unit 508 into a random access Memory (Random Access Memory, RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The CPU 501, ROM 502, and RAM 503 are connected to each other through a bus 504. An Input/Output (I/O) interface 505 is also connected to bus 504.

The various components in the device 500 are connected to an I/O interface 505, including an input unit 506, e.g., a keyboard, a mouse, etc., an output unit 507, e.g., various types of displays, speakers, etc., a storage unit 508, e.g., a magnetic disk, optical disk, etc., and a communication unit 509, e.g., a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The various processes and treatments described above, such as methods 100-400, may be performed by the processing unit 501. For example, in some embodiments, the methods 100-400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 500 via the ROM 502 and/or the communication unit 509. When the computer program is loaded into RAM 503 and executed by CPU 501, one or more of the steps of methods 100-400 described above may be performed. Alternatively, in other embodiments, CPU 501 may be configured to perform methods 100-400 in any other suitable manner (e.g., by means of firmware).

The present disclosure may be methods, apparatus, systems, and/or computer program products. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for performing aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-Only Memory (ROM), an erasable programmable read-Only Memory (EPROM) or flash Memory, a static random access Memory (Static Random Access Memory, SRAM), a portable compact disc read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), a digital versatile disc (Digital Video Disc, DVD), a Memory stick, a floppy disk, a mechanical encoding device, punch cards or in-groove protrusion structures such as those having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

The computer program instructions for performing the operations of the present disclosure may be assembler instructions, instruction set architecture (Instruction Set Architecture, ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Python, c++, or the like and conventional procedural programming languages, such as the "C" language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (Local Area Network, LAN) or a wide area network (Wide Area Network, WAN), or may be connected to an external computer (e.g., through the internet using an internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field programmable gate arrays (Field Programmable GATE ARRAY, FPGA), or programmable logic arrays (Programmable Logic Array, PLA), with state information of computer-readable program instructions, which may be executed.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (9)

A method for electronic design automation, comprising: Performing logic optimization on the Boolean logic representing the circuit to obtain optimized Boolean logic; Process mapping the Boolean logic to obtain a netlist representing the circuit; performing netlist optimization on the netlist to obtain an optimized netlist; and In response to determining that the optimized netlist is better than a local optimal netlist representing the circuit, the local optimal netlist is replaced with the optimized netlist and process mapped. The method according to claim 1, further comprising: In response to determining that the optimized netlist is worse than the local optimal netlist, determining whether the local optimal netlist is better than the global optimal netlist; and In response to determining that the local optimal netlist is better than the global optimal netlist, logic optimization is performed on the local optimal netlist. The method according to claim 2, further comprising: In response to determining that the local optimal netlist is inferior to the global optimal netlist, the global optimal netlist is determined as a synthesized netlist representing the circuit. The method according to claim 1, wherein the logic optimization comprises at least one of the following: performing area-first logic optimization on the Boolean logic; and A level-first logic optimization is performed on the Boolean logic. The method according to claim 1, wherein the process mapping comprises at least one of the following: performing area-first process mapping on the Boolean logic; and A hierarchical first process mapping is performed on the Boolean logic. The method according to claim 1, wherein the netlist optimization comprises at least one of the following: performing area-first netlist optimization on the netlist; and A level-first netlist optimization is performed on the netlist. A device comprising: Processor; and A memory is coupled to the processor and stores instructions, which, when executed by the processor, cause the device to implement the method according to any one of claims 1-6. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions, when executed by at least one processor, cause the at least one processor to perform the method according to any one of claims 1-6. A computer program, wherein when the computer program is executed by at least one processor, the at least one processor is caused to perform the method according to any one of claims 1 to 6.