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Van Eijk, 1997 - Google Patents

Formal methods for the verification of digital circuits

Van Eijk, 1997

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Document ID
10065260639121003184
Author
Van Eijk C
Publication year

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Snippet

With the increasing complexity and tight time-to-market schedules of today's digital systems, it is becoming more and more difficult to design correct circuits for these systems. Therefore, throughout the design process it is necessary to check that no errors are made. This task is …
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Classifications

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    • G06F17/504—Formal methods
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    • G06F17/5045—Circuit design
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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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