[go: up one dir, main page]

CN119133280A - Back contact solar cell, battery assembly and photovoltaic system - Google Patents

Back contact solar cell, battery assembly and photovoltaic system Download PDF

Info

Publication number
CN119133280A
CN119133280A CN202411059326.1A CN202411059326A CN119133280A CN 119133280 A CN119133280 A CN 119133280A CN 202411059326 A CN202411059326 A CN 202411059326A CN 119133280 A CN119133280 A CN 119133280A
Authority
CN
China
Prior art keywords
type
type doped
silicon substrate
electrode
doped layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202411059326.1A
Other languages
Chinese (zh)
Inventor
张生利
杨新强
龙裕
王永谦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Original Assignee
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuhai Fushan Aixu Solar Energy Technology Co Ltd filed Critical Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority to CN202411059326.1A priority Critical patent/CN119133280A/en
Publication of CN119133280A publication Critical patent/CN119133280A/en
Pending legal-status Critical Current

Links

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

本发明涉及太阳能电池技术领域,具体公开一种背接触太阳电池、电池组件及光伏系统,电池包括:硅衬底,所述硅衬底具有相对的受光面及背光面;所述背光面上沿远离受光面的方向依次设有掺杂层及电极层,所述掺杂层包括交替间隔排布的N型掺杂层及P型掺杂层,所述电极层包括N型电极及P型电极,所述硅衬底、所述P型掺杂层及所述N型掺杂层的电导率依次递增,当所述硅衬底为P型硅衬底,所有所述N型电极的总长度大于所有所述P型电极的总长度;当所述硅衬底为N型硅衬底,所有所述P型电极的总长度大于所有所述N型电极的总长度。本发明能够加强光生电子空穴对的分离及电流的收集,并能够有效减少串联电阻,降低电池内部的功率损耗,提高填充因子,同时,增加硅衬底有效发电面积,产生更多的光生载流子,提高短路电流,有效提高电池转换效率。

The present invention relates to the technical field of solar cells, and specifically discloses a back-contact solar cell, a cell assembly and a photovoltaic system. The cell comprises: a silicon substrate, the silicon substrate having a relative light-receiving surface and a back-light surface; a doping layer and an electrode layer are sequentially arranged on the back-light surface in a direction away from the light-receiving surface, the doping layer comprises an N-type doping layer and a P-type doping layer arranged alternately, the electrode layer comprises an N-type electrode and a P-type electrode, the conductivity of the silicon substrate, the P-type doping layer and the N-type doping layer increases in sequence, when the silicon substrate is a P-type silicon substrate, the total length of all the N-type electrodes is greater than the total length of all the P-type electrodes; when the silicon substrate is an N-type silicon substrate, the total length of all the P-type electrodes is greater than the total length of all the N-type electrodes. The present invention can enhance the separation of photogenerated electron-hole pairs and the collection of current, and can effectively reduce the series resistance, reduce the power loss inside the battery, and improve the filling factor. At the same time, it increases the effective power generation area of the silicon substrate, generates more photogenerated carriers, increases the short-circuit current, and effectively improves the battery conversion efficiency.

Description

Back contact solar cell, battery assembly and photovoltaic system
Technical Field
The invention relates to the technical field of solar cells, in particular to a back contact solar cell, a cell assembly and a photovoltaic system.
Background
At present, in a conventional solar cell, a front electrode and a back electrode are respectively arranged on a light receiving surface and a back surface of a substrate, and current transmission of carriers in the cell is mainly longitudinal transmission, but because the front electrode covers the light receiving surface of the substrate, partial incident light is reflected by the front electrode to cause optical loss, so that the energy conversion efficiency of the cell is affected.
Compared with a conventional solar cell, the back contact cell forms the P-type doped region and the N-type doped region which are alternately arranged in the backlight surface, the metal electrode correspondingly covers the backlight surface, and current transmission of carriers in the cell is mainly transverse transmission. The back contact battery has no metal electrode shielding on the light receiving surface, so that shading loss can be avoided, and conversion efficiency is improved to a certain extent. However, due to the long lateral transport distance, the lateral transport of majority carriers results in significant series resistance loss, resulting in limited conversion efficiency improvement.
Disclosure of Invention
The invention aims at providing a back contact solar cell, a cell assembly and a photovoltaic system aiming at the prior art.
The invention can realize larger potential gradient from the P-type doped layer to the N-type doped layer through the silicon substrate, and strengthen the separation of photo-generated electron hole pairs. The larger potential gradient is beneficial to electrons to quickly enter the N-type doped layer and holes to quickly enter the P-type doped layer, and collected charges can be more quickly transmitted to a metal collecting electrode corresponding to the metal grid line, so that series resistance can be effectively reduced, power loss in the battery is reduced, and filling factors are improved. Meanwhile, the effective power generation area of the silicon substrate is increased, more photo-generated carriers are generated, the short-circuit current is improved, and then the conversion efficiency of the battery is effectively improved.
In order to achieve the above purpose, the invention adopts the following technical scheme:
first, the present invention provides a back contact solar cell comprising:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
When the silicon substrate is a P-type silicon substrate, the total length of all the N-type electrodes is larger than that of all the P-type electrodes;
when the silicon substrate is an N-type silicon substrate, the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
In some embodiments:
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
In some embodiments:
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total contact area between all the N-type electrodes and the silicon substrate on the battery, S P is the total contact area between all the P-type electrodes and the silicon substrate on the battery, k is a coefficient, and k is 1.01-1.15.
In some embodiments, when the silicon substrate is a P-type silicon substrate, the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1<a.ltoreq.1.5;
When the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1<b to be less than or equal to 1.5.
In some embodiments, when the silicon substrate is a P-type silicon substrate, the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1.001.ltoreq.a.ltoreq.1.2;
When the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.001-1.2.
In some embodiments, the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the first N-type doped region and the first P-type doped region are arranged along a first direction in length, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are arranged in a crossing manner,
The width of the first N-type doped region is larger than that of the first P-type doped region.
In some embodiments, the N-type doped layer further includes a second N-type doped region, a plurality of first N-type doped regions are arranged on the same second N-type doped region along a second direction, the P-type doped layer further includes a second P-type doped region, a plurality of first P-type doped regions are arranged on the same second P-type doped region along the second direction, the second N-type doped region and the second P-type doped region are arranged along the second direction along the length direction of the second N-type doped region, and adjacent first N-type doped regions and first P-type doped regions are alternately arranged at intervals along the first direction,
The width of the second N-type doped region is larger than that of the second P-type doped region.
In some embodiments, the N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, the first N-type electrode is arranged outside the first N-type doped region, the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along the first direction, and the first P-type electrode is arranged outside the first P-type doped region.
In some embodiments, the N-type electrode comprises a first N-type electrode and a second N-type electrode, the length direction of the first N-type electrode is along a first direction, the length direction of the second N-type electrode is along a second direction, the first N-type electrode is arranged outside the first N-type doped region, the second N-type electrode is arranged outside the second N-type doped region, the P-type electrode comprises a first P-type electrode and a second P-type electrode, the length direction of the first P-type electrode is along a first direction, the length direction of the second P-type electrode is along a second direction, the first P-type electrode is arranged outside the first P-type doped region, and the second P-type electrode is arranged outside the second P-type doped region.
In some embodiments, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 1<c.ltoreq.9.
In some embodiments, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 1.4< c.ltoreq.4.5.
In some embodiments, the first P-type doped region has a width of 100 μm to 900 μm.
In some embodiments, the first P-type doped region has a width of 200 μm to 500 μm.
In some embodiments, an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is disposed between the adjacent first N-type doped region and the first P-type doped region, and the sum of widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 0.3 mm-3 mm.
In some embodiments, the sum of the widths of the single first N-type doped region, the two isolation regions, and the single first P-type doped region is 0.5mm to 1.6mm.
In some embodiments, the doping concentration of the silicon substrate is less than 5 x 10 14cm-3 and the conductivity of the silicon substrate is less than 2S/cm.
In some embodiments, the ratio between the conductivities of the P-doped layer and the N-doped layer is 1:2-6.5.
In some embodiments, the conductivity of the N-doped layer is 600ohm -1.cm-1~2800ohm-1.cm-1 and the conductivity of the P-doped layer is 150ohm -1.cm-1~580ohm-1.cm-1.
In some embodiments, the conductivity of the N-doped layer is 1000ohm -1.cm-1~1800ohm-1.cm-1 and the conductivity of the P-doped layer is 240ohm -1.cm-1~450ohm-1.cm-1.
In some embodiments, the sheet resistance of the P-doped layer is greater than the sheet resistance of the N-doped layer.
In some embodiments, the sheet resistance of the P-type doped layer is 1.5 times to 10 times that of the N-type doped layer.
In some embodiments, the sheet resistance of the N-type doped layer is 26-150 ohm/sq and the sheet resistance of the P-type doped layer is 80-400 ohm/sq.
In some embodiments, the sheet resistance of the N-type doped layer is 35-120 ohm/sq and the sheet resistance of the P-type doped layer is 90-350 ohm/sq.
In some embodiments, a passivation layer is further disposed on the backlight surface, the passivation layer is disposed on a side of the N-type doped layer and a side of the P-type doped layer, which is opposite to the silicon substrate, the passivation layer is provided with a first window and a second window, the N-type electrode at least partially extends into the first window and contacts with the N-type doped layer, and the P-type electrode at least partially extends into the second window and contacts with the P-type doped layer.
Next, the present invention provides a battery assembly including the above-mentioned back contact solar cell.
Furthermore, the invention provides a photovoltaic system comprising the battery assembly.
The invention has the beneficial effects that:
In the invention, the conductivity of the N-type silicon substrate, the conductivity of the P-type doped layer and the conductivity of the N-type doped layer are controlled to be sequentially increased, so that a larger potential gradient from the P-type doped layer to the N-type doped layer through the silicon substrate is realized, and the separation of photo-generated electron hole pairs is enhanced. The method comprises the steps of forming a high-low junction between one of the N-type doped layer and the P-type doped layer, which has the same polarity as the silicon substrate, and the silicon substrate, forming a P-N junction between one of the N-type doped layer and the P-type doped layer, which has the different polarities as the silicon substrate, and the silicon substrate, wherein a larger potential gradient is beneficial to enabling electrons to quickly enter the N-type doped layer and holes to quickly enter the P-type doped layer, and collected charges can be more quickly transmitted to a metal collecting electrode corresponding to a metal grid line, and can effectively reduce series resistance, reduce power loss in the battery, and improve the filling factor, and meanwhile, the total length of an electrode corresponding to one of the N-type doped layer and the P-type doped layer, which has the different polarities as the silicon substrate, is higher than the total length of an electrode corresponding to one of the N-type doped layer and the P-type doped layer, so that the effective power generation area of the silicon substrate is increased, more photo-generated carriers are generated, the short-circuit current is improved, and the conversion efficiency of the battery is further effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a back contact solar cell according to the present invention.
Fig. 2 is a schematic structural diagram of a doped layer of a back contact solar cell according to the present invention.
Fig. 3 is a schematic structural view of an electrode layer according to the present invention.
Fig. 4 is a schematic diagram of another structure of a doped layer of a back contact solar cell according to the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
First, referring to fig. 1, the present invention provides a back contact solar cell, comprising:
A silicon substrate 1 having a light receiving surface and a backlight surface opposite to each other;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layers comprise N-type doped layers 2 and P-type doped layers 3 which are alternately arranged at intervals,
The electrode layer 5 comprises an N-type electrode 51 and a P-type electrode 52, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
When the silicon substrate is a P-type silicon substrate, the total length of all the N-type electrodes is larger than that of all the P-type electrodes;
when the silicon substrate is an N-type silicon substrate, the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
In the invention, the conductivity of the N-type silicon substrate, the conductivity of the P-type doped layer and the conductivity of the N-type doped layer are controlled to be sequentially increased, so that a larger potential gradient from the P-type doped layer to the N-type doped layer through the silicon substrate is realized, and the separation of photo-generated electron hole pairs is enhanced. The method comprises the steps of forming a high-low junction between one of the N-type doped layer and the P-type doped layer, which has the same polarity as the silicon substrate, and the silicon substrate, forming a P-N junction between one of the N-type doped layer and the P-type doped layer, which has the different polarities as the silicon substrate, and the silicon substrate, wherein a larger potential gradient is beneficial to enabling electrons to quickly enter the N-type doped layer and holes to quickly enter the P-type doped layer, and collected charges can be more quickly transmitted to a metal collecting electrode corresponding to a metal grid line, and can effectively reduce series resistance, reduce power loss in the battery, and improve the filling factor, and meanwhile, the total length of an electrode corresponding to one of the N-type doped layer and the P-type doped layer, which has the different polarities as the silicon substrate, is higher than the total length of an electrode corresponding to one of the N-type doped layer and the P-type doped layer, so that the effective power generation area of the silicon substrate is increased, more photo-generated carriers are generated, the short-circuit current is improved, and the conversion efficiency of the battery is further effectively improved.
The conductivity difference of the N-type silicon substrate, the N-type doped layer and the P-type doped layer can be realized by controlling the doping concentration difference of the N-type dopant in the N-type doped layer and the P-type dopant in the P-type doped layer, the doping concentration is positively related to the conductivity, the P-type dopant in the P-type doped layer is boron, the N-type dopant in the N-type doped layer is phosphorus, and the high-doping phosphorus can keep a good passivation effect, so that the conversion efficiency of the battery is improved.
In some embodiments:
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
When the silicon substrate is an N-type silicon substrate, the total length of all the P-type electrodes is larger than that of all the N-type electrodes, and at this time, the total contact area between all the P-type electrodes and the silicon substrate on the battery is larger than that between all the N-type electrodes and the silicon substrate on the battery. When the silicon substrate is a P-type silicon substrate, the total length of all the N-type electrodes is larger than that of all the P-type electrodes, and at this time, the total contact area between all the N-type electrodes and the silicon substrate on the battery is larger than that between all the P-type electrodes and the silicon substrate on the battery. Furthermore, the total area of one of the N-type electrode and the P-type electrode, which has different polarity from the silicon substrate, is larger than the total area of one of the N-type electrode and the P-type electrode, which has the same polarity as the silicon substrate, so that the conversion efficiency of the battery is effectively improved.
In some embodiments:
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total contact area between all the N-type electrodes and the silicon substrate on the battery, S P is the total contact area between all the P-type electrodes and the silicon substrate on the battery, k is a coefficient, and k is 1.01-1.15.
Illustratively, k is 1.01, 1.02, 1.03, 1.04, or 1.05, but is not limited thereto.
When k is too small or too large, it is difficult to balance the collection of electron-hole pairs, affecting the conversion efficiency of the battery.
When the silicon substrate is a P-type silicon substrate, the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1<a to be less than or equal to 1.5;
When the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1<b to be less than or equal to 1.5.
Illustratively, when the silicon substrate is a P-type silicon substrate, the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1.01, 1.05, 1.08, 1.1, 1.12, 1.15, 1.18, 1.2, 1.22, 1.25, 1.28, 1.3, 1.32, 1.35, 1.38, 1.4, 1.43, 1.45, 1.48, or 1.5, but is not limited thereto.
Illustratively, when the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.01, 1.05, 1.08, 1.1, 1.12, 1.15, 1.18, 1.2, 1.22, 1.25, 1.28, 1.3, 1.32, 1.35, 1.38, 1.4, 1.43, 1.45, 1.48, or 1.5, but is not limited thereto.
When a or b is too small, the effective power generation area is insufficient, and when a or b is too large, it is difficult to balance the collection of electron-hole pairs, affecting the conversion efficiency of the battery.
When the silicon substrate is a P-type silicon substrate, the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1.001-1.2;
When the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.001-1.2.
Within this range, the collection of electron-hole pairs can be better balanced while ensuring a sufficient effective power generation area.
For example, when the silicon substrate is a P-type silicon substrate, the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1.001、1.002、1.005、1.008、1.01、1.02、1.03、1.04、1.05、1.06、1.07、1.08、1.09、1.1、1.11、1.12、1.13、1.14、1.15、1.16、1.17、1.18、1.19 or 1.2, but is not limited thereto.
Illustratively, when the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.001、1.002、1.005、1.008、1.01、1.02、1.03、1.04、1.05、1.06、1.07、1.08、1.09、1.1、1.11、1.12、1.13、1.14、1.15、1.16、1.17、1.18、1.19 or 1.2, but is not limited thereto.
Wherein the N-type doped layer comprises a first N-type doped region 21, the P-type doped layer comprises a first P-type doped region 31, the length directions of the first N-type doped region and the first P-type doped region are all along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
Wherein the N-type doped layer further comprises a second N-type doped region 22, a plurality of first N-type doped regions are arranged on the same second N-type doped region along a second direction, the P-type doped layer further comprises a second P-type doped region 32, a plurality of first P-type doped regions are arranged on the same second P-type doped region along the second direction, the length directions of the second N-type doped region and the second P-type doped region are arranged along the second direction, and adjacent first N-type doped regions and first P-type doped regions are arranged between each other, the second N-type doped regions and the second P-type doped regions are alternately arranged at intervals along the first direction,
The width of the second N-type doped region is larger than that of the second P-type doped region.
In the first embodiment, referring to fig. 2 to 3, the N-type doped layer and the P-type doped layer have rectangular structures, and at this time, the N-type doped layer is a first N-type doped region, and the P-type doped layer is a first P-type doped region.
In a second embodiment, referring to fig. 4, the N-doped layer and the P-doped layer are in a comb-tooth structure, at this time, the single N-doped layer is composed of a first N-doped region and a plurality of second N-doped regions, the same second N-doped region is provided with a plurality of first N-doped regions arranged along a second direction, the single P-doped layer is composed of a first P-doped region and a plurality of second P-doped regions, and the same second P-doped region is provided with a plurality of first P-doped regions arranged along the second direction.
Because the N-type doped layer is arranged at high conductivity compared with the P-type doped layer, the N-type doped layer has stronger transverse transmission capability than the P-type doped layer and can be transmitted for a larger distance, therefore, through the low-concentration doped silicon substrate, the width of the N-type doped layer is larger than that of the P-type doped layer, matching of carrier transmission distances is achieved according to the corresponding transverse transmission capacity of the N-type doped layer and the P-type doped layer, current collection is balanced, smaller series resistance and higher filling factor are obtained, and conversion efficiency is further improved. Meanwhile, the passivation characteristic of the highly doped N-type doped layer is superior to that of the P-type doped layer, so that the width of the N-type doped layer is increased by reducing the width of the P-type doped layer, the duty ratio of the passivation contact area of the N-type polysilicon material layer is higher, the overall comprehensive passivation level of the battery is higher, the composite loss is lower, and the conversion efficiency is further improved.
When the N-type doped layer and the P-type doped layer are of rectangular structures, the N-type electrode comprises a first N-type electrode, and the P-type electrode comprises a first P-type electrode.
Specifically, the N-type electrode includes a first N-type electrode 51, where the length direction of the first N-type electrode is set along a first direction, and the first N-type electrode is set outside the first N-type doped region;
The P-type electrode includes a first P-type electrode 52, where the length direction of the first P-type electrode is set along a first direction, and the first P-type electrode is set outside the first P-type doped region.
When the N-type doped layer and the P-type doped layer are of comb-tooth structures, the N-type electrode comprises a first N-type electrode and a second N-type electrode, and the P-type electrode comprises a first P-type electrode and a second P-type electrode.
Specifically, the N-type electrode comprises a first N-type electrode and a second N-type electrode, the length direction of the first N-type electrode is set along a first direction, the length direction of the second N-type electrode is set along a second direction, the first N-type electrode is arranged outside the first N-type doped region, and the second N-type electrode is arranged outside the second N-type doped region;
The P-type electrode comprises a first P-type electrode and a second P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, the length direction of the second P-type electrode is arranged along a second direction, the first P-type electrode is arranged outside the first P-type doped region, and the second P-type electrode is arranged outside the second P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 1<c to 9.
Illustratively, c is 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, or 9, but is not so limited.
When the ratio between the width of the first N-type doped region and the width of the first P-type doped region is too low, the improvement effect of the series resistance and the filling factor is poor, and when the ratio between the width of the first N-type doped region and the width of the first P-type doped region is too high, the width of the first P-type doped region is too narrow, the short-circuit current is too low, and the conversion efficiency is affected.
The ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 1.4< c.ltoreq.4.5.
Illustratively, c is 1.4, 1.5, 1.8, 2, 2.2, 2.5, 2.7, 3, 3.3, 3.5, 3.8, 4, 4.2, or 4.5, but is not limited thereto.
Within this range, a smaller series resistance and a higher fill factor can be obtained.
The width of the first P-type doped region is 100-900 μm.
When the width of the first P-type doped region is too large, the first N-type doped region needs to be provided with a larger width, so that the total width of the N-type doped layer and the P-type doped layer is increased, the transverse transport distance of carriers is increased, the composite loss in the transport process is increased, the number of the N-type doped layer and the P-type doped layer which can be arranged in the same battery is reduced, the number of metal grid lines (electrode layers) which are correspondingly arranged on the outer side is correspondingly reduced, the current collection capacity is reduced, and the conversion efficiency is influenced.
Illustratively, the first P-type doped region has a width of 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, or 900 μm, but is not limited thereto.
Preferably, the width of the first P-type doped region is 200 μm to 500 μm, and in this range, a smaller series resistance and a higher fill factor can be obtained.
And an isolation region 6 for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, wherein the sum of the widths of the single first N-type doped region, the two isolation regions and the single first P-type doped region is 0.3 mm-3 mm, and the width of the isolation region is W G.
Exemplary cell widths are 0.3mm, 0.5mm, 1.0mm, 1.5mm, 2.0mm, 2.5mm, or 3.0mm, but are not limited thereto.
On the basis of controlling the width and the total area proportion of the first N-type doped region and the first P-type doped region, the width of the unit is further controlled, the maximization of charge collection can be realized, the transverse transport distance of carriers is further shortened within the width range of the unit, the series resistance is reduced, the filling factor is improved, and the conversion efficiency of the battery is effectively improved.
When the cell width is too small, the preparation difficulty is increased, the superposition of an N-type doped layer and a P-type doped layer is easy to cause, meanwhile, due to technical limitation, the narrowest width exists in the isolation region, when the cell width is too small, the proportion of the isolation region occupying the whole cell width is easy to cause too large, the surface recombination loss of the isolation region is increased, and the conversion efficiency of the battery is reduced.
When the cell width is too large, the electric field intensity between the N-type doped layer and the P-type doped layer is weakened, the transverse transportation distance is prolonged, effective carrier collection is difficult to form, and the conversion efficiency of the cell is reduced.
The sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 0.5 mm-1.6 mm, and in the range, the battery conversion efficiency is high, the preparation difficulty is relatively low, the higher production yield is ensured, and the comprehensive performance is better.
Exemplary cell widths are, but not limited to, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, or 1.6 mm.
The doping concentration of the silicon substrate is less than 5 multiplied by 10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
In the invention, the silicon substrate adopts low-concentration doping to form the low-conductivity silicon substrate, so that larger conductivity difference is formed between the silicon substrate and the N-type doped layer and between the silicon substrate and the P-type doped layer, the N-type doped layer and the P-type doped layer are arranged in a high conductivity mode compared with the silicon substrate, and the high conductivity difference enables the N-type doped layer and the P-type doped layer to respectively form larger potential gradient with the low-doped and low-conductivity silicon substrate, thereby enhancing the electric field intensity, more effectively separating electron holes and enhancing the transverse transmission capability of carriers.
The ratio of the conductivities of the P-type doped layer and the N-type doped layer is 1:2-6.5, so that a large enough conductivity difference is formed between the N-type doped layer and the P-type doped layer, and a large potential gradient is formed between the P-type doped layer and the low-doped and low-conductivity silicon substrate respectively.
Exemplary, but not limited to, the ratio between the conductivities of the P-doped layer and the N-doped layer is 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5, 1:5, 1:5.5, 1:6, or 1:6.5.
Wherein the conductivity of the N-type doped layer is 600ohm -1.cm-1~2800ohm-1.cm-1 and the conductivity of the P-type doped layer is 150ohm -1.cm-1~580ohm-1.cm-1.
When the conductivity of the N-type doped layer or the conductivity of the P-type doped layer is too low, the current transmission efficiency is reduced, the surface recombination efficiency and the recombination loss in the transmission process are easily increased, the conversion efficiency is reduced, and when the conductivity of the N-type doped layer or the conductivity of the P-type doped layer is too high, the preparation difficulty is increased, the lattice quality is easily reduced, and the conversion efficiency is influenced.
Illustratively, the conductivity of the N-doped layer is 600ohm-1.cm-1、650ohm-1.cm-1、700ohm-1.cm-1、750ohm-1.cm-1、800ohm-1.cm-1、850ohm-1.cm-1、900ohm-1.cm-1、950ohm-1.cm-1、1000ohm- 1.cm-1、1050ohm-1.cm-1、1100ohm-1.cm-1、1150ohm-1.cm-1、1200ohm-1.cm-1、1250ohm-1.cm-1、1300ohm-1.cm-1、1350ohm-1.cm-1、1400ohm-1.cm-1、1450ohm-1.cm-1、1500ohm-1.cm-1、1550ohm-1.cm-1、1600ohm-1.cm-1、1650ohm-1.cm-1、1700ohm-1.cm-1、1750ohm-1.cm-1、1800ohm-1.cm-1、1850ohm-1.cm-1、1900ohm-1.cm-1、1950ohm-1.cm-1、2000ohm-1.cm-1、2100ohm-1.cm-1、2150ohm-1.cm-1、2200ohm-1.cm-1、2250ohm-1.cm-1、2300ohm-1.cm-1、2350ohm-1.cm-1、2400ohm-1.cm-1、2450ohm-1.cm-1、2500ohm-1.cm-1、2550ohm-1.cm-1、2600ohm-1.cm-1、2650ohm-1.cm-1、2700ohm-1.cm-1、2750ohm-1.cm-1 or 2800ohm -1.cm-1, but is not limited thereto.
Illustratively, the conductivity of the P-doped layer is 150ohm-1.cm-1、180ohm-1.cm-1、200ohm-1.cm-1、220ohm-1.cm-1、250ohm-1.cm-1、280ohm-1.cm-1、300ohm-1.cm-1、320ohm-1.cm-1、350ohm-1.cm-1、380ohm-1.cm-1、400ohm-1.cm-1、420ohm-1.cm-1、450ohm-1.cm-1、480ohm-1.cm-1、500ohm-1.cm-1、520ohm-1.cm-1、550ohm-1.cm-1 or 580ohm -1.cm-1, but is not limited thereto.
Wherein the conductivity of the N-type doped layer is 1000ohm -1.cm-1~1800ohm-1.cm-1, and the conductivity of the P-type doped layer is 240ohm -1.cm-1~450ohm-1.cm-1.
Illustratively, the conductivity of the N-doped layer is 1000hm-1.cm-1、1050ohm-1.cm-1、1100ohm- 1.cm-1、1120ohm-1.cm-1、1150ohm-1.cm-1、1180ohm-1.cm-1、1200ohm-1.cm-1、1230ohm-1.cm-1、1250ohm-1.cm-1、1280ohm-1.cm-1、1300ohm-1.cm-1、1320ohm-1.cm-1、1350ohm-1.cm-1、1380ohm-1.cm-1、1400ohm-1.cm-1、1420ohm-1.cm-1、1450ohm-1.cm-1、1480ohm-1.cm-1、1500ohm-1.cm-1、1520ohm-1.cm-1、1550ohm-1.cm-1、1580ohm-1.cm-1、1600ohm-1.cm-1、1620ohm-1.cm-1、1650ohm-1.cm-1、1680ohm-1.cm-1、1700ohm-1.cm-1、1720ohm-1.cm-1、1750ohm-1.cm-1、1780ohm-1.cm-1 or 1800ohm -1.cm-1, but is not limited thereto.
Illustratively, the conductivity of the P-doped layer is 240ohm-1.cm-1、250ohm-1.cm-1、280ohm-1.cm-1、300ohm-1.cm-1、320ohm-1.cm-1、350ohm-1.cm-1、380ohm-1.cm-1、400ohm-1.cm-1、420ohm-1.cm-1 or 450ohm -1.cm-1, but is not limited thereto.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The square resistance of the N-type doped layer is low, the transverse transportation capability is higher than that of the P-type doped layer, the width of the first N-type doped region can be set to be larger than that of the first P-type doped region, and the series resistance and the filling factor are improved while current collection is balanced, so that the conversion efficiency is improved.
The sheet resistance of the P-type doped layer is 1.5 times to 10 times of that of the N-type doped layer.
Illustratively, the sheet resistance of the P-type doped layer is 1.5 times, 2.0 times, 2.5 times, 3.0 times, 3.5 times, 4.0 times, 4.5 times, 5.0 times, 5.5 times, 6.0 times, 6.5 times, 7.0 times, 7.5 times, 8.0 times, 8.5 times, 9.0 times, 9.5 times, or 10 times that of the N-type doped layer, but is not limited thereto.
The square resistance of the N-type doped layer is 26-150 ohms/sq, and the square resistance of the P-type doped layer is 80-400 ohms/sq.
Illustratively, the sheet resistance of the N-type doped layer is 26ohm/sq、30ohm/sq、35ohm/sq、40ohm/sq、45ohm/sq、50ohm/sq、55ohm/sq、60ohm/sq、65ohm/sq、70ohm/sq、75ohm/sq、80ohm/sq、85ohm/sq、90ohm/sq、95ohm/sq、100ohm/sq、105ohm/sq、110ohm/sq、115ohm/sq、120ohm/sq、125ohm/sq、130ohm/sq、135ohm/sq、140ohm/sq、145ohm/sq or 150ohm/sq, but is not limited thereto.
Illustratively, the sheet resistance of the P-type doped layer is 80ohm/sq、90ohm/sq、100ohm/sq、110ohm/sq、120ohm/sq、130ohm/sq、140ohm/sq、150ohm/sq、160ohm/sq、170ohm/sq、180ohm/sq、190ohm/sq、200ohm/sq、210ohm/sq、220ohm/sq、230ohm/sq、240ohm/sq、250ohm/sq、260ohm/sq、270ohm/sq、280ohm/sq、290ohm/sq、300ohm/sq、310ohm/sq、320ohm/sq、330ohm/sq、340ohm/sq、350ohm/sq、360ohm/sq、370ohm/sq、380ohm/sq、390ohm/sq or 400ohm/sq, but is not limited thereto.
The square resistance of the N-type doped layer is 35-120 ohms/sq, and the square resistance of the P-type doped layer is 90-350 ohms/sq.
Illustratively, the sheet resistance of the N-type doped layer is 35ohm/sq、40ohm/sq、45ohm/sq、50ohm/sq、55ohm/sq、60ohm/sq、65ohm/sq、70ohm/sq、75ohm/sq、80ohm/sq、85ohm/sq、90ohm/sq、95ohm/sq、100ohm/sq、105ohm/sq、110ohm/sq、115ohm/sq or 120ohm/sq, but is not limited thereto.
Illustratively, the sheet resistance of the P-type doped layer is 90ohm/sq、100ohm/sq、110ohm/sq、120ohm/sq、130ohm/sq、140ohm/sq、150ohm/sq、160ohm/sq、170ohm/sq、180ohm/sq、190ohm/sq、200ohm/sq、210ohm/sq、220ohm/sq、230ohm/sq、240ohm/sq、250ohm/sq、260ohm/sq、270ohm/sq、280ohm/sq、290ohm/sq、300ohm/sq、310ohm/sq、320ohm/sq、330ohm/sq、340ohm/sq or 350ohm/sq, but is not limited thereto.
The passivation layer is arranged on one side of the N-type doped layer and one side of the P-type doped layer, which is opposite to the silicon substrate, and is provided with a first window and a second window, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
The passivation layer may be at least one of a silicon nitride material layer, a silicon oxide material layer, a silicon oxynitride material layer, and an intrinsic amorphous silicon material layer.
The passivation layer effectively reduces the recombination of minority carriers on the back surface of the battery and surface states, and is beneficial to improving the photoelectric conversion efficiency of the battery.
Next, the present invention provides a battery assembly including the above-mentioned back contact solar cell.
Furthermore, the invention provides a photovoltaic system comprising the battery assembly.
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
Example 1
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.05.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.002.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 4.5.
The width of the first P-type doped region is 500 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 2.85mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:3.53.
Wherein the conductivity of the N-type doped layer is 600ohm -1.cm-1, and the conductivity of the P-type doped layer is 170ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 2.71 times of that of the N-type doped layer.
The square resistance of the N-type doped layer is 140ohm/sq, and the square resistance of the P-type doped layer is 380ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 2
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.1.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.05.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 3.
The width of the first P-type doped region is 300 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 1.3mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:4.17.
Wherein the conductivity of the N-type doped layer is 1000ohm -1.cm-1, and the conductivity of the P-type doped layer is 240ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 4.2 times of that of the N-type doped layer.
The sheet resistance of the N-type doped layer is 50ohm/sq, and the sheet resistance of the P-type doped layer is 210ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 3
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.1.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.05.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 3.
The width of the first P-type doped region is 300 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 1.3mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:4.83.
Wherein the conductivity of the N-type doped layer is 2800ohm -1.cm-1, and the conductivity of the P-type doped layer is 580ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 2.81 times of that of the N-type doped layer.
The square resistance of the N-type doped layer is 32ohm/sq, and the square resistance of the P-type doped layer is 90ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 4
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.1.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.05.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 3.
The width of the first P-type doped region is 300 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 1.3mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:6.
Wherein the conductivity of the N-type doped layer is 1800ohm -1.cm-1, and the conductivity of the P-type doped layer is 300ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 7.5 times of that of the N-type doped layer.
The square resistance of the N-type doped layer is 28ohm/sq, and the square resistance of the P-type doped layer is 21ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 5
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.1.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.05.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
The ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 1.5.
The width of the first P-type doped region is 900 μm.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 2.35mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:4.
Wherein the conductivity of the N-type doped layer is 1800ohm -1.cm-1, and the conductivity of the P-type doped layer is 450ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 5 times of that of the N-type doped layer.
The square resistance of the N-type doped layer is 28ohm/sq, and the square resistance of the P-type doped layer is 140ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 6
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.13.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.08.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 9.
The width of the first P-type doped region is 100 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 1.1mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:4.
Wherein the conductivity of the N-type doped layer is 1800ohm -1.cm-1, and the conductivity of the P-type doped layer is 450ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 5 times of that of the N-type doped layer.
The sheet resistance of the N-type doped layer is 28ohm/sq, and the sheet resistance of the P-type doped layer is 1400ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 7
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.15.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.1.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 3.
The width of the first P-type doped region is 300 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 1.3mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:6.
Wherein the conductivity of the N-type doped layer is 1800ohm -1.cm-1, and the conductivity of the P-type doped layer is 300ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 7.5 times of that of the N-type doped layer.
The sheet resistance of the N-type doped layer is 28ohm/sq, and the sheet resistance of the P-type doped layer is 210ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Example 8
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is a P-type silicon substrate, and the total length of all N-type electrodes is larger than that of all P-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.15.
The silicon substrate is a P-type silicon substrate, and the ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1.2.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 1<c to 9.
The width of the first P-type doped region is 300 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 1.3mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:6.
Wherein the conductivity of the N-type doped layer is 1800ohm -1.cm-1, and the conductivity of the P-type doped layer is 300ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 7.5 times of that of the N-type doped layer.
The sheet resistance of the N-type doped layer is 28ohm/sq, and the sheet resistance of the P-type doped layer is 210ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, the present embodiment discloses a battery assembly including the above-described back contact solar cell.
Furthermore, the embodiment discloses a photovoltaic system, which comprises the battery assembly.
Comparative example 1
First, this comparative example discloses a back contact solar cell comprising:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivities of the silicon substrate, the N-type doped layer and the P-type doped layer are sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is larger than that of all the N-type electrodes.
Wherein,
Wherein L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, and S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell.
Wherein,
Where L N is the total length of all the N-type electrodes, L P is the total length of all the P-type electrodes, S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 1.05.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.002.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 4.5.
The width of the first P-type doped region is 500 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 2.85mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1.93:1.
Wherein the conductivity of the N-type doped layer is 300ohm -1.cm-1, and the conductivity of the P-type doped layer is 580ohm -1.cm-1.
Wherein, the sheet resistance of the P-type doped layer is 0.53 times of the sheet resistance of the N-type doped layer.
The square resistance of the N-type doped layer is 170ohm/sq, and the square resistance of the P-type doped layer is 90ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, this comparative example discloses a battery assembly including one of the back contact solar cells described above.
Further, this comparative example discloses a photovoltaic system including the above-described battery assembly.
Comparative example 2
First, the present embodiment discloses a back contact solar cell, including:
A silicon substrate having opposite light-receiving and backlight surfaces;
the backlight surface is sequentially provided with a doping layer and an electrode layer along the direction away from the light receiving surface,
The doped layer comprises N-type doped layers and P-type doped layers which are alternately arranged at intervals,
The electrode layer comprises an N-type electrode and a P-type electrode, the N-type electrode is electrically connected with the N-type doped layer, the P-type electrode is electrically connected with the P-type doped layer, wherein the widths of the N-type electrode and the P-type electrode are consistent,
The conductivity of the silicon substrate, the P-type doped layer and the N-type doped layer is sequentially increased,
The silicon substrate is an N-type silicon substrate, and the total length of all the P-type electrodes is smaller than that of all the N-type electrodes.
Wherein S is P·k·SN
Wherein S N is the total area of contact between all the N-type electrodes and the silicon substrate on the cell, S P is the total area of contact between all the P-type electrodes and the silicon substrate on the cell, k is a coefficient, and k is 0.85.
The silicon substrate is an N-type silicon substrate, and the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1:1.002.
Wherein the N-type doped layer comprises a first N-type doped region, the P-type doped layer comprises a first P-type doped region, the length directions of the first N-type doped region and the first P-type doped region are all arranged along a first direction, the first N-type doped region and the first P-type doped region are alternately arranged at intervals along a second direction, the first direction and the second direction are alternately arranged,
The width W N of the first N-type doped region is greater than the width W P of the first P-type doped region.
The N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along a first direction, and the first N-type electrode is arranged outside the first N-type doped region;
the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along a first direction, and the first P-type electrode is arranged outside the first P-type doped region.
Wherein, the ratio c of the width of the first N-type doped region to the width of the first P-type doped region is 4.5.
The width of the first P-type doped region is 500 mu m.
Wherein an isolation region for separating the adjacent first N-type doped region and the first P-type doped region is arranged between the adjacent first N-type doped region and the first P-type doped region, the sum of the widths among the single first N-type doped region, the two isolation regions and the single first P-type doped region is 2.85mm,
The doping concentration of the silicon substrate is 4.5X10 14cm-3, and the conductivity of the silicon substrate is less than 2S/cm.
The ratio of the conductivities of the P-type doping layer and the N-type doping layer is 1:3.53.
Wherein the conductivity of the N-type doped layer is 600ohm -1.cm-1, and the conductivity of the P-type doped layer is 170ohm -1.cm-1.
And the sheet resistance of the P-type doped layer is larger than that of the N-type doped layer.
The sheet resistance of the P-type doped layer is 2.71 times of that of the N-type doped layer.
The square resistance of the N-type doped layer is 140ohm/sq, and the square resistance of the P-type doped layer is 380ohm/sq.
The semiconductor device comprises a silicon substrate, a back surface, an N-type doped layer, a P-type doped layer, a passivation layer, a first window and a second window, wherein the passivation layer is arranged on the back surface, the passivation layer is arranged on one side, opposite to the silicon substrate, of the N-type doped layer and the P-type doped layer, the N-type electrode at least partially stretches into the first window to be in contact with the N-type doped layer, and the P-type electrode at least partially stretches into the second window to be in contact with the P-type doped layer.
Next, this comparative example discloses a battery assembly including one of the back contact solar cells described above.
Further, this comparative example discloses a photovoltaic system including the above-described battery assembly.
The solar cells prepared in examples 1 to 8 and comparative examples 1 to 2 were subjected to performance test, and the test results were as follows:
The foregoing description is only illustrative of the preferred embodiment of the present invention, and is not to be construed as limiting the invention, but is to be construed as limiting the invention to any and all simple modifications, equivalent variations and adaptations of the embodiments described above, which are within the scope of the invention, may be made by those skilled in the art without departing from the scope of the invention.

Claims (25)

1.一种背接触太阳电池,其特征在于,包括:1. A back contact solar cell, comprising: 硅衬底,所述硅衬底具有相对的受光面及背光面;A silicon substrate, wherein the silicon substrate has a light-receiving surface and a backlight surface opposite to each other; 所述背光面上沿远离受光面的方向依次设有掺杂层及电极层,The backlight surface is provided with a doping layer and an electrode layer in sequence in a direction away from the light receiving surface. 所述掺杂层包括交替间隔排布的N型掺杂层及P型掺杂层,The doping layer includes N-type doping layers and P-type doping layers that are alternately arranged. 所述电极层包括N型电极及P型电极,所述N型电极与所述N型掺杂层电性连接,所述P型电极与所述P型掺杂层电性连接,The electrode layer includes an N-type electrode and a P-type electrode, the N-type electrode is electrically connected to the N-type doped layer, and the P-type electrode is electrically connected to the P-type doped layer. 所述硅衬底、所述P型掺杂层及所述N型掺杂层的电导率依次递增,The electrical conductivities of the silicon substrate, the P-type doped layer, and the N-type doped layer increase in sequence. 当所述硅衬底为P型硅衬底,所有所述N型电极的总长度大于所有所述P型电极的总长度;When the silicon substrate is a P-type silicon substrate, the total length of all the N-type electrodes is greater than the total length of all the P-type electrodes; 当所述硅衬底为N型硅衬底,所有所述P型电极的总长度大于所有所述N型电极的总长度。When the silicon substrate is an N-type silicon substrate, the total length of all the P-type electrodes is greater than the total length of all the N-type electrodes. 2.根据权利要求1所述的一种背接触太阳电池,其特征在于,2. A back contact solar cell according to claim 1, characterized in that: 式中,LN为所有所述N型电极的总长度,LP为所有所述P型电极的总长度,SN为电池上所有所述N型电极与所述硅衬底之间接触的总面积,SP为电池上所有所述P型电极与所述硅衬底之间接触的总面积。In the formula, L N is the total length of all the N-type electrodes, LP is the total length of all the P-type electrodes, SN is the total contact area between all the N-type electrodes on the battery and the silicon substrate, and SP is the total contact area between all the P-type electrodes on the battery and the silicon substrate. 3.根据权利要求1所述的一种背接触太阳电池,其特征在于,3. A back contact solar cell according to claim 1, characterized in that: 式中,LN为所有所述N型电极的总长度,LP为所有所述P型电极的总长度,SN为电池上所有所述N型电极与所述硅衬底之间接触的总面积,SP为电池上所有所述P型电极与所述硅衬底之间接触的总面积,k为系数,且k为1.01~1.15。In the formula, L N is the total length of all the N-type electrodes, LP is the total length of all the P-type electrodes, SN is the total contact area between all the N-type electrodes on the battery and the silicon substrate, SP is the total contact area between all the P-type electrodes on the battery and the silicon substrate, k is a coefficient, and k is 1.01 to 1.15. 4.根据权利要求1所述的一种背接触太阳电池,其特征在于,当所述硅衬底为P型硅衬底,所有所述N型电极的总长度与所有所述P型电极的总长度的比值a为1<a≤1.5;4. A back-contact solar cell according to claim 1, characterized in that, when the silicon substrate is a P-type silicon substrate, a ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1<a≤1.5; 当所述硅衬底为N型硅衬底,所有所述P型电极的总长度与所有所述N型电极的总长度的比值b为1<b≤1.5。When the silicon substrate is an N-type silicon substrate, the ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1<b≤1.5. 5.根据权利要求4所述的一种背接触太阳电池,其特征在于,当所述硅衬底为P型硅衬底,所有所述N型电极的总长度与所有所述P型电极的总长度的比值a为1.001≤a≤1.2;5. A back-contact solar cell according to claim 4, characterized in that, when the silicon substrate is a P-type silicon substrate, a ratio a of the total length of all the N-type electrodes to the total length of all the P-type electrodes is 1.001≤a≤1.2; 当所述硅衬底为N型硅衬底,所有所述P型电极的总长度与所有所述N型电极的总长度的比值b为1.001≤a≤1.2。When the silicon substrate is an N-type silicon substrate, a ratio b of the total length of all the P-type electrodes to the total length of all the N-type electrodes is 1.001≤a≤1.2. 6.根据权利要求1所述的一种背接触太阳电池,其特征在于,所述N型掺杂层包括第一N型掺杂区,所述P型掺杂层包括第一P型掺杂区,所述第一N型掺杂区及所述第一P型掺杂区的长度方向均沿第一方向设置,所述第一N型掺杂区及所述第一P型掺杂区沿第二方向交替间隔排布,所述第一方向与所述第二方向交叉设置,6. A back-contact solar cell according to claim 1, characterized in that the N-type doping layer includes a first N-type doping region, the P-type doping layer includes a first P-type doping region, the length directions of the first N-type doping region and the first P-type doping region are both arranged along a first direction, the first N-type doping region and the first P-type doping region are alternately arranged along a second direction, and the first direction is arranged to intersect with the second direction, 所述第一N型掺杂区的宽度大于所述第一P型掺杂区的宽度。The width of the first N-type doping region is greater than the width of the first P-type doping region. 7.根据权利要求6所述的一种背接触太阳电池,其特征在于,所述N型掺杂层还包括第二N型掺杂区,同一所述第二N型掺杂区上沿第二方向排列有多个第一N型掺杂区,所述P型掺杂层还包括第二P型掺杂区,同一所述第二P型掺杂区上沿第二方向排列有多个第一P型掺杂区,所述第二N型掺杂区及所述第二P型掺杂区的长度方向沿第二方向设置,且相邻的所述第一N型掺杂区与所述第一P型掺杂区之间,所述第二N型掺杂区及所述第二P型掺杂区沿第一方向交替间隔排布,7. A back-contact solar cell according to claim 6, characterized in that the N-type doping layer further includes a second N-type doping region, and a plurality of first N-type doping regions are arranged along the second direction on the same second N-type doping region; the P-type doping layer further includes a second P-type doping region, and a plurality of first P-type doping regions are arranged along the second direction on the same second P-type doping region; the length directions of the second N-type doping region and the second P-type doping region are arranged along the second direction, and between adjacent first N-type doping regions and first P-type doping regions, the second N-type doping regions and the second P-type doping regions are alternately arranged along the first direction; 所述第二N型掺杂区的宽度大于所述第二P型掺杂区的宽度。The width of the second N-type doping region is greater than the width of the second P-type doping region. 8.根据权利要求7所述的一种背接触太阳电池,其特征在于,所述N型电极包括第一N型电极,所述第一N型电极的长度方向沿第一方向设置,所述第一N型电极设于所述第一N型掺杂区外侧;所述P型电极包括第一P型电极,所述第一P型电极的长度方向沿第一方向设置,所述第一P型电极设于所述第一P型掺杂区外侧;8. A back-contact solar cell according to claim 7, characterized in that the N-type electrode comprises a first N-type electrode, the length direction of the first N-type electrode is arranged along the first direction, and the first N-type electrode is arranged outside the first N-type doping region; the P-type electrode comprises a first P-type electrode, the length direction of the first P-type electrode is arranged along the first direction, and the first P-type electrode is arranged outside the first P-type doping region; 或者,所述N型电极包括第一N型电极和第二N型电极,所述第一N型电极的长度方向沿第一方向设置,所述第二N型电极的长度方向沿第二方向设置,所述第一N型电极设于所述第一N型掺杂区外侧,所述第二N型电极设于所述第二N型掺杂区外侧;所述P型电极包括第一P型电极和第二P型电极,所述第一P型电极的长度方向沿第一方向设置,所述第二P型电极的长度方向沿第二方向设置,所述第一P型电极设于所述第一P型掺杂区外侧,所述第二P型电极设于所述第二P型掺杂区外侧。Alternatively, the N-type electrode includes a first N-type electrode and a second N-type electrode, the length direction of the first N-type electrode is arranged along the first direction, the length direction of the second N-type electrode is arranged along the second direction, the first N-type electrode is arranged outside the first N-type doping region, and the second N-type electrode is arranged outside the second N-type doping region; the P-type electrode includes a first P-type electrode and a second P-type electrode, the length direction of the first P-type electrode is arranged along the first direction, the length direction of the second P-type electrode is arranged along the second direction, the first P-type electrode is arranged outside the first P-type doping region, and the second P-type electrode is arranged outside the second P-type doping region. 9.根据权利要求6所述的一种背接触太阳电池,其特征在于,所述第一N型掺杂区的宽度与所述第一P型掺杂区的宽度的比值c为1<c≤9。9 . The back-contact solar cell according to claim 6 , wherein a ratio c of a width of the first N-type doping region to a width of the first P-type doping region is 1<c≤9. 10.根据权利要求9所述的一种背接触太阳电池,其特征在于,所述第一N型掺杂区的宽度与所述第一P型掺杂区的宽度的比值c为1.4<c≤4.5。10 . The back-contact solar cell according to claim 9 , wherein a ratio c of a width of the first N-type doping region to a width of the first P-type doping region is 1.4<c≤4.5. 11.根据权利要求6所述的一种背接触太阳电池,其特征在于,所述第一P型掺杂区的宽度为100μm~900μm。11 . The back-contact solar cell according to claim 6 , wherein a width of the first P-type doping region is 100 μm to 900 μm. 12.根据权利要求11所述的一种背接触太阳电池,其特征在于,所述第一P型掺杂区的宽度为200μm~500μm。12 . The back-contact solar cell according to claim 11 , wherein a width of the first P-type doping region is 200 μm to 500 μm. 13.根据权利要求6所述的一种背接触太阳电池,其特征在于,相邻的所述第一N型掺杂区及所述第一P型掺杂区之间设有用于将两者间隔开来的隔离区,单个所述第一N型掺杂区、两个所述隔离区及单个所述第一P型掺杂区之间的宽度之和为0.3mm~3mm。13. A back-contact solar cell according to claim 6, characterized in that an isolation region is provided between adjacent first N-type doping regions and first P-type doping regions for separating the two, and the sum of the widths of a single first N-type doping region, two of the isolation regions and a single first P-type doping region is 0.3 mm to 3 mm. 14.根据权利要求13所述的一种背接触太阳电池,其特征在于,单个所述第一N型掺杂区、两个所述隔离区及单个所述第一P型掺杂区之间的宽度之和为0.5mm~1.6mm。14 . The back-contact solar cell according to claim 13 , wherein the sum of the widths of the single first N-type doping region, the two isolation regions and the single first P-type doping region is 0.5 mm to 1.6 mm. 15.根据权利要求1所述的一种背接触太阳电池,其特征在于,所述硅衬底的掺杂浓度小于5×1014cm-3,所述硅衬底的电导率小于2S/cm。15 . The back-contact solar cell according to claim 1 , wherein the doping concentration of the silicon substrate is less than 5×10 14 cm −3 , and the conductivity of the silicon substrate is less than 2 S/cm. 16.根据权利要求1所述的一种背接触太阳电池,其特征在于,所述P型掺杂层及所述N型掺杂层的电导率之间的比值为1:2~6.5。16 . The back-contact solar cell according to claim 1 , wherein a ratio of the conductivity of the P-type doped layer to the conductivity of the N-type doped layer is 1:2 to 6.5. 17.根据权利要求1所述的一种背接触太阳电池,其特征在于,所述N型掺杂层的电导率为600ohm-1.cm-1~2800ohm-1.cm-1,所述P型掺杂层的电导率为150ohm-1.cm-1~580ohm-1.cm-117 . The back-contact solar cell according to claim 1 , wherein the conductivity of the N-type doped layer is 600 ohm -1 .cm -1 to 2800 ohm -1 .cm -1 , and the conductivity of the P-type doped layer is 150 ohm -1 .cm -1 to 580 ohm -1 .cm -1 . 18.根据权利要求17所述的一种背接触太阳电池,其特征在于,所述N型掺杂层的电导率为1000ohm-1.cm-1~1800ohm-1.cm-1,所述P型掺杂层的电导率为240ohm-1.cm-1~450ohm- 1.cm-118 . The back-contact solar cell according to claim 17 , wherein the conductivity of the N-type doped layer is 1000 ohm -1 .cm -1 to 1800 ohm -1 .cm -1 , and the conductivity of the P-type doped layer is 240 ohm -1 .cm -1 to 450 ohm -1 .cm -1 . 19.根据权利要求1所述的一种背接触太阳电池,其特征在于,所述P型掺杂层的方阻大于所述N型掺杂层的方阻。19 . The back-contact solar cell according to claim 1 , wherein the sheet resistance of the P-type doped layer is greater than the sheet resistance of the N-type doped layer. 20.根据权利要求19所述的一种背接触太阳电池,其特征在于,所述P型掺杂层的方阻为所述N型掺杂层的方阻的1.5倍~10倍。20 . The back-contact solar cell according to claim 19 , wherein the sheet resistance of the P-type doped layer is 1.5 to 10 times that of the N-type doped layer. 21.根据权利要求19所述的一种背接触太阳电池,其特征在于,所述N型掺杂层的方阻为26ohm/sq~150ohm/sq,所述P型掺杂层的方阻为80ohm/sq~400ohm/sq。21 . The back-contact solar cell according to claim 19 , wherein the sheet resistance of the N-type doped layer is 26 ohm/sq to 150 ohm/sq, and the sheet resistance of the P-type doped layer is 80 ohm/sq to 400 ohm/sq. 22.根据权利要求20所述的一种背接触太阳电池,其特征在于,所述N型掺杂层的方阻为35ohm/sq~120ohm/sq,所述P型掺杂层的方阻为90ohm/sq~350ohm/sq。22. The back-contact solar cell according to claim 20, characterized in that the sheet resistance of the N-type doped layer is 35 ohm/sq to 120 ohm/sq, and the sheet resistance of the P-type doped layer is 90 ohm/sq to 350 ohm/sq. 23.根据权利要求1所述的一种背接触太阳电池,其特征在于,所述背光面上还设有钝化层,所述钝化层设于所述N型掺杂层及所述P型掺杂层背向所述硅衬底的一侧,且所述钝化层设有第一窗口及第二窗口,所述N型电极至少部分伸入于所述第一窗口内,与所述N型掺杂层相接触,所述P型电极至少部分伸入于所述第二窗口内,与所述P型掺杂层相接触。23. A back-contact solar cell according to claim 1, characterized in that a passivation layer is also provided on the backlight surface, the passivation layer is provided on the side of the N-type doped layer and the P-type doped layer facing away from the silicon substrate, and the passivation layer is provided with a first window and a second window, the N-type electrode at least partially extends into the first window and contacts with the N-type doped layer, and the P-type electrode at least partially extends into the second window and contacts with the P-type doped layer. 24.一种电池组件,其特征在于,包括根据权利要求1至23任意一项所述的一种背接触太阳电池。24. A battery assembly, characterized in that it comprises a back-contact solar cell according to any one of claims 1 to 23. 25.一种光伏系统,其特征在于,包括权利要求24所述的电池组件。25. A photovoltaic system, comprising the battery assembly according to claim 24.
CN202411059326.1A 2024-08-03 2024-08-03 Back contact solar cell, battery assembly and photovoltaic system Pending CN119133280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202411059326.1A CN119133280A (en) 2024-08-03 2024-08-03 Back contact solar cell, battery assembly and photovoltaic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202411059326.1A CN119133280A (en) 2024-08-03 2024-08-03 Back contact solar cell, battery assembly and photovoltaic system

Publications (1)

Publication Number Publication Date
CN119133280A true CN119133280A (en) 2024-12-13

Family

ID=93758573

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202411059326.1A Pending CN119133280A (en) 2024-08-03 2024-08-03 Back contact solar cell, battery assembly and photovoltaic system

Country Status (1)

Country Link
CN (1) CN119133280A (en)

Similar Documents

Publication Publication Date Title
JP7168800B1 (en) Solar cells and photovoltaic modules
US20190245101A1 (en) Solar cell
EP2867926B1 (en) Solar cell
US10522705B2 (en) Solar cell and solar cell module
CN102254970A (en) Solar cell module
KR20100118574A (en) Group iii-nitride solar cell with graded compositions
CN104810412A (en) solar cell and module thereof
US20240204121A1 (en) Solar cell and photovoltaic module
US20130160840A1 (en) Solar cell
US20240429325A1 (en) Back-contact solar cell, solar cell structure, and photovoltaic module
KR20230116748A (en) Solar cell and photovoltaic modules
CN104638047A (en) back contact solar cell
CN216311796U (en) Back contact solar cell with passivated contact
US20250221088A1 (en) Solar cell and photovoltaic module
TW201419559A (en) Solar cell with thick and thin bus bar electrodes
CN119133280A (en) Back contact solar cell, battery assembly and photovoltaic system
KR101032064B1 (en) Solar cell and manufacturing method thereof
CN213401222U (en) Silicon heterojunction solar cell
CN112086536B (en) A tandem solar cell
CN119133279A (en) Back contact solar cells, battery modules and photovoltaic systems
KR101310518B1 (en) Solar cell and method of manufacturing the same
JP2023033940A (en) Solar battery cell and solar battery
EP2610917A2 (en) Solar cell having buried electrode
CN220041872U (en) Back contact battery and photovoltaic module
CN223067451U (en) A solar cell and photovoltaic module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination