CN119110583B - SRAM cell structure and memory - Google Patents
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- CN119110583B CN119110583B CN202411598359.3A CN202411598359A CN119110583B CN 119110583 B CN119110583 B CN 119110583B CN 202411598359 A CN202411598359 A CN 202411598359A CN 119110583 B CN119110583 B CN 119110583B
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Abstract
本申请涉及半导体技术领域，具体而言涉及一种SRAM单元结构和存储器。SRAM单元结构包括：半导体衬底，在半导体衬底上形成有第一晶体管和第二晶体管，第一晶体管包括：第一栅极结构，第一栅极结构的两侧壁上分别形成有第一间隙壁和第二间隙壁，第二晶体管包括第二栅极结构和有源区，有源区内形成有掺杂区，掺杂区位于第二栅极结构的外侧，第二间隙壁靠近掺杂区，第二间隙壁的高度低于第一栅极结构的高度；共享接触孔，共享接触孔电连接第一晶体管的第一栅极结构和第二晶体管的掺杂区，共享接触孔包括第一部分，第一部分覆盖至少部分第二间隙壁。本发明的SRAM单元结构，共享接触孔不会直接落在硅层上，解决了共享接触孔因刻蚀过度引起的高漏电问题。
The present application relates to the field of semiconductor technology, and specifically to an SRAM cell structure and a memory. The SRAM cell structure includes: a semiconductor substrate, a first transistor and a second transistor are formed on the semiconductor substrate, the first transistor includes: a first gate structure, a first spacer and a second spacer are formed on the two side walls of the first gate structure, respectively, the second transistor includes a second gate structure and an active area, a doped area is formed in the active area, the doped area is located outside the second gate structure, the second spacer is close to the doped area, and the height of the second spacer is lower than the height of the first gate structure; a shared contact hole, the shared contact hole electrically connects the first gate structure of the first transistor and the doped area of the second transistor, the shared contact hole includes a first part, and the first part covers at least part of the second spacer. In the SRAM cell structure of the present invention, the shared contact hole will not fall directly on the silicon layer, which solves the problem of high leakage caused by excessive etching of the shared contact hole.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SRAM (static random Access memory) unit structure and a memory.
Background
A stripe (stripe) Static Random-Access Memory (SRAM) is a Memory device commonly used for a logic platform, and a common SRAM cell layout is shown in fig. 1, and includes a stripe-shaped active area (ACTIVE AREA, AA) 1, a Gate (GT) 2, a Contact (CT) 3, and a Metal-wiring (Metal-1, m 1) 4.
As the device advanced process iterates the device size shrinks, the SRAM size also shrinks, resulting in the stripe structure SRAM replacing the original two square contact holes (square-CT) with the shared contact holes (square-CT). However, the inherent defects and weaknesses formed in the manufacturing process of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) are difficult to meet the etching requirement under the conventional shared contact hole. Moreover, when etching the contact hole, it is difficult to achieve both the etching amount and depth under different morphologies and different contact hole sizes. Generally, share-CT is easy to cause high electric leakage due to excessive etching because of larger size and wider etching range.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the problems existing at present, an aspect of an embodiment of the present invention provides an SRAM cell structure, including:
A semiconductor substrate, on which a first transistor and a second transistor are formed, wherein the first transistor comprises a first gate structure, a first spacer and a second spacer are respectively formed on two side walls of the first gate structure, the second transistor comprises a second gate structure and an active region, a doped region is formed in the active region, the doped region is positioned on the outer side of the second gate structure, the second spacer is close to the doped region, and the height of the second spacer is lower than that of the first gate structure;
The shared contact hole is electrically connected with the first grid structure of the first transistor and the doped region of the second transistor, and comprises a first part which covers at least part of the second clearance wall.
In one embodiment, the shared contact hole further comprises a second portion and a third portion, the third portion covering at least a portion of a surface of the doped region, the second portion being located between the first portion and the third portion, wherein,
The width of the second portion is smaller than the width of the first portion and smaller than the width of the third portion, and/or
The third portion has a width greater than a width of the first portion.
In one embodiment, the semiconductor device further comprises a metal silicide formed in the doped region, and the shared contact hole covers at least a portion of the metal silicide, wherein the second portion spans the metal silicide near an edge of the second spacer.
In one embodiment, the second portion and the third portion form a step at the bottom of the shared contact hole.
In one embodiment, the shared contact hole further comprises a fourth portion covering at least part of the surface of the doped region, the fourth portion being located between the second portion and the third portion, wherein,
The fourth portion has a width that is greater than the width of the second portion and less than the width of the third portion.
In one embodiment, a bottom surface of the second portion and/or the fourth portion is spaced from a surface of the doped region by a predetermined distance that is greater than 0 and less than or equal to a height of the second spacer.
In one embodiment, the semiconductor device further comprises a first interlayer medium, the first interlayer medium is located at the junction of the second spacer and the doped region, and the second part further covers the first interlayer medium.
In one embodiment, the semiconductor device further comprises a second interlayer dielectric, the second interlayer dielectric is located above the doped region, and the fourth part further covers the second interlayer dielectric.
In one embodiment, the first transistor and the second transistor are fin field effect transistors or metal-oxide semiconductor field effect transistors.
A second aspect of an embodiment of the present invention provides a memory comprising an SRAM cell structure as described above.
According to the SRAM unit structure provided by the invention, the shared contact hole covers at least part of the gap wall, so that the shared contact hole cannot directly fall on the silicon layer, and the problem of high electric leakage caused by excessive etching of the shared contact hole is solved.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention. In the accompanying drawings:
FIG. 1 shows a layout of a prior art SRAM cell;
FIG. 2 illustrates a cross-sectional view of a prior art SRAM cell structure after a spacer corner has been pierced;
FIG. 3 illustrates a schematic cross-sectional view of an SRAM cell of one embodiment of the present invention;
FIG. 4 illustrates a schematic cross-sectional view of an SRAM cell prior to shared contact hole etching in accordance with one embodiment of the present invention;
FIG. 5 illustrates a schematic cross-sectional view of an SRAM cell prior to shared contact hole etching in accordance with one embodiment of the present invention;
FIG. 6 illustrates a schematic cross-sectional view of an SRAM cell after shared contact hole etching in accordance with one embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of an SRAM cell after shared contact hole etching and a layout corresponding to the shared contact hole according to another embodiment of the present invention;
Fig. 8 shows the layout of the SRAM cell where the shared contact hole 3a is located.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Because Share-CT has a large size and a wide etching range, and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) manufacturing process forms intrinsic defects and weaknesses such as a spacer corner (corner) and an active region corner, it is difficult to satisfy etching requirements under a conventional shared contact hole. For example, the spacer at the coverage of the shared contact hole is etched, because the metal silicide (Silicide) cannot be made under the spacer, the shared contact hole falls on the silicon layer, the corner of the active region (indicated by the arrow in the figure) is pierced to form high electric leakage, as shown in fig. 2, the shared contact Kong Shifa is easy to be over-etched during etching, the oxide layer is easy to be etched away during etching of the spacer to form a side-draw, so that the silicon nitride (SiN) deposited at the corner of the spacer (indicated by the arrow in the figure) is thinner and just located at the end of the metal silicide, and thus pierces at the corner of the spacer.
In order to avoid high leakage caused by over etching at the defect and weak point of the MOSFET, an embodiment of the present invention proposes an SRAM cell structure, as shown in fig. 3, comprising:
A semiconductor substrate, on which a first transistor and a second transistor are formed, wherein the first transistor includes a first gate structure 11, a first spacer 21 and a second spacer 22 are formed on two sidewalls of the first gate structure 11, respectively, the second transistor includes a second gate structure (not shown in the figure) and an active region 30, a doped region 31 is formed in the active region 30, the doped region 31 is located outside the second gate structure, the second spacer 22 is close to the doped region 31, and the height of the second spacer 22 is lower than the height of the first gate structure 11;
A shared contact hole 40, wherein the shared contact hole 40 electrically connects the first gate structure 11 of the first transistor and the doped region 31 of the second transistor, and the shared contact hole 40 includes a first portion 41, and the first portion 41 covers at least part of the second spacer 22.
In the present application, the semiconductor substrate may be silicon or silicon-on-insulator (SOI). Isolation structures are formed in a semiconductor substrate, the isolation structures being Shallow Trench Isolation (STI) structures or local silicon oxide (LOCOS) isolation structures. Various well (well) structures and channel layers on the substrate surface are also formed in the semiconductor substrate. Generally, the ion doped conductivity type of the well (well) structure is the same as that of the channel layer, but the concentration is lower than that of the gate channel layer, the ion implantation depth is wider, and the depth of the isolation structure is required to be larger than that of the isolation structure.
Here, the first gate structure 11 and the second gate structure may include various materials including, but not limited to, certain metals, metal alloys, metal nitrides, and metal silicides, and laminates and composites thereof. The gate may also include doped polysilicon and polysilicon-germanium alloy materials (i.e., having a doping concentration of from about 1e18 to about 1e22 doping atoms per cubic centimeter) as well as polysilicon metal silicide (polycide) materials (doped polysilicon/metal silicide stack materials). Similarly, any of several methods may be used to form the foregoing materials. In one embodiment, the gate is comprised of a polysilicon material. The gate electrode may be formed by any known technique known to those skilled in the art, and is preferably formed by chemical vapor deposition, such as low pressure plasma chemical vapor deposition or plasma enhanced chemical vapor deposition. The gate has a thickness of 800 to 3000 angstroms.
Fig. 4 is a schematic cross-sectional view of an SRAM cell before etching a shared contact hole according to an embodiment of the present invention, as shown in fig. 4, a doped region 31 is formed in the active region 30 by implantation, and a first spacer 21 and a third spacer 23 are formed on two sidewalls of the first gate structure 11, respectively, for isolating the gate from the drain/source, and may be used as a mask for an ion implantation process for forming the drain/source region. The first gate structure 11, the first spacers 21, the third spacers 23, and the active region 30 are covered with a contact hole etch stop layer 50 and an interlayer dielectric 60, and the interlayer dielectric 60 is formed on the contact hole etch stop layer 50. The contact etch stop layer 50 is typically a silicon nitride film.
If the process is not optimized, the third spacer 23 is completely etched, the shared contact hole is stopped above the active region 30, and the metal silicide cannot be formed under the spacer, and over-etching is easily generated at the metal silicide, so that the problem of leakage is easily caused.
In the present application, during etching the shared contact hole, the etching depth needs to be reduced above the spacer to reserve a portion of the spacer, so that after the etching of the shared contact hole 40 is completed, the second spacer 22 is obtained due to the etching of the portion of the third spacer 23, that is, the second spacer 22 is a residual spacer formed after etching the shared contact hole.
The first spacers 21 and the second spacers 22, which may include nitride, oxynitride, or a combination thereof, are formed by deposition and etching. The spacer structures may have different thicknesses, but the thickness of the spacer structures is typically 10 to 30nm, measured from the bottom surface.
In the present application, the shared contact hole 40 is composed of at least a first contact hole and a second contact hole, where the first contact hole and the second contact hole are divided according to an etching process, not according to a structure. During etching, the first contact hole is etched first, the second contact hole is etched, and through the steps, the shared contact hole formed by the first contact hole and the second contact hole is formed in the SRAM area finally.
Specifically, when etching the contact hole, the method comprises the following steps:
a contact layer is deposited (optional) by depositing a layer of a specific material, such as a barrier layer or contact layer, over the area where the contact hole is to be formed in order to form a precise contact hole during a subsequent etching process.
Coating photoresist and exposing and developing, namely, in order to form the contact hole, the photoresist is coated again, and a photoetching machine is used for projecting the designed contact hole pattern onto the photoresist, so that exposing and developing treatment is carried out.
And etching to form contact holes, namely etching the insulating layer by using an etching technology, and forming contact holes above the active region and the drain region respectively so as to be connected with the metal interconnection line.
After etching the contact hole, a tungsten filling and tungsten planarization process is adopted, and finally the shared contact hole 3 is formed.
According to the SRAM unit structure provided by the invention, the shared contact hole covers at least part of the gap wall, so that the shared contact hole cannot directly fall on the silicon layer, and the problem of high electric leakage caused by excessive etching of the shared contact hole is solved.
Next, a shared contact hole according to an embodiment of the present application is described with reference to fig. 5 and 6. It should be noted that, in order to avoid repetition, the same components and structures as in the foregoing embodiments will not be described in detail, and specific explanation and description thereof may be referred to the description in the foregoing embodiments.
As shown in fig. 6, according to one embodiment of the present application, the shared contact hole 40 further includes a second portion 42 and a third portion 43, the third portion covering at least a portion of the surface of the doped region 31, the second portion 42 being located between the first portion 41 and the third portion 43. At the bottom of the shared contact hole, the second portion and the third portion constitute a step.
In this embodiment, the shared contact hole 40 further includes a gate upper portion 401 covering the gate 11. That is, in the present embodiment, the shared contact hole 40 is composed of four parts in total.
The first portion 41, the second portion 42 and the third portion 43 have characteristic dimensions a, b and c, respectively, in cross-section. The method for determining the feature sizes a, b, c is described in detail below with reference to fig. 5.
FIG. 5 shows a schematic cross-sectional view of an SRAM cell prior to shared contact hole etching in accordance with one embodiment of the present invention, as shown in FIG. 5, the SRAM cell structure includes an active region 30, a first gate structure 11, a third spacer 23, a doped region 31, an interlayer dielectric 60, and an etch stop layer 50. In the figure, a is the maximum thickness of the spacer to be etched, i.e., the third spacer 23. In the figure b is the thickness of the contact etch stop layer 50 and c is the distance from the contact etch stop layer to the edge above the shared contact hole location.
In one embodiment, the device may be measured by a transmission electron microscope (Transmission Electron Microscope, TEM) to obtain a feature size (CD).
Illustratively, a and b are 115nm,35nm, respectively.
And when the shared contact hole is etched, the characteristic sizes of the shared contact holes at different MOSFET positions can be designed by controlling the sizes and the morphologies of the first part contact hole, the second part contact hole and the third part shared contact hole.
According to one embodiment of the present application, the SRAM cell structure further comprises a metal silicide formed in the doped region, the shared contact hole covering at least a portion of the metal silicide, wherein the second portion spans the metal silicide proximate an edge of the second spacer.
In this embodiment, the metal silicide process can achieve precise control and alignment of the contact area between the metal and silicon, thereby reducing contact resistance. And, because the second part spans the edge of the metal silicide close to the second spacer, the shared contact hole on the self-aligned silicide of the doped region can be ensured not to fall on the end of the self-aligned silicide.
In this embodiment, the bottom surface of the second portion is spaced from the surface of the doped region by a predetermined distance, where the predetermined distance is greater than 0 and less than or equal to the height of the second spacer.
In one specific implementation, when the bottom surface of the second portion is spaced from the surface of the doped region by a predetermined distance greater than the thickness of the etching stop layer, the SRAM cell structure further includes a first interlayer dielectric, the first interlayer dielectric being located at a junction between the second spacer and the doped region, and the second portion further covering the first interlayer dielectric. Specifically, the height of the first interlayer medium is greater than 0 and less than or equal to the height of the second spacer.
According to one embodiment of the application, the width of the second portion 42 is smaller than the width of the first portion 41 and smaller than the width of the third portion 43, and/or
The width of the third portion 43 is greater than the width of the first portion 41.
Here, the width of the second portion 42, the width of the first portion 41, and the width of the third portion 43 are all widths of portions in the chip plan view, that is, widths corresponding to portions in the layout.
Because of the design requirement of the SRAM memory cell, the distance from the contact hole to the polysilicon gate needs to be fixed, otherwise, the switching speed is changed, and the overlap between the contact hole and the polysilicon cannot be too small, otherwise, high resistance is caused, and the read-write is invalid under different voltages. Therefore, in this embodiment, by properly reducing the overlapping area of the shared contact hole and the polysilicon layer, when the shared contact hole window is reduced, the etching energy is reduced, and the etching depth is reduced, but the contact Kong Kailu is not caused.
Specifically, in the etching process, the size of the window of the etched shared contact hole is controlled, so that the etching speed is controlled, and under the condition that the resistance is not increased, the over-etching phenomenon of the shared contact hole is improved.
In the embodiment, the electric leakage problem in SRAM read-write/storage is improved through designing the SRAM shared contact hole layout, in addition, square contact holes can be compatible, the risk of open circuit/short circuit is avoided, the process difficulty is reduced, the size of the contact holes can be flexibly adjusted, the process window for etching the contact holes is further increased, and the damage to devices is reduced.
Next, a shared contact hole according to another embodiment of the present application is described with reference to fig. 7 to 8. In fig. 7, the red portion is a schematic cross-sectional view of the shared contact hole 3a in the SRAM cell, and the blue portion is a layout of the shared contact hole 3 a. Fig. 8 shows the layout of the SRAM cell where the shared contact hole 3a is located.
In this embodiment, the shared contact hole includes a gate upper portion 3a0, a first portion 3a1, a second portion 3a2, a third portion 3a3, and a fourth portion 3a4, the fourth portion 3a4 covering at least a portion of the surface of the doped region, the fourth portion 3a4 being located between the second portion 3a2 and the third portion 3a3, wherein,
The width of the fourth portion 3a4 is greater than the width of the second portion 3a2 and less than the width of the third portion.
Specifically, the width of the fourth portion is also the width of each portion in the chip in the top view, that is, the width corresponding to each portion in the layout.
Here, a bottom surface of the fourth portion is spaced apart from a surface of the doped region by a predetermined distance, the predetermined distance being greater than 0 and less than or equal to a height of the second spacer.
When the bottom surface of the fourth part is spaced from the surface of the doped region by a predetermined distance greater than the thickness of the etching stop layer, the SRAM cell structure further comprises a second interlayer medium, the second interlayer medium is located above the doped region, and the fourth part further covers the second interlayer medium.
According to one embodiment of the application, the first transistor and the second transistor are fin field effect transistors or metal-oxide semiconductor field effect transistors.
When the transistors are all metal-oxide semiconductor field effect transistors, the SRAM structure in the present application is a Strip (Strip) SRAM.
Example two
The present invention also provides a memory comprising the SRAM cell structure of the first embodiment.
The memory of the embodiment of the invention has better memory performance due to the SRAM unit structure in the first embodiment.
Example III
In another embodiment of the present invention, an electronic device is provided, including the foregoing memory.
The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, and the like, and may also be any intermediate product including a circuit. The electronic device provided by the embodiment of the invention has better performance due to the use of the memory.
Although a number of embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and alterations may be made in the arrangement and/or component parts of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and variations in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Claims (9)
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