CN119087719A - Array substrate, manufacturing method thereof, display panel and display device - Google Patents

Abstract

The array substrate comprises a substrate, an electrode layer and a grid layer, wherein the electrode layer is positioned on the substrate and comprises a plurality of first signal lines, the grid layer is positioned on one side of the electrode layer far away from the substrate and comprises a plurality of second signal lines, the second signal lines are in contact with the first signal lines, and orthographic projection of the second signal lines on the substrate coincides with orthographic projection of the first signal lines on the substrate.

Description

Array substrate, manufacturing method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof, a display panel and a display device.

Background

The thin film transistor liquid crystal display (Thin Film Transistor Liquid CRYSTAL DISPLAY, TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation, portability, etc., has been rapidly developed in recent years, has gradually replaced the conventional cathode ray tube display device (Cathode Ray Tube display, CRT), and has been dominant in the current flat panel display market. At present, TFT-LCDs are widely used in various large, medium and small-sized products, and almost cover the main electronic products of the current information society, such as liquid crystal televisions, high definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigators, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and illusive displays.

Disclosure of Invention

The embodiment of the disclosure provides an array substrate, a manufacturing method thereof, a display panel and a display device, which are used for reducing parasitic capacitance and load of grid lines, solving relevant defects such as V-CT, flicker and the like and improving product quality.

Therefore, the embodiment of the disclosure provides an array substrate, a manufacturing method thereof, a display panel and a display device, and the specific scheme is as follows:

In one aspect, an array substrate provided by an embodiment of the present disclosure includes:

A substrate base;

An electrode layer located over the substrate base plate, the electrode layer including a plurality of first signal lines;

The grid electrode layer is positioned on one side, far away from the substrate, of the electrode layer, the grid electrode layer comprises a plurality of second signal lines, the second signal lines are in contact with the first signal lines, and orthographic projection of the second signal lines on the substrate coincides with orthographic projection of the first signal lines on the substrate.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the first signal line includes a first gate line and a first common electrode line, and the second signal line includes a second gate line corresponding to the first gate line and a second common electrode line corresponding to the first common electrode line.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the first signal line further includes a first auxiliary line located at a side of the first gate line away from the first common electrode line, and the second signal line further includes a second auxiliary line corresponding to the first auxiliary line.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the first auxiliary line and the second auxiliary line are a common electrode line or a floating arrangement.

In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, at least one of the second gate line, the second common electrode line, and the second auxiliary line includes a main line, and a plurality of bump structures located on at least one side of the main line.

In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the first signal line includes a first fanout line, and the second signal line includes a second fanout line corresponding to the first fanout line.

Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing an array substrate, including:

Providing a substrate base plate;

Sequentially coating an electrode layer, a grid layer and first photoresist on the substrate;

Exposing and developing the first photoresist by adopting a half-tone mask plate so as to keep the first photoresist corresponding to a semi-permeable area and a full-permeable area of the half-tone mask plate;

Etching the gate layer and the electrode layer under the protection of the first photoresist to form a first pattern of the electrode layer and a second pattern of the gate layer;

coating a second photoresist such that the second photoresist fills the first gaps of the first pattern and the second gaps of the second pattern and covers the first photoresist;

Ashing the first photoresist and the second photoresist to remove the first photoresist and the second photoresist of the semi-permeable region, and partially removing the first photoresist and the second photoresist at the first gap and the second gap, so that the second pattern of the semi-permeable region is exposed, and the first pattern at both sides of the first gap and the second pattern at both sides of the second gap are covered and protected by the first photoresist and the second photoresist;

Etching to remove the second pattern of the semi-permeable region under the protection of the first photoresist and the second photoresist, wherein the reserved second pattern comprises a plurality of second signal lines of the grid layer, and the first pattern overlapped with the plurality of second signal lines in the electrode layer is a plurality of first signal lines;

and stripping off the first photoresist and the second photoresist.

In some embodiments, in the above manufacturing method provided in the embodiments of the present disclosure, coating the second photoresist specifically includes:

and coating a second photoresist with the thickness 1.2-2 times of the sum of the thicknesses of the electrode layer and the gate layer.

In some embodiments, in the foregoing manufacturing method provided by the embodiments of the present disclosure, ashing the first photoresist and the second photoresist specifically includes:

And ashing the first photoresist and the second photoresist according to the ashing amount which is 1.2-2 times of the sum of the thicknesses of the first photoresist and the second photoresist in the semi-permeable region.

In some embodiments, in the above manufacturing method provided in the embodiments of the present disclosure, etching the gate layer and the electrode layer to form a first pattern of the electrode layer and a second pattern of the gate layer specifically includes:

Etching the grid electrode layer to form a second pattern comprising a second grid line, a second common electrode line and a second fanout line;

Etching the electrode layer to form a first pattern comprising a first grid line, a first common electrode line and a first fan-out line, wherein the first grid line is overlapped with the second grid line, the first common electrode line is overlapped with the second common electrode line, and the first fan-out line is overlapped with the second fan-out line.

In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, etching the gate layer to form a second pattern including a second gate line and a second common electrode line, and simultaneously, etching to form a second auxiliary line located at a side of the second gate line away from the second common electrode line, where a line width of the second auxiliary line is greater than 1/2 of an etching deviation of the gate layer;

and etching the electrode layer to form a first pattern comprising a first grid line and a first common electrode line, and simultaneously, etching to form a first auxiliary line overlapped with the second auxiliary line.

On the other hand, the embodiment of the disclosure provides a display panel, which comprises the array substrate provided by the embodiment of the disclosure and an opposite substrate opposite to the array substrate.

On the other hand, the embodiment of the disclosure provides a display device, which comprises the display panel provided by the embodiment of the disclosure, and a backlight module positioned on the light incident side of the display panel.

The beneficial effects of the present disclosure are as follows:

The array substrate, the manufacturing method thereof, the display panel and the display device comprise a substrate, an electrode layer and a grid layer, wherein the electrode layer is positioned on the substrate and comprises a plurality of first signal lines, the grid layer is positioned on one side of the electrode layer far away from the substrate and comprises a plurality of second signal lines, the second signal lines are in contact with the first signal lines, and orthographic projection of the second signal lines on the substrate coincides with orthographic projection of the first signal lines on the substrate. The method eliminates ITO Tail, improves the image quality of the product, greatly reduces CD Bias, expands design/process Margin, can completely replace a 1+mask process, simultaneously reduces the cost compared with the 1+mask process, and shortens the production period.

Drawings

Fig. 1 is a picture of signal lines in a related art gate layer and electrode layer;

Fig. 2 is a schematic structural diagram of four sub-pixel regions in an array substrate according to an embodiment of the disclosure;

FIG. 3 is a schematic cross-sectional view taken along line I-I' of FIG. 2;

fig. 4 is a schematic structural diagram of a fanout line according to an embodiment of the present disclosure;

fig. 5 is a picture of signal lines in a gate layer and an electrode layer provided in an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of four sub-pixel regions in an array substrate according to an embodiment of the disclosure;

FIG. 7 is a schematic cross-sectional view taken along line II-II' of FIG. 6;

fig. 8 is a schematic structural diagram of four sub-pixel regions in an array substrate according to an embodiment of the disclosure;

Fig. 9 is a schematic structural diagram of four sub-pixel regions in an array substrate according to an embodiment of the disclosure;

Fig. 10 is a schematic structural diagram of four sub-pixel regions in an array substrate according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of four sub-pixel regions in an array substrate according to an embodiment of the disclosure;

FIG. 12 is a flowchart of a method for fabricating an array substrate provided by the present disclosure;

FIG. 13 is a process diagram of fabricating the array substrate of FIG. 2 using the fabrication method of FIG. 12;

FIG. 14 is a process diagram of the fabrication of the array substrate of FIG. 6 using the fabrication method of FIG. 12;

FIG. 15 is a process diagram of the fabrication of the array substrate of FIG. 4 using the fabrication method of FIG. 12;

Fig. 16 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

Fig. 17 is a schematic structural diagram of a display device according to an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It is noted that in the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described in this disclosure with reference to cross-sectional views that are schematic illustrations of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing techniques and/or tolerances, will be expected. Thus, the embodiments described in this disclosure should not be construed as limited to the particular shapes of regions as illustrated in this disclosure but are to include deviations in shapes that result, for example, from manufacturing. For example, the regions illustrated or described as flat may typically have rough and/or nonlinear features, the sharp corners illustrated may be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their sizes and shapes are not intended to illustrate the precise shape of a region and are not to reflect an actual scale, so as to merely schematically illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed description of known functions and known components.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.

In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on, connected to, or intervening elements or layers may be present. When an element or layer is referred to as being "disposed on" a side of another element or layer, it can be directly on the side of the other element or layer, be directly connected to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. The term "and/or" includes any and all combinations of one or more of the associated listed items.

With the progress of the transistor industry and the improvement of the process, the liquid crystal display has been rapidly developed. The advanced super-dimensional field switch ADS is used as a mode of a TFT-LCD display area structure, has the advantages of wide viewing angle, high aperture ratio, low chromatic aberration, low corresponding time and the like, and is applied to more and more products including mobile phones, computers, liquid crystal televisions and the like.

In the ADS mode TFT-LCD product, the TFT substrate mainly comprises a substrate, a first electrode layer (1 ITO), a Gate layer (Gate), a Gate insulating layer (GI), a source drain layer (SD), a passivation layer (PVX) and a second electrode layer (2 ITO) from bottom to top. The pattern production process of the first electrode layer and the grid layer is divided into a 0+mask process and a 1+mask process, wherein in the 0+mask process, the first electrode layer and the grid layer are combined into a composition process by adopting a half-tone Mask (HGA Mask), and in the 1+mask process, the pattern of the first electrode layer and the pattern of the grid layer are respectively subjected to the composition process. Compared with the 1+mask process, the 0+mask process can obviously shorten the production period, and a buffer layer is not needed under the grid layer, so that the cost can be reduced. However, the 0+mask process needs to perform two Gate layer etches (Gate Etch), resulting in larger size deviation (CD Bias) of the Gate layer pattern, reduced design/process Margin (Margin), and after etching the Gate layer for the 2 nd time, the Tail (ITO Tail) shown in fig. 1 is formed under the pattern of the Gate layer, and the parasitic capacitance Cgs of the Gate and source of the product or the parasitic capacitance Cdc of the data line and the common electrode line is large, so that the load is large, and related defects such as V-CT, flicker and the like are easily generated.

Because of the existence of the ITO Tail, high-end products such as 8K and the like all adopt a 1+mask process, although the influence of the ITO Tail is avoided, the production period is prolonged, the input of an integral device is required to be increased, and meanwhile, when a grid layer is manufactured subsequently, a buffer layer (buffer) is required to be added below the grid layer, so that the adhesion between metal and glass is conveniently increased, and the production cost is increased.

In order to solve the above technical problems, an embodiment of the present disclosure provides an array substrate, fig. 2 is a schematic structural view of four sub-pixel regions in the array substrate provided by the embodiment of the present disclosure, fig. 3 is a schematic structural view of a cross section along line I-I' in fig. 2, fig. 4 is a schematic structural view of a fanout line provided by the embodiment of the present disclosure, and fig. 5 is a picture of a signal line in a gate layer and an electrode layer provided by the embodiment of the present disclosure. As shown in fig. 2 to 5, an array substrate provided in an embodiment of the present disclosure includes:

The substrate 101 optionally includes a display area (AA) and a non-display area located on at least one side of the display area (AA), wherein in some embodiments, the display area (AA) includes red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. arranged in an array, and the substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

The electrode layer 102 is disposed on the substrate 101, the electrode layer 102 may include a plurality of first signal lines 1021 and a plurality of electrodes 1022, in some embodiments, the electrodes 1022 may be pixel electrodes (pixels) or common electrodes (com) arranged in an array in the display area AA, the first signal lines 1021 may include a first gate line GL1, a first common electrode line CL1, and the like in the display area AA, and a fan-out line FL in a non-display area, optionally, when the electrodes 1022 are common electrodes, the first common electrode line CL1 is integrally disposed with the electrodes 1022, and when the electrodes 1022 are pixel electrodes, the first common electrode line CL1 is spaced from the electrodes 1022, which is illustrated by taking the electrodes 1022 as the common electrodes. In some embodiments, the electrode layer 102 may include at least one transparent conductive material of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), aluminum Zinc Oxide (AZO), gallium Zinc Oxide (GZO), or the like.

The gate layer 103 is located on a side of the electrode layer 102 away from the substrate 101, the gate layer 103 includes a plurality of second signal lines 1031, the second signal lines 1031 are disposed in contact with the first signal lines 1021, and an orthographic projection of the second signal lines 1031 on the substrate 101 coincides with an orthographic projection of the first signal lines 1021 on the substrate 101. In some embodiments, the second signal line 1031 may include a second gate line GL2 contacting the first gate line GL1 and overlapping each other, a second common electrode line CL2 contacting the first common electrode line CL1 and overlapping each other, a second fanout line FL2 contacting the first fanout line FL1 and overlapping each other, and the like. In some embodiments, the material of the gate layer 103 may include at least one metal of gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., and the gate metal layer may have a single-layer structure or a stacked-layer structure, for example, the gate metal layer has a single-layer structure composed of a copper metal layer or a stacked-layer structure composed of a copper metal layer/a molybdenum metal layer. Moreover, it should be noted that, due to the limitation of the process conditions or the influence of other factors such as measurement, the "coincidence" may be exactly coincident, and some deviation may also be possible (for example, a deviation of ±0.5 μm), so the "coincidence" relationship between the related features is within the protection scope of the present disclosure as long as the error allowance is satisfied.

In some embodiments, the electrode layer 102 and the gate layer 103 of the present disclosure may be manufactured using a 0+mask process, unlike the conventional 0+mask process, the present disclosure further coats Photoresist (PR) after etching the gate layer 103 and the electrode layer 102 for the first time, fills the gaps at the edges of the signal line with the mobility and the pattern flatness of the PR, then solidifies again to form a protection, then performs PR Ashing (ashing) of the protection, removes PR glue in the semi-permeable region, etches the gate layer 103 for the second time, and finally strips off the photoresist (PR Strip) to form the final pattern of the gate layer 103 and the electrode layer 102. The final pattern of the gate layer 103 is completely protected in the secondary etching process, so that no etching loss exists, the alignment of the pattern of the gate layer 103 and the pattern of the electrode layer 102 contacted below the pattern is ensured, ITO Tail is completely eliminated, the image quality of a product is improved, CD Bias is greatly reduced, the design/process Margin is enlarged, the 1+mask process can be completely replaced, meanwhile, the cost is reduced compared with the 1+mask process, and the production period is shortened. In addition, under the condition that the yield is not influenced, namely, the Fanout SPACE MASK CD and the Fanout FICD are unchanged, the Fanout Pitch (sum of Space & LINE FINAL CD) is obviously reduced by eliminating the ITO Tail and CD Bias maximization, the occupied Space is reduced, the resistance difference is optimized, the COF Block is improved, and an extremely narrow frame can be achieved.

In some embodiments, fig. 6 is a schematic structural diagram of four sub-pixel regions in the array substrate according to an embodiment of the disclosure, and fig. 7 is a schematic sectional structural diagram along the line II-II' in fig. 6. As shown in fig. 6 and 7, in the array substrate provided in the embodiment of the present disclosure, the first signal line 1021 may further include a first auxiliary line AL1 located at a side of the first gate line GL1 away from the first common electrode line CL1, and the second signal line 1031 further includes a second auxiliary line AL2 contacting and overlapping with the first auxiliary line AL. The first auxiliary line AL1 and the second auxiliary line AL2 can improve the heights of the two sides of the extending direction of the first gate line GL1 and the second gate line GL2, promote the filling of the second coated PR glue into the bottom gap, so that the PR glue effectively protects the final pattern of the gate layer 103 such as the second signal line 1031 in the process of etching the gate layer 103 for the second time, and eliminates the ITO tail. When the Mask CD of the first auxiliary line AL1 and the second auxiliary line AL2 is smaller (for example, the Mask CD of the first auxiliary line AL1 and the second auxiliary line AL2 is less than or equal to 1 ^st Gate Etch Bias/2), the first auxiliary line AL1 and the second auxiliary line AL2 can be completely etched in the process of etching the Gate layer 103 and the electrode layer 102 for the first time, the pixel area is not affected, but the flow of the PR glue coated for the second time to the bottom void is not promoted, and when the Mask CD of the first auxiliary line AL1 and the second auxiliary line AL2 is greater than 1 ^st Gate Etch Bias/2, the first auxiliary line AL1 and the second auxiliary line AL2 remain after the first etching the Gate layer 103 and the electrode layer 102, and the flow of the PR glue coated for the second time to the bottom void can be promoted. When the first auxiliary line AL1 and the second auxiliary line AL2 remain, they can be connected as a common electrode line, so as to increase the stability of the common voltage and improve the anti-flicker performance. Meanwhile, because the Gate Etch Bias is obviously reduced and the whole Margin is larger, the pixel area is enlarged, correspondingly, the design of a Black Matrix (BM) on the opposite substrate side (CF side) is very small, the product transmittance is obviously improved, and the first auxiliary line AL1 and the second auxiliary line AL2 are positioned in the BM and cannot influence the product performances such as transmittance and the like. In some embodiments, the first auxiliary line AL1 and the second auxiliary line AL2 may also be provided floating (floating).

In some embodiments, fig. 8 to 11 respectively show still another schematic structural diagram of four sub-pixel regions in an array substrate provided in an embodiment of the disclosure. As shown in fig. 8 to 11, at least one of the second gate line GL2, the second common electrode line CL2, and the second auxiliary line AL2 in the present disclosure may include a main line, and a plurality of bump structures located at least one side of the main line. Alternatively, the protruding structures may be triangular structures shown in fig. 8 and 9, square structures shown in fig. 10 and 11, or the like, and the protruding structures on both sides of the trunk line may be symmetrically arranged or asymmetrically arranged. By arranging the two sides of the second gate line GL2 in a zigzag shape, the edge unevenness thereof can be increased, so that the PR glue coated for the second time is easier to flow downwards for filling through the bump structure interval, and the stability is increased. It should be understood that, since the second gate line GL2, the second common electrode line CL2, and the second auxiliary line AL2 are respectively overlapped with the first gate line GL1, the first common electrode layer CL1, and the first auxiliary line AL1, in case that an edge of at least one of the second gate line GL2, the second common electrode line CL2, and the second auxiliary line AL2 has a zigzag design, at least one of the corresponding first gate line GL1, first common electrode line CL1, and first auxiliary line AL1 also has a zigzag design.

It should be noted that, if the edge of the fan-out line is set to be saw-tooth, the fan-out line is easy to be broken, and in some embodiments, in order to ensure that the lengths of the fan-out lines are the same, the fan-out lines at the edge of the fan-out area are designed in a straight line, the fan-out line in the middle of the fan-out line is designed in a bending way, and the design is easy to enable PR glue coated for the second time to flow into the bottom gap, so that a protruding structure is not required to be arranged at the edge of the fan-out line.

Based on the same inventive concept, the embodiment of the present disclosure provides a method for manufacturing the above-mentioned array substrate, and since the principle of the method for solving the problem is similar to that of the above-mentioned array substrate, the implementation of the method for manufacturing the above-mentioned array substrate provided by the embodiment of the present disclosure may refer to the implementation of the above-mentioned array substrate provided by the embodiment of the present disclosure, and the repetition is omitted.

In some embodiments, fig. 12 is a flowchart illustrating the above-mentioned manufacturing method provided in the present disclosure, fig. 13 is a process diagram of correspondingly manufacturing the array substrate illustrated in fig. 2 by using the manufacturing method illustrated in fig. 12, fig. 14 is a process diagram of correspondingly manufacturing the array substrate illustrated in fig. 6 by using the manufacturing method illustrated in fig. 12, and fig. 15 is a process diagram of correspondingly manufacturing the array substrate illustrated in fig. 4 by using the manufacturing method illustrated in fig. 12. As can be seen from fig. 12 to 15, the manufacturing method provided in the embodiment of the disclosure may include the following steps:

S1201, a substrate 101 is provided.

S1202, coating the electrode layer 102, the gate layer 102 and the first photoresist PR1 on the substrate 101 in order;

S1203, exposing and developing the first photoresist PR1 by adopting a half-tone Mask plate HGA Mask to reserve a first photoresist PR1 corresponding to a semi-transparent area HTA and a full-transparent area FTA of the half-tone Mask plate HGA Mask;

S1204, etching the gate layer 103 and the electrode layer 102 under the protection of the first photoresist PR1 to form a first pattern (including the first signal line 1021 and the electrode 1022) of the electrode layer 102 and a second pattern (including the second signal line 1031 overlapping the first signal line 1021 and the pattern 1032 overlapping the electrode 1022) of the gate layer 103;

S1205, coating the second photoresist PR2 such that the second photoresist PR2 fills the first gap of the first pattern (including the first signal line 1021 and the electrode 1022) and the second gap of the second pattern (including the second signal line 10321 overlapping the first signal line 1021 and the pattern 1032 overlapping the electrode 1022) and covers the first photoresist PR1;

S1206, ashing the first photoresist PR1 and the second photoresist PR2 to remove the first photoresist PR1 and the second photoresist PR2 of the semi-permeable area HTA, and partially removing the first gap, the first photoresist PR1 and the second photoresist PR2 at the second gap, so that the second pattern of the semi-permeable area HTA (including the pattern 1032 overlapping the electrode 1022) is exposed, the first pattern (including the first signal line 1021) at both sides of the first gap, and the second pattern (including the second signal line 10321 overlapping the first signal line 1021) at both sides of the second gap are covered and protected by the first photoresist PR1 and the second photoresist PR 2;

S1207, under the protection of the first photoresist PR1 and the second photoresist PR2, etching to remove the second pattern (including the pattern 1032 overlapped with the electrode 1022) of the semi-permeable area HTA, where the remaining second pattern includes a plurality of second signal lines 1031, and the first pattern overlapped with the plurality of second signal lines 1031 is a plurality of first signal lines 1021;

S1208, the first photoresist PR1 and the second photoresist PR2 are stripped off.

In some embodiments, in the above manufacturing method provided in the embodiments of the present disclosure, the step S1205 of coating the second photoresist may be specifically implemented by coating the second photoresist PR2 with a thickness 1.2-2 times the sum of the thicknesses of the electrode layer 102 and the gate layer 103, and optionally, the second photoresist PR2 is a positive photoresist. Therefore, the bottom gap of the first photoresist PR1 can be ensured to be completely filled with the second photoresist PR2, effective protection in the second etching process of the gate layer 103 is realized, the generation of ITO tail due to etching loss of the gate layer 103 is prevented, meanwhile, the overall thickness of the photoresist is ensured to be moderate, the cost of raw materials is saved, the time required for ashing off the HTA photoresist in the semipermeable area is saved, and the production efficiency is improved.

In some embodiments, in the above manufacturing method provided by the embodiments of the present disclosure, the step S1206 of ashing the first photoresist and the second photoresist may be specifically implemented by ashing the first photoresist PR1 and the second photoresist PR2 according to an ashing amount 1.2-2 times of the sum of thicknesses of the first photoresist PR1 and the second photoresist PR2 in the semi-permeable area HTA, so that the photoresist in the semi-permeable area HTA is completely ashed, and the photoresist in the full-permeable area FTA remains, and the ashing time is not too long, which is beneficial to improving the production efficiency.

In some embodiments, in the above manufacturing method provided in the embodiments of the present disclosure, as shown in fig. 13 to 15, step S1204, etching the gate layer 103 and the electrode layer 102 to form a first pattern of the electrode layer 102 and a second pattern of the gate layer 103 may specifically include the following steps:

etching the gate layer 103 to form a second pattern including a second gate line GL2, a second common electrode line CL2, and a second fanout line FL 2;

the electrode layer 102 is etched to form a first pattern including a first gate line GL1, a first common electrode line CL1, and a first fanout line FL1, wherein the first gate line GL1 overlaps with the second gate line GL2, the first common electrode line CL1 overlaps with the second common electrode line CL2, and the first fanout line FL1 overlaps with the second fanout line FL 2.

Optionally, as shown in fig. 14, the second auxiliary line AL2 on the side of the second Gate line GL2 away from the second common electrode line CL2 may be etched while the second pattern including the second Gate line GL2 and the second common electrode line CL2 is etched to form the second auxiliary line GL2, the line width of the second auxiliary line AL2 is greater than 1/2 of the etching deviation (1 ^st Gate etching Bias) of the Gate layer, and the first auxiliary line AL1 overlapping with the second auxiliary line AL2 may be etched while the electrode layer 102 is etched to form the first pattern including the first Gate line GL1 and the first common electrode line CL 1.

In the above manufacturing method provided by the embodiment of the present invention, the patterning process involved in forming each layer of structure may include not only a part or all of the process procedures of deposition, photoresist coating, mask masking, exposure, development, etching, photoresist stripping, and the like, but also other process procedures, specifically, the process of forming a pattern of a desired pattern in an actual manufacturing process is not limited herein. For example, a post bake process may also be included after development and before etching. The deposition process may be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a physical vapor deposition method, which are not limited herein, and the etching may be a dry etching or a wet etching, which are not limited herein.

Based on the same inventive concept, the embodiments of the present disclosure provide a display panel, and fig. 16 is a schematic structural diagram of the display panel provided by the embodiments of the present disclosure. As shown in fig. 16, the display panel of the present disclosure includes the above-described array substrate 001 provided in the embodiment of the present disclosure, and the opposite substrate 002 opposite to the array substrate 001. Since the principle of the display panel for solving the problems is similar to that of the array substrate, the implementation of the display panel can refer to the embodiment of the array substrate, and the repetition is omitted.

In some embodiments, in the above display panel provided by the embodiments of the present disclosure, as shown in fig. 16, a liquid crystal layer 003 may be further disposed between the array substrate 001 and the opposite substrate 002, a first polarizer 004 may be disposed on a side of the array substrate 001 away from the opposite substrate 002, a second polarizer 005 may be disposed on a side of the opposite substrate 002 away from the array substrate 001, and a polarization direction of the first polarizer 004 and a polarization direction of the second polarizer 005 are mutually perpendicular. Other essential components of the display panel will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the present disclosure.

Based on the same inventive concept, an embodiment of the present disclosure provides a display device, and fig. 17 is a schematic structural diagram of the display device provided by the embodiment of the present disclosure. As shown in fig. 17, the display device provided by the embodiment of the disclosure may include the display panel PNL provided by the embodiment of the disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side-in type backlight module. Alternatively, the side-entry backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, and the like, which are stacked, and the light bar is located at one side of the light guide plate in the thickness direction of the light guide plate. The direct type backlight module can comprise a matrix light source, a reflecting sheet, a diffusion plate, a brightness enhancement film and the like, wherein the reflecting sheet, the diffusion plate, the brightness enhancement film and the like are arranged on the light emitting side of the matrix light source in a stacked mode, and the reflecting sheet comprises an opening which is opposite to the position of each lamp bead in the matrix light source. The beads in the light bar, the beads in the matrix light source may be Light Emitting Devices (LEDs), such as quantum dot light emitting devices.

In some embodiments, the beads may also be Micro light emitting devices (e.g., mini LEDs, micro LEDs), etc., which are self-emitting devices on the order of submillimeter or even micrometer, as are Organic Light Emitting Devices (OLEDs). It has a series of advantages of high brightness, ultra low delay, ultra large visible angle, etc. as the organic light emitting device. And because the inorganic luminescent device emits light based on a metal semiconductor with more stable property and lower resistance, the inorganic luminescent device has the advantages of lower power consumption, higher high temperature and low temperature resistance and longer service life compared with an organic luminescent device which emits light based on an organic substance. And when the miniature light-emitting device is used as a backlight source, a more precise dynamic backlight effect can be realized, the glare phenomenon caused between the bright and dark areas of the screen by the traditional dynamic backlight can be solved while the brightness and the contrast of the screen are effectively improved, and the visual experience is optimized.

In some embodiments, the display device provided by the embodiments of the present disclosure may be any product or component having a display function, such as a television, a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, a smart watch, a gymnastic wristband, a personal digital assistant, and the like. Optionally, the display device provided by the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), or the like. For example, the control chip may further include a memory, a power module, and the like, and realize power supply and signal input/output functions through wires, signal lines, and the like that are additionally provided. For example, the control chip may also include hardware circuitry, computer-executable code, and the like. The hardware circuits may include conventional Very Large Scale Integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components, and may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, the above-described structure does not constitute a limitation of the above-described display device provided by the embodiments of the present disclosure, in other words, more or less of the above-described components may be included in the above-described display device provided by the embodiments of the present disclosure, or some components may be combined, or different component arrangements may be included.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims (13)

1. An array substrate, characterized by comprising:

A substrate base;

An electrode layer located over the substrate base plate, the electrode layer including a plurality of first signal lines;

The grid electrode layer is positioned on one side, far away from the substrate, of the electrode layer, the grid electrode layer comprises a plurality of second signal lines, the second signal lines are in contact with the first signal lines, and orthographic projection of the second signal lines on the substrate coincides with orthographic projection of the first signal lines on the substrate.

2. The array substrate of claim 1, wherein the first signal line includes a first gate line and a first common electrode line, and the second signal line includes a second gate line corresponding to the first gate line and a second common electrode line corresponding to the first common electrode line.

3. The array substrate of claim 2, wherein the first signal line further comprises a first auxiliary line located at a side of the first gate line away from the first common electrode line, and the second signal line further comprises a second auxiliary line corresponding to the first auxiliary line.

4. The array substrate of claim 3, wherein the first auxiliary line and the second auxiliary line are common electrode lines or floating.

5. The array substrate of claim 3 or 4, wherein at least one of the second gate line, the second common electrode line, and the second auxiliary line includes a main line, and a plurality of bump structures located at least one side of the main line.

6. The array substrate of any one of claims 1-4, wherein the first signal line comprises a first fanout line and the second signal line comprises a second fanout line corresponding to the first fanout line.

7. The manufacturing method of the array substrate is characterized by comprising the following steps of:

Providing a substrate base plate;

Sequentially coating an electrode layer, a grid layer and first photoresist on the substrate;

Exposing and developing the first photoresist by adopting a half-tone mask plate so as to keep the first photoresist corresponding to a semi-permeable area and a full-permeable area of the half-tone mask plate;

Etching the gate layer and the electrode layer under the protection of the first photoresist to form a first pattern of the electrode layer and a second pattern of the gate layer;

coating a second photoresist such that the second photoresist fills the first gaps of the first pattern and the second gaps of the second pattern and covers the first photoresist;

Ashing the first photoresist and the second photoresist to remove the first photoresist and the second photoresist of the semi-permeable region, and partially removing the first photoresist and the second photoresist at the first gap and the second gap, so that the second pattern of the semi-permeable region is exposed, and the first pattern at both sides of the first gap and the second pattern at both sides of the second gap are covered and protected by the first photoresist and the second photoresist;

Etching to remove the second pattern of the semi-permeable region under the protection of the first photoresist and the second photoresist, wherein the reserved second pattern comprises a plurality of second signal lines of the grid layer, and the first pattern overlapped with the plurality of second signal lines in the electrode layer is a plurality of first signal lines;

and stripping off the first photoresist and the second photoresist.

8. The method of manufacturing of claim 7, wherein applying the second photoresist comprises:

and coating a second photoresist with the thickness 1.2-2 times of the sum of the thicknesses of the electrode layer and the gate layer.

9. The method of claim 7, wherein ashing the first photoresist and the second photoresist, specifically comprising:

And ashing the first photoresist and the second photoresist according to the ashing amount which is 1.2-2 times of the sum of the thicknesses of the first photoresist and the second photoresist in the semi-permeable region.

10. The method of any one of claims 7 to 9, wherein etching the gate layer and the electrode layer to form a first pattern of the electrode layer and a second pattern of the gate layer specifically includes:

Etching the grid electrode layer to form a second pattern comprising a second grid line, a second common electrode line and a second fanout line;

Etching the electrode layer to form a first pattern comprising a first grid line, a first common electrode line and a first fan-out line, wherein the first grid line is overlapped with the second grid line, the first common electrode line is overlapped with the second common electrode line, and the first fan-out line is overlapped with the second fan-out line.

11. The method of claim 10, wherein etching the gate layer to form a second pattern including a second gate line and a second common electrode line, further comprises etching a second auxiliary line on a side of the second gate line away from the second common electrode line, wherein a line width of the second auxiliary line is greater than 1/2 of an etching deviation of the gate layer;

and etching the electrode layer to form a first pattern comprising a first grid line and a first common electrode line, and simultaneously, etching to form a first auxiliary line overlapped with the second auxiliary line.

12. A display panel, comprising the array substrate according to any one of claims 1 to 6, and an opposite substrate disposed opposite to the array substrate.

13. A display device comprising the display panel of claim 12, and a backlight module disposed on an incident side of the display panel.