CN100536145C - Pixel array structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a pixel array structure and a manufacturing method thereof. The pixel array structure comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel structures. The scanning lines and the data lines enclose a plurality of pixel regions. Each pixel structure is electrically connected with the corresponding scanning line and the corresponding data line. Each pixel structure is located in the corresponding pixel area. Each pixel structure comprises an active element, a pixel electrode electrically connected with the active element and a storage capacitor. The storage capacitor lower electrode is arranged at the periphery of the pixel area and partially overlapped with the pixel electrode to form a storage capacitor. The storage capacitor lower electrode comprises at least one first line segment adjacent to the data line and at least one second line segment adjacent to the scanning line. The first line segment and the second line segment are different film layers. The first line segment and one of the adjacent data lines are different film layers, and the second line segment and one of the adjacent scanning lines are different film layers. The pixel array structure and the manufacturing method thereof have higher qualification rate.

Description

Pixel array structure and manufacturing method thereof

technical field

The present invention relates to a pixel array structure and a manufacturing method thereof, and particularly relates to a pixel array structure with a high display aperture ratio and a manufacturing method thereof.

Background technique

Due to the increasing demand for displays and the rise of the concept of green environmental protection in recent years, thin film transistor liquid crystal displays (thin film transistor liquid crystal displays) have superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation. , TFT-LCD) has gradually become the mainstream of the display market. In order to meet the needs of users, the performance of thin film transistor liquid crystal displays is constantly moving towards high contrast ratio, no gray scale inversion, little color shift, and high luminance. , High color richness, high color saturation, fast response, stable display and wide viewing angle.

Generally speaking, a thin film transistor liquid crystal display is mainly composed of two substrates respectively configured with a pixel array and a color filter array, and a liquid crystal layer disposed between the two substrates. FIG. 1 is a partial schematic diagram of a known pixel array structure. The pixel array structure 100 includes a plurality of scan lines 102 , a plurality of data lines 104 and a plurality of pixel structures 110 electrically connected to the scan lines 102 and the data lines 104 . The scan lines 102 and the data lines 104 intersect to form a plurality of pixel regions P (only one is shown in FIG. 1 ), and the pixel structures 110 are disposed in the pixel regions P. The pixel structure 110 includes an active element 112 and a pixel electrode 114 . The active element 112 is electrically connected to one of the scan lines 102 and one of the data lines 104 , and the pixel electrode 114 is electrically connected to the active element 112 . In addition, the pixel array structure 100 further includes a storage capacitor bottom electrode 120 , which forms a storage capacitor with the pixel electrode 114 to maintain the stability of the image displayed by the pixel structure 110 . The lower electrodes 120 of these storage capacitors are mostly composed of large-area metal lines, which may affect the display aperture ratio of the pixel structure 100 . Therefore, the lower electrode 120 of the storage capacitor is mostly disposed around the pixel area P.

In fact, the lower electrode 120 of the storage capacitor is generally made of the same film layer as the scanning line 102 , so a sufficient distance d must be maintained between the lower electrode 120 of the storage capacitor and the scanning line 102 to avoid a short circuit between the two lines. In other words, in order to consider the yield of the process and avoid the short circuit between the storage capacitor bottom electrode 120 and the scan line 102 , the display aperture ratio of the pixel structure 110 must be sacrificed. If the pixel array structure 100 is applied to a transmissive liquid crystal display, it is necessary to improve the luminous performance of the backlight source to maintain proper display brightness. Therefore, the pixel array structure 100 cannot effectively save energy consumption. In order to maintain the stability of the display image of the pixel structure 110 while maintaining a good display aperture ratio and even further reducing energy consumption, it is necessary to improve the known pixel array structure 100 .

Contents of the invention

The present invention provides a pixel array structure to increase the display aperture ratio of the pixel array structure.

The invention also provides a manufacturing method of the pixel array structure, so as to improve the qualified rate of the manufacturing process of the pixel array structure and make the pixel array structure have a high display aperture ratio.

The present invention proposes a pixel array structure, including a plurality of scanning lines, a plurality of data lines and a plurality of pixel structures. The scan lines and the data lines surround a plurality of pixel areas, and each pixel structure is electrically connected to the corresponding scan lines and data lines. Each pixel structure is located in the corresponding pixel area. Each pixel structure includes an active element, a pixel electrode electrically connected to the active element, and a storage capacitor. The lower electrode of the storage capacitor is arranged around the pixel region and partially overlaps with the pixel electrode to form the storage capacitor. The lower electrode of the storage capacitor includes at least one first line segment adjacent to the data line and at least one second line segment adjacent to the scan line. The first line segment and the second line segment have different film layers, the first line segment and one of the adjacent data lines have different film layers, and the second line segment and one of the adjacent scan lines have different film layers.

The above pixel array structure, wherein the first line segment partially overlaps with the second line segment and is electrically connected.

The above pixel array structure, wherein the first line segment is of the same film layer as the scan line, and the second line segment is of the same film layer as the data line.

The above-mentioned pixel array structure, wherein the shape of the lower electrode of the storage capacitor is U-shaped or U-shaped, and the lower electrode of the storage capacitor includes two first line segments, and the two ends of the second line segment are respectively connected to the two The first line segments overlap and are electrically connected.

The invention also proposes a method for manufacturing the pixel array structure, which includes the following steps: forming a first metal layer on the substrate, the first metal layer including a plurality of gates, a plurality of scanning lines and a plurality of first line segments. The gate is connected to the scan line, and the first line segment is separated from the scan line. Next, a gate insulating layer and a semiconductor layer are sequentially formed on the substrate, and the gate insulating layer covers the first metal layer. Then, part of the gate insulating layer and part of the semiconductor layer are removed to form a patterned semiconductor layer and a plurality of contact windows. The patterned semiconductor layer is located above the gate and the contact window exposes the end of the first line segment. Subsequently, a second metal layer is formed on the substrate. The second metal layer includes a plurality of second line segments adjacent to the scan lines, a plurality of data lines adjacent to the first line segment, a plurality of sources and a plurality of drains connected to the data lines. The data lines intersect with the scan lines to form a plurality of pixel areas. The source and drain are located above the gate. The second line segment is electrically connected to the first line segment through the contact window to form a plurality of storage capacitor bottom electrodes, wherein the storage capacitor bottom electrodes are located around the pixel area. The above manufacturing method further includes: forming a protective layer on the substrate to cover the second metal layer; and forming a plurality of pixel electrodes on the protective layer, the pixel electrodes are electrically connected to the drain and the The pixel electrode partially overlaps with the lower electrode of the storage capacitor to form a storage capacitor.

The above-mentioned manufacturing method, wherein the method for forming the patterned semiconductor layer and the contact window includes: forming a patterned photoresist layer on the semiconductor layer, corresponding to each of the pixel regions, the patterned The photoresist layer has at least one opening, a first region and a second region outside the first region and the opening, the opening is located above the first line segment, the first region is located above the gate, and The thickness of the patterned photoresist layer in the first region is greater than the thickness in the second region; remove the semiconductor layer and the gate insulating layer exposed by the opening to form the contact window; remove the patterned photoresist layer of the second region; and removing the semiconductor layer in the second region.

The manufacturing method as above, wherein the forming method of the patterned photoresist layer comprises forming a photoresist material layer on the substrate and using a semi-transparent mask to pattern the photoresist material layer.

The above-mentioned manufacturing method, wherein the semi-transparent mask has a plurality of light-transmitting regions with different light transmittances.

The present invention adopts different film layers to make different line segments of the lower electrode of the storage capacitor, and each line segment of the lower electrode of the storage capacitor and adjacent scanning and data conductor lines are also of different film layers. Therefore, in the pixel array structure and its manufacturing method of the present invention, the lower electrode of the storage capacitor is less likely to be short-circuited with adjacent circuits. In other words, the pixel array structure and its manufacturing method of the present invention have a higher yield. In addition, in the pixel array structure of the present invention, there is no need to maintain a relatively large distance between the bottom electrode of the storage capacitor and its adjacent conductor lines in order to prevent short circuits. Therefore, the pixel array structure of the present invention has a higher display aperture ratio.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a partial schematic diagram of a known pixel array structure.

FIG. 2 is a schematic diagram of a pixel array structure according to an embodiment of the present invention.

FIG. 3 is a schematic top view of the pixel structure in FIG. 2 .

4A to 4D are cross-sectional views of the fabrication method of the pixel array structure in FIG. 2 along the section line AA'.

FIG. 5 is a schematic diagram of a semi-transparent mask according to an embodiment of the present invention.

6A to 6E show the method for manufacturing the patterned semiconductor layer and the contact window of the pixel array structure in FIG. 2 .

Wherein, the reference signs are explained as follows:

100, 200: pixel array structure

102, 202: scan line

104, 204: data line

110, 210: pixel structure

112, 212: active components

114, 214: pixel electrodes

120, 216: storage capacitor lower electrode

212A: Gate

212B: source

212C: drain

216A: first line segment

216B: Second line segment

218: contact window

400: Substrate

410: first metal layer

420: gate insulating layer

430: Patterning the semiconductor layer

432: Semiconductor layer

434: Undoped amorphous silicon layer

436: doped amorphous silicon layer

440: second metal layer

450: protective layer

500: semi-transparent mask

610: Patterning photoresist layer

612: opening

614: First Area

616: Second Area

A-A': section line

P: pixel area

T, T1, T2, T3: Translucent area

Detailed ways

FIG. 2 is a schematic diagram of a pixel array structure according to an embodiment of the present invention. Please refer to FIG. 2 , the pixel array structure 200 includes a plurality of scan lines 202 , a plurality of data lines 204 and a plurality of pixel structures 210 . The scan line 202 intersects with the data line 204 and encloses a plurality of pixel regions P. As shown in FIG. The pixel structure 210 is disposed in the pixel area P. Each pixel structure 210 includes an active element 212 , a pixel electrode 214 and a storage capacitor. The active element 212 is electrically connected to the corresponding scan line 202 and the data line 204 , and the pixel electrode 214 is electrically connected to the active element 212 .

The storage capacitor lower electrode 216 is disposed around the pixel region P, and the storage capacitor lower electrode 216 partially overlaps the pixel electrode 214 to form a storage capacitor. When the pixel structure 210 is displaying, the storage capacitor helps to maintain the display voltage of the pixel electrode 214 . Therefore, the image displayed by the liquid crystal display using the pixel array structure 200 is relatively stable, that is, there will be no afterimage or flicker in the displayed image. However, the storage capacitor bottom electrode 216 is made of opaque metal material, so the configuration of the storage capacitor bottom electrode 216 may affect the display aperture ratio of the pixel structure 210 . In order to solve the above problems, the present invention proposes to manufacture the lower electrode 216 of the storage capacitor in sections with different film layers, so that the short circuit between the lower electrode 216 of the storage capacitor and the adjacent circuit is less likely to occur. In this way, the distance between the lower electrode 216 of the storage capacitor and the adjacent lines can be shortened to increase the display aperture ratio, and further improve the yield of the manufacturing process of the pixel array structure 200 .

Specifically, the lower electrode 216 of the storage capacitor includes a first line segment 216A and a second line segment 216B. The first line segment 216A and the second line segment 216B are composed of different film layers. The first line segment 216A is disposed adjacent to the data line 204 , and the second line segment 216B is disposed adjacent to the scan line 202 . In addition, the first line segment 216A and its adjacent data line 204 have different film layers, and the second line segment 216B and its adjacent scan line 202 have different film layers. In this embodiment, the shape of the lower electrode 216 of the storage capacitor is, for example, U-shaped, and the lower electrode 216 of the storage capacitor includes two first line segments 216A, and the two ends of the second line segment 216B are respectively connected to the two first line segments. Segments 216A overlap. In addition, the pixel structure 210 further includes a contact window 218 located at the intersection of the first line segment 216A and the second line segment 216B, and the first line segment 216A and the second line segment 216B are electrically connected through the contact window 218 .

Certainly, the lower electrode 216 of the storage capacitor of the present invention is not limited to the ㄇ-shaped shape. In other embodiments, for example, the lower electrode 216 of the storage capacitor does not intersect or overlap the active element 212 and forms a nearly C-shaped pattern, surrounding most of the peripheral area of the pixel region P. For example, the lower electrode 216 of the storage capacitor is disposed around the pixel area P, and has an opening corresponding to the active element 212 .

FIG. 3 is a schematic top view of the pixel structure 210 in FIG. 2 . Please refer to FIG. 2 and FIG. 3 , in the pixel structure 210 , the second line segment 216B and the scan line 202 are made of different film layers. From the top view, even if the distance d between the second line segment 216B and the scan line 202 is shortened, the problem of short circuit between the second line segment 216B and the scan line 202 is not easy to occur. Therefore, compared with the known pixel structure 110 , the second line segment 216B of the storage capacitor lower electrode 216 can be closer to the scan line 202 , thus helping to increase the display aperture ratio of the pixel structure 210 . In addition, the first line segment 216A and the data line 206 are also of different film layers, so it is also helpful to increase the display aperture ratio of the pixel structure 210 .

According to the actual test results, it is found that compared with the known pixel structure 110, the pixel structure 210 of this embodiment has a higher display aperture ratio (depending on the pixel design, generally greater than 1%), so under the same light source conditions, the application The liquid crystal display panel of the pixel structure 210 also has a high light transmittance. Therefore, the design of the pixel structure 210 can increase the light utilization rate of the backlight, thereby helping to reduce the energy consumption of the backlight. In other words, the liquid crystal display using the pixel structure 210 can achieve sufficient display brightness without a high-brightness backlight module or an expensive brightness-enhancing film, so as to further save costs.

4A to 4D are cross-sectional views of the fabrication method of the pixel array structure in FIG. 2 along the section line AA'. Please refer to FIG. 2 and FIG. 4A at the same time, the first metal layer 410 is formed on the substrate 400 . The first metal layer 410 includes a gate 212A, a scan line 202 and a first line segment 216A. The gate 212A is connected to the scan line 202 , and the first line segment 216A is away from the scan line 202 . Actually, the first line segment 216A does not touch or overlap with the scan line 202 , and the extension direction of the first line segment 216A intersects the extension direction of the scan line 202 . Corresponding to each pixel region P, the first line segment 216A is connected to the first line segment 216A of the adjacent pixel region P, for example.

Next, referring to FIG. 2 and FIG. 4B , a gate insulating layer 420 and a patterned semiconductor layer 430 are sequentially formed on the substrate 400 , and the gate insulating layer 420 covers the gate 212A. In addition, a contact window 218 is formed on the gate insulating layer 420 . The patterned semiconductor layer 430 is located above the gate 212A, and the contact window 218 exposes the end of the first line segment 216A.

Then, referring to FIG. 2 and FIG. 4C , a second metal layer 440 is formed on the substrate 400 . The second metal layer 440 includes a second line segment 216B adjacent to the scan line 202 , a data line 204 adjacent to the first line segment 216A, a source 212B connected to the data line 204 , and a drain 212C. The source 212B and the drain 212C are located on the patterned semiconductor layer 430 above the gate 212A. The second line segment 216B is electrically connected to the first line segment 216A through the contact window 218 to form the storage capacitor bottom electrode 216 , wherein the storage capacitor bottom electrode 216 is located around the pixel region P.

Because, the adjacent scan line 202 and the second line segment 216B are respectively the first metal layer 410 and the second metal layer 440 , wherein at least the gate insulating layer 420 is disposed between the first metal layer 410 and the second metal layer 440 . Therefore, the scan line 202 and the adjacent second line segment 216B are less likely to be short-circuited, so that the pixel array structure 200 has a higher manufacturing process yield. The distance between the scan line 202 and the adjacent second line segment 216B can be shortened compared with the design of the known pixel structure 110 , so as to increase the display aperture ratio of the pixel array structure 200 . In addition, the metal layer of the data line 204 and the adjacent first line segment 216A is also different, so it also has the above advantages.

Furthermore, referring to FIG. 2 and FIG. 4D at the same time, a protective layer 450 is formed on the substrate 400 to cover the second metal layer 440 , and a plurality of pixel electrodes 214 are formed on the protective layer 450 . The pixel electrode 214 is electrically connected to the drain electrode 212C, and the edge of the pixel electrode 214 substantially partially overlaps with the storage capacitor bottom electrode 216 to form a storage capacitor. In this way, the fabrication of the pixel array structure 200 is completed.

In this embodiment, the contact window 218 and the patterned semiconductor layer 430 are formed, for example, by using the semi-transmissive mask shown in FIG. 5 to perform an etching process. Please refer to FIG. 4D and FIG. 5 at the same time, the semi-transparent mask 500 has a plurality of light-transmitting regions T with different light transmittances. Corresponding to the single pixel region P, the transparent region T1 corresponds to the top of the contact window 218 , the transparent region T2 corresponds to the top of the patterned semiconductor layer 430 , and the transparent region T3 is located in other regions. In detail, the method of forming the patterned semiconductor layer 430 and the contact window 218 is shown in FIGS. 6A-6E .

First, referring to FIG. 6A , a gate insulating layer 420 , a semiconductor layer 432 and a photoresist material layer (not shown) are sequentially formed on a substrate 400 . At the same time, a photoresist material layer (not shown) is patterned using the semi-transmissive mask 500 to form a patterned photoresist layer 610 . The gate insulating layer 420 and the semiconductor layer 432 cover the first metal layer 410 . In this embodiment, the semiconductor layer 432 includes an undoped amorphous silicon layer 434 and a doped amorphous silicon layer 436 . The doped amorphous silicon layer 436 is formed by, for example, performing a doping process to dope impurities into the amorphous silicon material.

In addition, the semi-transparent mask 500 has light-transmitting regions T with different transmittances, so that the photoresist material layer (not shown) corresponding to different regions receives light with different energies. Therefore, the patterned photoresist layer 610 has different thicknesses in different regions. In this embodiment, corresponding to a single pixel region P, the patterned photoresist layer 610 has at least one opening 612 , a first region 614 , and a second region 616 outside the first region 614 and the opening 612 . The position of the opening 612 corresponds to the end of the first line segment 216A, and the first region 614 corresponds to the top of the gate 212A. In addition, the patterned photoresist layer 610 is thicker in the first region 614 than in the second region 616 .

Then, referring to FIG. 6B , the semiconductor layer 432 and the gate insulating layer 420 exposed by the opening 612 are removed to form the contact window 218 . In this step, for example, an etching process is performed to remove the semiconductor layer 432 and the gate insulating layer 420 exposed by the opening 612 . At this time, the patterned photoresist layer 610 in the first region 614 and the second region 616 can protect the semiconductor layer 432 and the gate insulating layer 420 thereunder from being etched.

Next, referring to FIG. 6C , part of the patterned photoresist layer 610 in the second region 616 is removed. This step is, for example, an ashing process. Because, the partially patterned photoresist layer 610 in the second region 616 has a thinner thickness, while the partially patterned photoresist layer 610 in the first region 614 has a thicker thickness. Therefore, when the part of the patterned photoresist layer 610 in the second region 616 is completely removed in the ashing process, the part of the part of the patterned photoresist layer 610 in the first region 614 is still not removed. In addition, it can be used as a mask in the subsequent process.

Subsequently, please refer to FIG. 6D and FIG. 6E , using part of the patterned photoresist layer 610 in the first region 614 as a mask, part of the semiconductor layer 432 is removed. Afterwards, the patterned photoresist layer 510 in the first region 214 is removed to complete the patterned half body layer 430 . The semiconductor layer 432 in the second region 616 is removed in this step, leaving only the patterned semiconductor layer 430 above the gate 212A. In this embodiment, the etching manufacturing processes with different etching depths can be completed without using different photomasks, thus helping to save the cost of purchasing and making photomasks. Of course, under different manufacturing process designs, the present invention does not exclude the use of different photomasks to form the contact window 218 and the patterned semiconductor layer 430 in different etching manufacturing processes.

To sum up, in the pixel array structure and the manufacturing method thereof of the present invention, each line segment of the lower electrode of the storage capacitor and the adjacent metal lines are in different metal layers. Therefore, a short circuit between the lower electrode of the storage capacitor and adjacent metal lines, such as scan lines or data lines, is unlikely to occur. That is to say, the pixel array structure and its manufacturing method of the present invention have a high process yield. In addition, the short circuit between the lower electrode of the storage capacitor and the adjacent metal circuit is less likely to occur, so the distance between the lower electrode of the storage capacitor and the adjacent scanning line or data line can be shortened, which helps to improve the display aperture ratio of the pixel structure. In short, the present invention provides a pixel array structure with high manufacturing process yield and high display aperture ratio and its manufacturing method.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be The scope defined by the appended claims shall prevail.

Claims (7)

1, a kind of picture element array structure comprises:

The multi-strip scanning line;

Many data wires, described multi-strip scanning line and described many data wires cross a plurality of pixel regions;

A plurality of dot structures are electrically connected pairing described multi-strip scanning line and described many data wires respectively, and each described dot structure is positioned at pairing described a plurality of pixel regions, and each described dot structure comprises:

Active element;

Pixel electrode is electrically connected this active element; And

Storage capacitors, has the storage capacitors bottom electrode, be disposed at this pixel region periphery and overlapping with pixel electrode part, this storage capacitors bottom electrode comprises at least one first line segment of contiguous described many data wires and at least one second line segment of contiguous described multi-strip scanning line, wherein this first line segment and this second line segment are different retes for this second line segment of different retes with contiguous wherein this scan line for different retes and this first line segment and contiguous wherein this data wire, wherein this first line segment partly overlaps with this second line segment and is electrically connected, wherein this first line segment and described multi-strip scanning line are same rete, and this second line segment and described many data wires are same rete.

2, picture element array structure as claimed in claim 1, wherein the profile of this storage capacitors bottom electrode is ㄇ type or U type, and this storage capacitors bottom electrode comprises two first line segments, and the two ends of this second line segment overlap with described two first line segments respectively and are electrically connected.

3, a kind of manufacture method of picture element array structure comprises:

Form the first metal layer on substrate, this first metal layer comprises a plurality of grids, multi-strip scanning line and a plurality of first line segment, and described a plurality of grids are connected with described multi-strip scanning line, and described a plurality of first line segment separates with described multi-strip scanning line;

Form gate insulation layer and semiconductor layer on this substrate successively, this gate insulation layer covers this first metal layer;

Remove this gate insulation layer of part and this semiconductor layer of part to form patterned semiconductor layer and a plurality of contact hole, this patterned semiconductor layer is positioned at described a plurality of grids top and described a plurality of contact hole exposes the end of described a plurality of first line segments; And

On this substrate, form second metal level, this second metal level comprises a plurality of second line segments of contiguous described multi-strip scanning line, many data wires of contiguous described a plurality of first line segments, connect a plurality of source electrodes and a plurality of drain electrode of described many data wires, described many data wires and described multi-strip scanning line intersect and surround a plurality of pixel regions, described a plurality of source electrode and described a plurality of drain electrode are positioned at described a plurality of grids top, and described a plurality of second line segment is electrically connected described a plurality of first line segment to form a plurality of storage capacitors bottom electrodes by described a plurality of contact holes, and wherein said a plurality of storage capacitors bottom electrodes are positioned at described a plurality of pixel region periphery.

4, manufacture method as claimed in claim 3 also comprises:

On this substrate, form protective layer to cover this second metal level; And

Form a plurality of pixel electrodes on this protective layer, described a plurality of pixel electrodes are electrically connected described a plurality of drain electrode and described a plurality of pixel electrode and described a plurality of storage capacitors bottom electrode and overlap to constitute storage capacitors.

5, manufacture method as claimed in claim 3, the method that wherein forms this patterned semiconductor layer and described a plurality of contact holes comprises:

On this semiconductor layer, form patterning photoresist layer, in each described pixel region, this patterning photoresist layer has the second area outside at least one opening, first area and this first area and this opening, this opening is positioned at this first line segment top, this first area is positioned at this grid top, and this patterning photoresist layer at the thickness of this first area greater than thickness at this second area;

Remove this semiconductor layer and this gate insulation layer that this opening comes out, and form this contact hole;

Remove this patterning photoresist layer of this second area; And

Remove this semiconductor layer in this second area;

Remove the patterning photoresist layer of first area, and form patterned semiconductor layer.

6, manufacture method as claimed in claim 5, wherein the formation method of this patterning photoresist layer is included in and forms the photo anti-corrosion agent material layer on this substrate and use semi-transparent mask with this photo anti-corrosion agent material layer of patterning.

7, manufacture method as claimed in claim 6, the wherein transmission region of this semi-transparent mask with a plurality of different light transmittances.

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