CN119069345A - Semiconductor gate structure preparation method and semiconductor structure - Google Patents
Semiconductor gate structure preparation method and semiconductor structure Download PDFInfo
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- CN119069345A CN119069345A CN202411555633.9A CN202411555633A CN119069345A CN 119069345 A CN119069345 A CN 119069345A CN 202411555633 A CN202411555633 A CN 202411555633A CN 119069345 A CN119069345 A CN 119069345A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses a preparation method of a semiconductor grid structure and the semiconductor structure. The preparation method of the semiconductor gate structure comprises the steps of providing a substrate, forming gate polysilicon on the substrate, performing sinking treatment on well regions on two sides of the gate polysilicon in the forming process of the gate polysilicon, forming side wall structures on two sides of the gate polysilicon along the channel length direction of a semiconductor, wherein the side wall structures comprise a sacrificial layer and side wall layers formed on the outer sides of the sacrificial layer, removing the gate polysilicon and the sacrificial layer to form a first groove, performing sinking treatment on contact parts of the two sides of the gate polysilicon and a shallow groove isolation region in the removing process of the gate polysilicon along the channel width direction of the semiconductor to form a second groove on the shallow groove isolation region, and performing gate filling treatment on the first groove and the second groove. By the scheme of the application, the grid structure of the semiconductor device is changed, so that the effective improvement of the short channel effect of the device is realized.
Description
Technical Field
The present application relates generally to the field of semiconductor manufacturing processes. More particularly, the present application relates to a method for fabricating a semiconductor gate structure and a semiconductor structure.
Background
In the prior art, the size of a semiconductor device such as a metal oxide semiconductor field effect transistor (MOS) is generally reduced to improve the working performance of the semiconductor device and save the cost. However, as the size of semiconductor devices such as MOS is reduced, the channel length of the semiconductor devices is reduced to a certain extent, the specific gravity of the depletion region of the source and drain junction in the entire channel is increased, and the amount of charge required for forming an inversion layer on the silicon surface under the gate is reduced, and thus the threshold voltage is reduced. Meanwhile, the threshold voltage is increased by the charges of the lateral stretching part of the depletion region in the substrate along the width of the channel, when the width of the depletion region of the source electrode and the drain electrode is close to the channel length of the device, the threshold voltage is obviously reduced, and serious short channel effect can occur in semiconductor devices such as MOS.
In view of the foregoing, there is a need to provide a solution for improving the short channel effect of semiconductor devices in order to improve the performance of small-sized semiconductor devices.
Disclosure of Invention
In order to solve at least one or more of the technical problems mentioned above, the present application proposes a solution capable of improving a short channel effect of a semiconductor device in various aspects.
In a first aspect, the application provides a method for manufacturing a semiconductor gate structure, which comprises the steps of providing a substrate, forming gate polysilicon on the substrate, sinking well regions on two sides of the gate polysilicon in the forming process of the gate polysilicon, forming side wall structures on two sides of the gate polysilicon along the channel length direction of a semiconductor, wherein the side wall structures comprise sacrificial layers formed on two sides of the gate polysilicon and side wall layers formed on the outer sides of the sacrificial layers, removing the gate polysilicon and the sacrificial layers to form a first groove, forming shallow groove isolation regions in the well regions of the substrate, sinking contact portions of the two sides of the gate polysilicon and the shallow groove isolation regions in the channel width direction of the semiconductor in the removing process of the gate polysilicon, forming a second groove on the shallow groove isolation regions, and filling the first groove and the second groove.
In some embodiments, the sinking of the well regions on two sides of the gate polysilicon comprises performing an etching process on the well regions on two sides of the gate polysilicon so that the well regions on two sides of the gate polysilicon are sunk by a first height.
In some embodiments, forming the side wall structures on two sides of the grid polycrystalline silicon comprises forming the sacrificial layer with a preset thickness on two sides of the grid polycrystalline silicon, and forming the side wall layers on the outer sides of the sacrificial layer, wherein the sacrificial layer and the side wall layers are made of different materials.
In some embodiments, wherein the sacrificial layer is made of silicon oxide.
In some embodiments, removing the gate polysilicon and the sacrificial layer includes forming an interlayer dielectric on the well region of the substrate after forming the sidewall structure such that the interlayer dielectric covers the gate polysilicon and the sidewall structure, removing the interlayer dielectric over the gate polysilicon and the sacrificial layer in the sidewall structure to expose the gate polysilicon and the sacrificial layer, and removing the gate polysilicon and the sacrificial layer to form the first recess.
In some embodiments, removing the interlayer dielectric above the gate polysilicon and the sacrificial layer in the sidewall structure includes removing the interlayer dielectric above the gate polysilicon and the sacrificial layer in the sidewall structure using a chemical mechanical planarization technique.
In some embodiments, the sinking of the contact portions of the two sides of the grid polysilicon and the shallow trench isolation region comprises the step of carrying out etching treatment on the contact portions of the two sides of the grid polysilicon and the shallow trench isolation region so that the shallow trench isolation region is sunk to a second height to form the second groove.
In some embodiments, performing gate filling processing on the first groove and the second groove comprises performing high-K dielectric layer filling processing on the first groove and the second groove, and continuing performing metal gate filling processing on the first groove and the second groove after the high-K dielectric layer filling is completed.
In a second aspect, the application provides a semiconductor structure, which comprises a substrate, a grid electrode, a source electrode and a drain electrode formed on the substrate, wherein the grid electrode is manufactured by adopting the manufacturing method provided by the first aspect, the channel length of the semiconductor structure is related to the length of grid electrode polycrystalline silicon, the sinking height of well regions at two sides of the grid electrode polycrystalline silicon and the thickness of the sacrificial layer, and the channel width of the semiconductor structure is related to the width of the grid electrode polycrystalline silicon and the height of the second groove.
In some embodiments, the channel length L=l+2h1+2h2 of the semiconductor structure, wherein L represents the length of the gate polysilicon, h1 represents the sinking height of the well regions at two sides of the gate polysilicon, h2 represents the thickness of the sacrificial layer, and the channel width W=w+2h3 of the semiconductor structure, wherein W represents the width of the gate polysilicon, and h3 represents the height of the second groove.
The method for manufacturing the semiconductor gate structure and the semiconductor structure have the unexpected beneficial technical effects that through the method for manufacturing the semiconductor gate structure and the semiconductor structure, in the embodiment of the application, the well regions on the two sides of the gate polysilicon are sunk in the manufacturing process of the semiconductor gate structure, and the sacrificial layers are formed on the two sides of the gate polysilicon, so that the gate length is prolonged through removing the gate polysilicon and the sacrificial layers. And simultaneously, in the process of removing the grid polysilicon, sinking treatment is carried out on contact parts of the two sides of the grid polysilicon and the shallow slot isolation region so as to widen the width of the grid, thereby completing the modification of the grid structure of the semiconductor device. Therefore, the scheme of the application can effectively increase the length and the width of the channel of the semiconductor device by changing the grid structure of the semiconductor device on the premise of not adding a mask (mask), not increasing the area of the device and the like, thereby effectively improving the short channel effect of the device and further improving the performance of the small-size semiconductor device.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, embodiments of the application are illustrated by way of example and not by way of limitation, and like reference numerals refer to similar or corresponding parts and in which:
FIGS. 1 a-1 c are schematic diagrams illustrating the structure of a semiconductor structure in different directions according to an embodiment of the present application;
fig. 2 illustrates a schematic flow chart of a method of fabricating a semiconductor gate structure in accordance with some embodiments of the present application;
FIG. 3 is a schematic flow chart of a method for fabricating a semiconductor gate structure according to other embodiments of the application, and
Fig. 4a to fig. 4f are schematic diagrams illustrating a semiconductor cross-sectional structure in a method for manufacturing a semiconductor gate structure according to some embodiments of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that the terms "comprises" and "comprising," when used in this specification and in the claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification and claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the present specification and claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Specific embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1a, 1b and 1c show schematic structural views of a semiconductor structure in different directions according to an embodiment of the present application, respectively. Note that fig. 1a shows a schematic top structure of a semiconductor structure, where an X direction in fig. 1a indicates a channel length direction of the semiconductor structure, and a Y direction indicates a channel width direction of the semiconductor structure. Fig. 1b shows a schematic cross-sectional view of the semiconductor structure in the X-direction (i.e. the channel length direction of the semiconductor structure) and fig. 1c shows a schematic cross-sectional view of the semiconductor structure in the Y-direction (i.e. the channel width direction of the semiconductor structure).
The semiconductor structure in the scheme of the application can comprise a metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT for short MOS), a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor for short CMOS) and the like.
As shown in fig. 1b and 1c, the semiconductor structure 100 comprises a substrate 101. The substrate 101 may be a silicon substrate, a silicon germanium substrate, or other semiconductor material substrate known to those skilled in the art. For example, a silicon substrate is generally used for a MOS transistor, a CMOS transistor, and the like.
A gate, a source, and a drain may be formed on the substrate 101. The scheme of the application mainly relates to the change of a grid structure, the embodiment focuses on the description and the display of a grid part, a source electrode and a drain electrode can be prepared by adopting the known technology, and the scheme of the application does not excessively describe the source electrode and the drain electrode.
In this embodiment, the gate of the semiconductor structure is formed mainly by the following process:
First, gate polysilicon is formed on a substrate 101, and well regions 102 on both sides of the gate polysilicon are subjected to a sinker process during the formation of the gate polysilicon. Next, a sidewall layer 104 may be formed on the sacrificial layer on both sides of the gate polysilicon and on the outside of the sacrificial layer. In a subsequent process, the gate polysilicon and the sacrificial layer may be removed to form a first recess. The well region 102 of the substrate 101 is further formed with a shallow trench isolation region 105, and in the foregoing removal process of the gate polysilicon, a portion of the contact between two sides of the gate polysilicon and the shallow trench isolation region 105 may be subjected to a sinking process to form a second groove on the shallow trench isolation region 105. Then, gate filling is performed on the first recess and the second recess to complete the preparation of the gate 103. The specific process of preparing the gate electrode 103 may be described later.
The structure of the gate 103 of the semiconductor of the present application is improved over that of a conventional gate. Specifically, the length of the gate 103 in the present application is related to the length of the gate polysilicon, the sinking height of the well regions at both sides of the gate polysilicon, and the thickness of the sacrificial layer, and the width of the gate 103 is related to the width of the gate polysilicon and the height of the second recess. The length of the grid electrode prepared by the traditional process is only related to the length of the grid electrode polysilicon, and the width of the grid electrode is only related to the width of the grid electrode polysilicon.
The application has the unexpected beneficial technical effects that compared with the grid prepared by the traditional technology, the length of the grid of the semiconductor in the scheme is prolonged, the width of the grid of the semiconductor is widened, and the length and the width of a channel of the semiconductor device are effectively increased by changing the grid structure of the semiconductor device, so that the effective improvement of the short channel effect of the device is realized, and the performance of the small-size semiconductor device is improved.
Fig. 2 illustrates a schematic flow chart of a method 200 of fabricating a semiconductor gate structure according to some embodiments of the application. It should be noted that fig. 2 is understood to be an exemplary process for preparing the gate electrode in the semiconductor structure of fig. 1b and 1 c. The relevant description in fig. 1b and 1c applies equally to the following.
As shown in fig. 2, at step S201, a substrate may be provided and gate polysilicon is formed on the substrate, wherein well regions on both sides of the gate polysilicon are subjected to a sinker process during the formation of the gate polysilicon. As indicated above, the substrate may comprise a silicon substrate, a silicon germanium substrate, or other semiconductor material substrate known to those skilled in the art, and may be specifically configured and adapted to the desired performance requirements of the semiconductor to be fabricated.
In some embodiments, a well region may be formed on a substrate first. The well region may include an N-well, a P-well, or a double well. For example, a sacrificial oxide layer may be formed on a substrate by a thermal oxidation process or the like, then a photoresist is coated over the P/N well region and exposed to light by a photolithography process, developed, and N/P impurities are implanted by an ion implantation process, and unnecessary photoresist is ashed to remove. And then removing the sacrificial oxide layer, and annealing and activating the P/N well region to form the P/N well. If the semiconductor structure is a CMOS transistor, a P-well and an N-well are formed on the substrate to form a double well. The description of the well formation process is merely illustrative, and the embodiment of the present application is not limited thereto, and other known processes may be used to complete the well preparation.
After the well region is prepared, a gate oxide layer consisting of a silicon oxynitride layer or a silicon dioxide layer may be formed on the well region, and a polysilicon gate may be deposited on the gate oxide layer. Then, the pattern on the gate mask is transferred to the substrate by using a photolithography technique to form a photoresist pattern of the gate, and the photoresist is remained on the gate region of the device. Next, the polysilicon not covered by the photoresist may be removed using a dry etching technique or the like to form gate polysilicon. Typically, when a gate etch is performed, the polysilicon etch is indicated as being complete when the gate oxide is etched. In this embodiment, the well regions on both sides of the gate polysilicon need to be subjected to a sinking process during the formation of the gate polysilicon. Specifically, the well regions on both sides of the gate polysilicon may be subjected to an etching process so that the well regions on both sides of the gate polysilicon are sunk by a first height. The first height may be preset, and may specifically be designed according to the performance requirement of the prepared semiconductor device.
At step S202, sidewall structures may be formed on both sides of the gate polysilicon along the channel length direction of the semiconductor. The side wall structure can comprise a sacrificial layer formed on two sides of the grid polysilicon and a side wall layer formed on the outer side of the sacrificial layer. In some embodiments, a sacrificial layer of a predetermined thickness may be formed on both sides of the gate polysilicon. Then, a sidewall layer is formed on the outer side of the sacrificial layer. For example, a plasma chemical vapor deposition method and the like can be adopted to sequentially form sacrificial layers and side wall layers with different materials on two sides of the grid polysilicon. It should be noted that, the thickness of the sacrificial layer and the thickness of the side wall layer are not limited by the scheme of the application, and the design can be specifically performed according to the performance requirements of the prepared semiconductor device.
The sacrificial layer needs to be removed in the subsequent process, so any material can be used to form the sacrificial layer, so long as the material is different from the material of the side wall layer. Preferably, the sacrificial layer may be made of silicon oxide or silicon, etc., to increase the adhesion between the sacrificial layer and the gate polysilicon.
At step S203, the foregoing gate polysilicon and sacrificial layer may be removed to form a first recess and a second recess on the shallow trench isolation region.
In this embodiment, after the sidewall structure is formed, an interlayer dielectric (Inter-LEVEL DIELECTRIC, abbreviated as ILD) may be formed on the well region of the substrate, so that the interlayer dielectric covers the gate polysilicon and the sidewall structure. The ILD process refers to a dielectric material formed between the transistor and the first metal layer to form an electrical isolation. The ILD dielectric layer can effectively reduce parasitic capacitance between the metal and the substrate and improve parasitic field effect transistors formed by crossing different areas by the metal. In some embodiments, silicon oxide may be employed as the dielectric material of the ILD.
Then, the interlayer dielectric above the sacrificial layer in the gate polysilicon and sidewall structure may be removed to expose the gate polysilicon and sacrificial layer. In some embodiments, a Chemical Mechanical Planarization (CMP) technique may be used to remove the interlayer dielectric over the sacrificial layer in the gate polysilicon and sidewall structures. For example, chemical mechanical planarization methods such as an anti-etching method, a BPSG reflow method, an SOG spin-on-glass method and the like can be used to polish the interlayer dielectric above the gate polysilicon and the sacrificial layer, so as to remove the interlayer dielectric at the corresponding position, and expose the gate polysilicon and the sacrificial layer relative to other areas.
Then, the gate polysilicon and the sacrificial layer are removed to form a first recess. In some embodiments, the gate polysilicon and the sacrificial layer may be processed, in particular, by an etching process, to complete the removal of the gate polysilicon and the sacrificial layer.
In practical applications, a gate oxide layer is further formed between the gate polysilicon and the substrate, and the formation of the first recess may specifically involve removal of the gate polysilicon, removal of the gate oxide layer, and removal of the sacrificial layer. If the material of the sacrificial layer and the material of the gate polysilicon are the same (e.g., silicon is used), the sacrificial layer can be removed simultaneously with the removal of the gate polysilicon. If the material of the sacrificial layer and the gate oxide layer are the same (for example, silicon oxide or the like is used), the sacrificial layer can be removed simultaneously with the removal of the gate oxide layer. If the materials of the sacrificial layer and the gate polysilicon are different from each other, the gate polysilicon can be removed first, then the gate oxide layer can be removed, and then the sacrificial layer can be removed. It should be noted that the description herein of the removal process of the gate polysilicon and the sacrificial layer is only an exemplary illustration, and the specific removal manner may be adjusted according to the specific material of the sacrificial layer.
In some embodiments, shallow trench isolation regions are also formed in the well region of the substrate. Shallow trench isolation (Shallow Trench Isolation, STI) technology has become popular for fabricating isolation structures between devices. In some embodiments, a silicon nitride layer may be deposited on the well region of the semiconductor substrate, and then patterned to form a hard mask. The substrate is then etched to form abrupt trenches between adjacent devices. Finally, oxide (such as silicon oxide) is filled in the trench to form shallow trench isolation region. In other embodiments, a liner oxide layer may be formed on the well region of the semiconductor substrate by oxidation, then a silicon nitride layer may be deposited, a trench region may be defined by patterning a photoresist, etching to form a trench, and finally filling the trench to form a shallow trench isolation region.
In this embodiment, in the removal process of the gate polysilicon, further sinking treatment is required to be performed on the contact portions between the two sides of the gate polysilicon and the shallow trench isolation region along the channel width direction of the semiconductor, so as to form the second recess on the shallow trench isolation region. In some embodiments, the contact portions between the two sides of the gate polysilicon and the shallow trench isolation region may be subjected to etching treatment, so that the shallow trench isolation region is sunk to a second height to form a second groove. The second height may be preset, and may be specifically designed according to the performance requirement of the prepared semiconductor device.
After forming the first and second grooves, at step S204, a gate filling process may be performed on the first and second grooves. In some embodiments, the first and second grooves may be filled with a gate dielectric layer, and then the filling of the polysilicon or metal gate may be continued. For example, silicon dioxide or SiON may be filled in the first and second grooves as a gate dielectric layer, and then polysilicon or a metal gate may be further filled on the gate dielectric layer. For another example, silicon oxynitride may be filled in the first groove and the second groove to serve as a gate dielectric layer, and then the metal gate is continuously filled on the gate dielectric layer. Also for example, a High-K material (High-K MATERIAL) may be substituted for silicon oxynitride as the gate dielectric layer, and then the metal gate may continue to be filled over the gate dielectric layer. Alternatively, in other embodiments, a SiON film may be deposited in the first recess and the second recess to improve the interface state between the high-K dielectric material and the substrate silicon by the SiON film, and then the high-K dielectric material (e.g., hfO 2) may be deposited by an atomic layer deposition technique. Then, a metal gate may be deposited by an atomic layer deposition technique, and a gate filling process may be completed by depositing a low-resistance metal filling gate trench or the like by an atomic layer deposition technique.
In this embodiment, preferably, the first groove and the second groove are filled with a high-K dielectric layer, that is, the first groove and the second groove are filled with a gate dielectric layer of a high-K material. In some embodiments, the high-K material includes, but is not limited to, hafnium oxide (Hf 02), hafnium silicon oxide (HfSi 0), hafnium silicon oxynitride (HfSi 0N), hafnium tantalum oxide (HfTa 0), hafnium titanium oxide (HM 0), hafnium zirconium oxide (HfZr), lanthanum oxide (La 0), zirconium oxide (Zr 0), titanium oxide (Ti 0), tantalum oxide (Ta 205), yttrium oxide (Y203), strontium titanium oxide (SrTi 03, STO), and the like. And after the high-K dielectric layer is filled, continuing to fill the metal gate into the first groove and the second groove. In some embodiments, the metal gate may employ, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, taC, taSiN, taCN, tiA, tiAIN, or other suitable materials. Therefore, compared with the situation that other materials are adopted as the gate dielectric layer, the gate dielectric layer with larger physical thickness can be obtained under the condition of the same equivalent gate oxide layer thickness, and therefore the gate leakage current is improved.
Thus, the preparation of the gate is completed based on the steps S201 to S204. Further, the preparation of the source electrode and the drain electrode can be performed on the well region on the substrate, and finally the preparation of the whole semiconductor structure is completed.
The preparation process of the gate structure shown in the implementation can effectively improve the gate structure of the semiconductor on the basis of not changing the area of the device, thereby improving the performance of the small-size semiconductor device.
Fig. 3 illustrates a schematic flow chart of a method 300 of fabricating a semiconductor gate structure according to further embodiments of the present application. It should be noted that fig. 3 may be understood as a specific implementation of the preparation method shown in fig. 2. The preparation process in fig. 3 can be understood as being an improvement over the prior art (e.g., post HK process), where "Σ" represents the prior art and "ζ" represents the improvement. The process of post HK (HK Last) in the prior art is that an IL layer is used for depositing virtual SiO2 as a virtual medium layer, then virtual Si is directly deposited as a virtual gate, then the processes of source-drain embedded GeSi strain, source-drain doping, stress Memory (SMT), contact etching barrier layer strain (CESL), side walls and the like are carried out, then the virtual Si is exposed by a CMP process after the ILD layer is deposited, after the virtual Si and the virtual SiO2 are etched, an IL layer and an HK layer are deposited, and finally a metal gate is deposited.
As shown in fig. 3, in step S301, a gate polysilicon preparation may be performed using, for example, a Poly mask process. For example, a well region may be formed on a substrate, a gate oxide layer formed of a silicon oxynitride layer or a silicon dioxide layer may be formed on the well region after the well region is completed, and a polysilicon gate may be deposited on the gate oxide layer. Specifically, the pattern on the gate mask can be transferred to the substrate by using a photolithography technique to form a photoresist pattern for the gate, and the photoresist remains on the gate region of the device. Then, the polysilicon not covered with the photoresist is removed by a dry etching technique or the like to form gate polysilicon. Wherein the length of the grid polysilicon is l.
In step S302, during the etching process of the gate polysilicon, an appropriate amount of etching process may be added to the well regions on both sides of the gate polysilicon. For example, the well regions on both sides of the gate polysilicon may be subjected to an etching process such that the well regions on both sides of the gate polysilicon are sunk by the first height (h 1).
Referring to fig. 4a, the semiconductor structure comprises a substrate 401, a well region 402. A gate polysilicon 403 is formed on the well region 402, and during the etching process of the gate polysilicon 403, the well regions on both sides of the gate polysilicon 403 may be subjected to etching treatment, so that the well regions on both sides of the gate polysilicon 403 are sunk by h1 (h 1> 0) height.
Returning to fig. 3, at step S303, a polysilicon removal process may be performed. The removal process (Strip) is a process for removing photoresist covered by the pattern after the etching process forms a corresponding pattern on the substrate, and the process can be implemented along with the existing process, which is not described herein.
At step S304, a sacrificial layer may be formed on both sides of the aforementioned gate polysilicon. For example, a sacrificial layer of silicon oxide, silicon or other materials may be formed on both sides of the gate polysilicon by plasma chemical vapor deposition or the like, and the thickness of the sacrificial layer is h2 (h 2> 0).
At step S305, a sidewall layer may be formed on the outer side of the sacrificial layer side. For example, a sidewall layer may be formed on the outer side of the sacrificial layer by a plasma chemical vapor deposition method or the like, and the sidewall layer is made of a material different from that of the sacrificial layer.
Referring to fig. 4b, the semiconductor structure includes a substrate 401, a well region 402, and gate polysilicon 403 formed on the well region 402. A sacrificial layer with a thickness of h2 and a sidewall layer 405 are formed on two sides of the gate polysilicon 403.
Returning to fig. 3, at step S306, a middle-stage process may be performed. The general middle process may be understood as a process of connecting the front-end device and the rear-end first metal layer, and the middle process in this embodiment may be the same or similar to the prior art, which is not described herein.
At step S307, a process of interlayer dielectric ILD is performed. For example, an interlayer dielectric ILD may be formed on the well region of the substrate such that the interlayer dielectric ILD covers the gate polysilicon and the sidewall structure.
At step S308, a chemical mechanical planarization process may be performed on the interlayer dielectric ILD to expose the gate polysilicon and the sacrificial layer.
At step S309, a removal process is performed on the gate polysilicon and the sacrificial layer. For example, the gate polysilicon and the sacrificial layer may be removed by etching or the like to form the first recess.
In addition, a shallow trench isolation region is formed in the well region of the substrate, and in the removing process of the gate polysilicon, the contact portions between the two sides of the gate polysilicon and the shallow trench isolation region need to be further subjected to sinking treatment so as to form a second groove on the shallow trench isolation region. In some embodiments, the contact portions between the two sides of the gate polysilicon and the shallow trench isolation region may be subjected to etching treatment, so that the shallow trench isolation region is sunk to a second height to form a second groove.
Referring to fig. 4c, the semiconductor structure includes a substrate 401 and a well region 402. A gate polysilicon 403 (not shown in fig. 4 c) is further formed on the well region 402, a sacrificial layer 404 (not shown in fig. 4 c) is formed on both sides of the gate polysilicon 403, and a sidewall layer 405 is formed on the outer side of the sacrificial layer 404. After the gate polysilicon 403 and the sacrificial layer 404 are removed, a first recess a may be formed.
Referring to fig. 4d, the semiconductor structure further includes a shallow trench isolation region 406, and the shallow trench isolation region 406 is filled with a material such as silicon oxide. An interlayer dielectric 407 may cover the well region 402, the gate polysilicon 403, the sacrificial layer 404, and the sidewall layer, and the gate polysilicon 403 and the sacrificial layer 404 are exposed by removing the interlayer dielectric 407 over the gate polysilicon 403 and the sacrificial layer 404, and removing the gate polysilicon 403 and the sacrificial layer 404 to form the first recess. During the removal process of the gate polysilicon 403, a further sinking process is required for the contact portion between the two sides of the gate polysilicon 403 and the shallow trench isolation region 406. That is, the silicon oxide at the corresponding position in the shallow trench isolation region 406 is subjected to an etching process to form the second groove B on the shallow trench isolation region 406. The shallow trench isolation 406 is sunk by a second height h3 (h 3> 0), i.e. the height or depth of the second recess B is h3. Wherein the width of the gate polysilicon 403 is w.
Returning to fig. 3, at step S310, the first recess and the second recess are gate dielectric layer filled. For example, silicon dioxide, silicon nitride or various high-K materials can be filled in the first groove and the second groove as the gate dielectric layer.
At step S311, after the gate dielectric layer filling is completed, filling of the metal gate into the second recess of the first recess may be continued.
The filling operation can be performed by using different metal materials. For example, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, or other suitable metal materials may be used to complete the filling of the metal gate. The filled semiconductor structure may be referred to in fig. 4e and 4f. In fig. 4e and 4f, the first recess and the second recess may be filled with silicon dioxide, silicon nitride, or various high-K materials as the gate dielectric layer 408. Then, after the filling of the gate dielectric layer 408 is completed, the filling of the metal gate into the second recess in the first recess may be continued to complete the filling of the gate 409. That is, the gate 408 of the semiconductor shown in fig. 4e and 4f may be specifically fabricated using the fabrication process shown in fig. 3.
In addition, for the semiconductor structure shown in fig. 4e and 4f, the channel length (L) of the semiconductor structure is related to the length (L) of the gate polysilicon, the sinking height (h 1) of the well regions on both sides of the gate polysilicon, and the thickness (h 2) of the sacrificial layer, and the channel width (W) of the semiconductor structure is related to the width (W) of the gate polysilicon and the height (h 3) of the second recess. Specifically, in some embodiments, the channel length l=l+2h1+2h2 of the semiconductor structure, and the channel width w=w+2h3 of the semiconductor structure. The specific values of the parameters h1, h2 and h3 are not limited, and may be designed in combination with the performance requirements of the prepared semiconductor device.
The application has the unexpected beneficial technical effect that the scheme of the application can realize the effective improvement of the short channel effect by changing the structure of the semiconductor device on the basis of the existing nano process node. Furthermore, the present application can combine the prior larger nanometer technology and the proposal of the present application to realize the promotion of the nanometer technology node, so that the prepared semiconductor device has the performance of the semiconductor device prepared by adopting the smaller nanometer technology node. Meanwhile, the whole preparation process node does not involve the change of the area of a device, does not additionally increase the number of masks (masks), and does not generate additional production cost.
It should be noted that although the operations of the method of the present application are depicted in the drawings in a particular order, this does not require or imply that the operations must be performed in that particular order or that all of the illustrated operations be performed in order to achieve desirable results. Rather, the steps depicted in the flowcharts may change the order of execution. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.
While various embodiments of the present application have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the application. It should be understood that various alternatives to the embodiments of the application described herein may be employed in practicing the application. The appended claims are intended to define the scope of the application and are therefore to cover all equivalents or alternatives falling within the scope of these claims.
Claims (10)
1. A method for fabricating a semiconductor gate structure, comprising:
Providing a substrate and forming gate polysilicon on the substrate, wherein well regions on two sides of the gate polysilicon are subjected to sinking treatment in the forming process of the gate polysilicon;
Forming side wall structures on two sides of the grid polysilicon along the length direction of the channel of the semiconductor, wherein the side wall structures comprise sacrificial layers formed on two sides of the grid polysilicon and side wall layers formed on the outer sides of the sacrificial layers;
Removing the gate polysilicon and the sacrificial layer to form a first groove, wherein a shallow groove isolation region is also formed in the well region of the substrate, sinking the contact parts between the two sides of the gate polysilicon and the shallow groove isolation region along the channel width direction of the semiconductor in the removing process of the gate polysilicon to form a second groove on the shallow groove isolation region, and
And carrying out grid filling treatment on the first groove and the second groove.
2. The method of claim 1, wherein the sinking the well regions on both sides of the gate polysilicon comprises:
and carrying out etching treatment on the well regions at the two sides of the grid polycrystalline silicon so that the well regions at the two sides of the grid polycrystalline silicon sink to a first height.
3. The method of claim 1, wherein forming sidewall structures on both sides of the gate polysilicon comprises:
forming a sacrificial layer with a predetermined thickness on both sides of the gate polysilicon, and
And forming the side wall layer on the outer side of the sacrificial layer, wherein the sacrificial layer and the side wall layer are made of different materials.
4. A method of manufacturing according to claim 3, wherein the sacrificial layer is made of silicon oxide.
5. The method of claim 1, wherein removing the gate polysilicon and the sacrificial layer comprises:
after the side wall structure is formed, forming an interlayer medium on the well region of the substrate, so that the gate polysilicon and the side wall structure are covered by the interlayer medium;
removing interlayer dielectric above the gate polysilicon and the sacrificial layer in the sidewall structure to expose the gate polysilicon and the sacrificial layer, and
And removing the grid polysilicon and the sacrificial layer to form the first groove.
6. The method of claim 5, wherein removing interlayer dielectric over the gate polysilicon and the sacrificial layer in the sidewall structure comprises:
And removing interlayer dielectric above the grid polysilicon and the sacrificial layer in the side wall structure by adopting a chemical mechanical planarization technology.
7. The method of claim 1, wherein sinking the contact portions between the two sides of the gate polysilicon and the shallow trench isolation region comprises:
And carrying out etching treatment on the contact parts of the two sides of the grid polycrystalline silicon and the shallow slot isolation region, so that the shallow slot isolation region is sunk to a second height to form the second groove.
8. The method of any one of claims 1-7, wherein performing gate filling processing on the first and second grooves comprises:
filling the first groove and the second groove with a high-K dielectric layer, and
And after the high-K dielectric layer is filled, continuing to fill the metal gate into the first groove and the second groove.
9. A semiconductor structure, comprising:
A substrate;
a gate electrode, a source electrode and a drain electrode formed on the substrate, wherein,
The gate is manufactured by the manufacturing method according to any one of claims 1 to 8, the channel length of the semiconductor structure is related to the length of the gate polysilicon, the sinking height of the well regions on two sides of the gate polysilicon and the thickness of the sacrificial layer, and the channel width of the semiconductor structure is related to the width of the gate polysilicon and the height of the second groove.
10. The semiconductor structure of claim 9, wherein:
The channel length L=l+2h1+2h2 of the semiconductor structure, wherein L represents the length of the gate polysilicon, h1 represents the sinking height of the well regions at two sides of the gate polysilicon, and h2 represents the thickness of the sacrificial layer;
The channel width w=w+2h3 of the semiconductor structure, wherein W represents the width of the gate polysilicon, and h3 represents the height of the second groove.
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