CN110571141B

CN110571141B - Method for manufacturing metal gate and method for manufacturing semiconductor device

Info

Publication number: CN110571141B
Application number: CN201810570137.9A
Authority: CN
Inventors: 纪世良; 张海洋
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-06-05
Filing date: 2018-06-05
Publication date: 2022-01-28
Anticipated expiration: 2038-06-05
Also published as: CN110571141A

Abstract

The present invention provides a method for manufacturing a metal gate and a method for manufacturing a semiconductor device. Before removing the dummy gate to form an opening for filling the metal gate, a portion of the initial side on the sidewall of the dummy gate is first The wall is material modified so that the original side wall is transformed into a first side wall without material modification and a second side wall located on the first side wall and which has undergone material modification, so that it can be removed At the same time as the dummy gate is removed, all or part of the second spacer is removed, so that after the process of removing the dummy gate is completed, an opening with an upper width and a lower width for filling the metal gate can be formed, and the aspect ratio of the opening can be reduced Therefore, the gap filling capability of the subsequent metal gate can be improved, and the occurrence of defects such as filling holes and gaps in the metal gate can be reduced, thereby improving the performance of the final semiconductor device.

Description

Method for manufacturing metal gate and method for manufacturing semiconductor device

Technical Field

The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a method for manufacturing a metal gate and a method for manufacturing a semiconductor device.

Background

With the continuous improvement of the integration of semiconductor devices, when manufacturing MOS transistors, a high-K Metal Gate using a high-K (dielectric constant K is greater than or equal to 10) material as a Gate dielectric layer and a Metal material as a Gate electrode has become a mainstream technology of 32 nm and below processes for manufacturing semiconductor devices, and is currently manufactured by a Gate-last (Replacement Metal Gate) process, wherein a conventional polysilicon Gate process is usually adopted to manufacture a Dummy polysilicon Gate (also referred to as a Dummy Gate or a sacrificial Gate), and after high-temperature annealing of source and drain electrodes, a wet etching process is used to remove the Dummy polysilicon Gate, a hollow Gate trench is formed at the position of the original Dummy polysilicon Gate, and then the high-K material, work function Metal material, Metal Gate electrode material and the like are filled, therefore, the work function value of the high-K metal gate can be freely adjusted, and the threshold voltage (Vt) of the device can be fully controlled. However, in a new process technology node below 28 nm, the size of the gate is gradually reduced, the Aspect Ratio (Aspect Ratio) in the gate trench is gradually increased, gap filling of the high-K metal gate is affected, defects such as voids (Void) or gaps (seam) are easily generated, and improvement of device performance is seriously affected.

Disclosure of Invention

The invention aims to provide a manufacturing method of a metal grid and a manufacturing method of a semiconductor device, which can reduce the depth-to-width ratio of an opening for filling the metal grid, improve the gap filling capacity of the metal grid, reduce the defects of filling holes, gaps and the like and improve the performance of the device.

In order to achieve the above object, the present invention provides a method for manufacturing a metal gate, including the steps of:

providing an interlayer dielectric layer, wherein a virtual grid with the top surface exposed is formed in the interlayer dielectric layer, and an initial side wall is formed between the side wall of the virtual grid and the interlayer dielectric layer;

performing material modification on part of the initial side wall to form a first side wall which is not subjected to material modification and a second side wall which is positioned on the first side wall and is subjected to material modification;

removing the dummy gate and part or all of the second side wall to form an opening with a wide top and a narrow bottom;

and forming a metal gate filled in the opening.

Optionally, the step of providing an interlayer dielectric layer on which the dummy gate and the initial sidewall spacer are formed includes:

providing a semiconductor substrate, and forming the virtual grid on the surface of the semiconductor substrate;

forming the initial side wall on the side wall of the virtual grid;

covering interlayer dielectric materials on the surfaces of the semiconductor substrate, the virtual grid and the side wall, and carrying out top planarization and/or back etching on the interlayer dielectric materials to form an interlayer dielectric layer exposing the top of the initial side wall and the top of the virtual grid.

Optionally, after the interlayer dielectric layer exposing the top of the initial sidewall and the top of the dummy gate is formed, etching and removing a part of the thickness of the dummy gate, so that the top of the dummy gate is lower than the top of the initial sidewall.

Optionally, a dry etching process is used to etch and remove a part of the thickness of the dummy gate.

Optionally, before and/or after removing a part of the thickness of the dummy gate, material modification is performed on the initial sidewall.

Optionally, an ion implantation process is used for performing ion implantation on the initial side wall, and/or a plasma surface treatment process is used for treating the surface of the initial side wall, so as to perform material modification on part of the initial side wall, and form a first side wall which is not subjected to material modification and a second side wall which is located on the first side wall and is subjected to material modification.

Optionally, the implanted ions of the ion implantation process include at least one of hydrogen, carbon, sulfur, phosphorus, fluorine, chlorine, and oxygen.

Optionally, the initial side wall is of a single-layer structure or a stacked structure, and the material of the initial side wall includes silicon nitride.

Optionally, a wet etching process is used to remove the dummy gate and the second sidewall to form an opening with a wide top and a narrow bottom.

Optionally, the wet etching process includes: removing the virtual grid electrode by adopting first etching liquid; and etching and removing the second side wall by using second etching liquid different from the first etching liquid.

Optionally, the first etching solution is an alkaline solution, and/or the second etching solution is an acidic solution.

Optionally, the first etching solution includes a potassium hydroxide solution or a tetramethylammonium hydroxide solution; and/or the second etching liquid comprises hydrofluoric acid.

Optionally, the lateral thickness of the second sidewall is not more than 50 angstroms.

Optionally, the step of forming the metal gate filled in the opening includes:

depositing a work function metal layer on the side wall and the bottom wall of the opening, wherein the deposited work function metal layer does not fill the opening;

filling metal gate electrode material in the opening;

and flattening the top of the metal gate electrode material until reaching the top of the interlayer dielectric layer to form a metal gate.

Optionally, before depositing the work function metal layer on the side wall and the bottom wall of the opening, a high-K dielectric layer and a metal barrier layer are further deposited on the side wall and the bottom wall of the opening; and/or, before filling of the metal gate electrode material in the opening, a metal barrier layer is further deposited on the surface of the work function metal layer.

The invention also provides a manufacturing method of the semiconductor device, and the required metal grid is formed by adopting the manufacturing method of the metal grid.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

1. according to the manufacturing method of the metal grid, before the virtual grid is removed to form the opening for filling the metal grid, part of the initial side wall on the side wall of the virtual grid is subjected to material modification, so that the initial side wall is converted into the first side wall which is not subjected to material modification and the second side wall which is positioned on the first side wall and is subjected to material modification, all or part of the second side wall can be removed while the virtual grid is removed, the opening which is wide at the top and narrow at the bottom and used for filling the metal grid can be formed after the process of removing the virtual grid is finished, the depth-to-width ratio of the opening is reduced, the gap filling capacity of the subsequent metal grid can be improved, and the defects such as filling holes and gaps of the metal grid can be reduced.

2. According to the manufacturing method of the semiconductor device, the required metal grid is formed by adopting the manufacturing method of the metal grid, so that the performance of the finally manufactured semiconductor device can be improved.

Drawings

Fig. 1A to fig. 1C are schematic cross-sectional views of a device structure in a method for manufacturing a metal gate;

FIG. 2 is a flow chart of a method of fabricating a metal gate in accordance with an embodiment of the present invention;

fig. 3A to 3E are schematic cross-sectional views of the device structure in the method for manufacturing the metal gate shown in fig. 2.

Detailed Description

A method for manufacturing a high-K metal gate comprises the following steps:

firstly, referring to fig. 1A, a semiconductor substrate 100 is provided, a polysilicon gate 102 is formed on the semiconductor substrate 100 as a dummy gate to be replaced by a subsequent metal gate, and a sidewall 103 is formed on a sidewall of the polysilicon gate 102;

next, with reference to fig. 1A, depositing an interlayer dielectric layer 101, and performing chemical mechanical planarization on the top of the deposited interlayer dielectric layer 101 until the top surface of the polysilicon gate 102 is exposed;

then, referring to fig. 1A and fig. 1B, a dry etching process is first used to partially etch the exposed polysilicon gate 102, so as to provide an etching solution storage region for subsequent wet etching, thereby improving the effect of the subsequent wet etching; then, tetramethyl ammonium hydroxide solution (THMA) is adopted to completely remove the rest of the polysilicon gate, so that an opening 102a is formed at the position of the original polysilicon gate 102;

next, referring to fig. 1B and fig. 1C, a high-K gate dielectric layer 104a, a work function metal layer 104B, and a metal gate electrode layer 104C are sequentially deposited on the surface of the interlayer dielectric layer 101 and the opening, the thickness of the deposited metal gate electrode layer 104C is enough to fill up the space of the opening 102a on the surface of the work function metal layer 104B, and the deposited metal gate electrode layer 104C is chemically and mechanically planarized by a chemical and mechanical planarization process until the surface of the interlayer dielectric layer 101 is exposed, so as to form the high-K metal gate 104, wherein the high-K metal gate 104 is mainly formed by stacking the high-K gate dielectric layer 104a, the work function metal layer 104B, and the metal gate electrode layer 104C in the opening.

In the above method, the aspect ratio of the opening 102a formed by removing the polysilicon gate 102 is large, which seriously affects the subsequent filling of the metal gate, easily causes the problems of filling holes, gaps, and the like, and affects the device performance. Although MOSFET devices are scaled down to 45nm and below, and then FinFET (fin field effect transistor, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top and sidewalls of the fin, and a source region and a drain region located in the fin on both sides of the gate structure) devices can be used to effectively control the Short Channel Effect (SCE) that is difficult to overcome due to scaling down of the devices, and improve device performance, as the device size is scaled down to 14nm and below, the aspect ratio of the gate structure becomes larger and larger, and it becomes more and more difficult to manufacture an opening for filling a metal gate through a gate-last process, and the above-mentioned problems of filling voids, gaps, etc. have become the most important reason for restricting the improvement of device performance.

According to the manufacturing method of the metal gate and the semiconductor device, before the polysilicon gate is removed, the side wall on the side wall of the polysilicon gate is subjected to material modification, so that the side wall can be partially removed in the process of removing the polysilicon gate, an inverted trapezoidal opening with a wide upper part and a narrow lower part and a reduced depth-to-width ratio is formed, the gap filling capacity of the metal gate is improved, defects such as filling holes and gaps are avoided, and the manufacturing method is suitable for manufacturing semiconductor devices (such as FinFETs) with technical nodes below 14nm (such as 10nm, 7nm and 5 nm).

The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.

The invention provides a manufacturing method of a metal gate, which comprises the following steps:

s1, providing an interlayer dielectric layer, wherein a virtual grid with the top surface exposed is formed in the interlayer dielectric layer, and an initial side wall is formed between the side wall of the virtual grid and the interlayer dielectric layer;

s2, performing material modification on part of the initial side wall to form a first side wall which is not subjected to material modification and a second side wall which is located on the first side wall and is subjected to material modification;

s3, removing the dummy gate and part or all of the second side wall to form an opening with a wide top and a narrow bottom;

and S4, forming a metal gate filled in the opening.

Referring to fig. 3A, the specific process of step S1 includes:

firstly, providing a semiconductor substrate 300, wherein the semiconductor substrate 300 provides a working platform for subsequent processes, and can be any semiconductor substrate known by persons skilled in the art, such as a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate or a semiconductor substrate with a semiconductor epitaxial layer with a certain thickness on the surface of the substrate; the semiconductor substrate 300 may have a device isolation structure and a well structure (not shown) formed therein. In addition, when the semiconductor device to be formed is a FinFET device, a plurality of protruding fins (Fin) and an isolation structure located between two adjacent fins and having a surface flush with or lower than the top surface of the Fin are formed in the semiconductor substrate 300; the process of providing the semiconductor substrate 300 is not a focus of the present invention and will not be described herein;

then, a gate dielectric layer (not shown) may be formed on the surface of the semiconductor substrate 300 by a deposition process, a thermal oxidation process, or the like, a dummy gate material layer may be further deposited on the surface of the gate dielectric layer by the deposition process, and portions of the dummy gate material layer and the gate dielectric layer (not shown) may be removed by a photolithography and etching process to form the dummy gate 302, where the gate dielectric layer 301a may be made of a material that may include silicon dioxide (SiO)₂) And/or high-K gate dielectric material (e.g., hafnium oxide, etc.), the material of the dummy gate 302 may include polysilicon (including doped polysilicon and/or undoped polysilicon), amorphous silicon (including doped amorphous silicon and/or undoped amorphous silicon), amorphous carbon, photoresist, and metal silicideAt least one of the above, the dummy Gate needs to be replaced by a High-K Metal Gate (HKMG) through a Gate Last process, and the deposition thickness of the dummy Gate determines the height of the Metal Gate to be formed subsequently;

then, depositing at least one layer of side wall material including silicon nitride on the surfaces of the virtual gate 302 and the semiconductor substrate 300 by using processes such as chemical vapor deposition and the like, and etching all the deposited side wall materials to form an initial side wall 303 for protecting the side wall of the virtual gate 302, wherein when the deposited side wall material is one layer, the initial side wall 303 is of a single-layer structure, and when the deposited side wall material is multiple layers, the initial side wall 303 is of a laminated structure; in addition, before or after the initial side walls 303 are formed, source and drain regions may be formed in the semiconductor substrate 300 on both sides of the dummy gate 302 by a known source and drain process, for example, an ion implantation process, where the process includes performing heavily doped source and drain ion implantation on the semiconductor substrate 300 on both sides of the dummy gate 302; the known source and drain process is, for example, an embedded source and drain epitaxial growth process, and the process includes: etching the semiconductor substrate 300 on two sides of the virtual grid 302 to form a source drain groove, and epitaxially growing a semiconductor layer which is different from the material of the semiconductor substrate 300 in the source drain groove to form an embedded source drain region;

then, a chemical vapor deposition, a coating and other processes may be adopted to cover the surface of the semiconductor substrate 300, the initial sidewall 303 and the dummy gate 302 with an interlayer dielectric material, where the interlayer dielectric material may be silicon dioxide, silicon oxynitride, a Tetraethylorthosilicate (TEOS) \\ low-K dielectric material with a dielectric constant smaller than that of silicon dioxide, metal silicon nitride and the like, the thickness of the interlayer dielectric material on the surface of the semiconductor substrate 300 is greater than the stacking thickness of the dummy gate and the gate dielectric layer, and the covered interlayer dielectric material is subjected to top planarization (for example, chemical mechanical planarization CMP) and/or Etch back (Etch back) to form an interlayer dielectric layer 301 exposing the top of the initial sidewall 303 and the top of the dummy gate 302, where the top planarization (CMP) is performed on the covered interlayer dielectric material to finally reduce the heights of the initial sidewall 303 and the dummy gate, in this embodiment, the top of the covered interlayer dielectric material is first planarized chemically and mechanically to the top of the virtual gate 302, and then etched back to some extent to form the interlayer dielectric layer 301, so as to better expose the top of the initial sidewall 303 and the top of the virtual gate 302;

then, the dummy gate 302 with a partial thickness is removed by using a dry etching process, which is equivalent to performing a certain back etching on the dummy gate 302, so that the top of the dummy gate 302 is lower than the top of the sidewall 303 to form a groove 302a, the groove 302a can provide a better process window for the material modification process in the subsequent step S2, thereby ensuring the effect of performing material modification on the initial sidewall, and simultaneously providing a stagnation space for an etching solution of the wet etching process for removing the dummy gate 302 in the subsequent step S3, thereby increasing the removal rate of the dummy gate 302, wherein the dry etching process can select HBr as a main etching gas, and select O3 as the main etching gas₂Or Ar is used as an etching supplementary gas, so that the etching quality can be improved. In other embodiments of the present invention, if the subsequent modification effect on the initial sidewall 303 and the subsequent removal effect on the dummy gate 303 are not affected, the step of performing back etching on the top of the dummy gate 302 to form the groove 302a may also be omitted.

Referring to fig. 3C, step S2 may be performed before and/or after forming the recess 302a by removing a portion of the thickness of the dummy gate 302 through a dry etching process, the ion implantation process may be selected to perform ion implantation on the initial sidewall 303 exposed from the groove 302a to modify a portion of the initial sidewall 303, or the plasma surface treatment process may be adopted to treat the exposed surface of the initial sidewall 303 to modify the material of the initial sidewall 303, therefore, the initial sidewall 303 is converted into a first sidewall 303a which is not subjected to material modification and a second sidewall 303b which is located on the first sidewall 303a and is subjected to material modification, the etching ratio of the second sidewall 303b is improved compared with that of the first sidewall 303a, and the etching process for removing the dummy gate in the subsequent step S3 can be simultaneously completely removed or mostly removed. When the ion implantation process is employed, the implanted ions into the initial sidewall 303 may include at least one of hydrogen, carbon, sulfur, phosphorus, fluorine, chlorine, and oxygen. For example, in this embodiment, after the groove 302a is formed, hydrogen ions are implanted into the initial sidewall 303 exposed by the groove 302a by using an oblique ion implantation process, the implantation depth of the hydrogen ions depends on the requirements of a subsequent opening to be formed with a wide top and a narrow bottom (i.e., depends on the requirements of device performance), annealing is performed to enhance the diffusion depth and distribution uniformity of the hydrogen ions, the implanted hydrogen ions can break original chemical bonds in the initial sidewall 303, so that the initial sidewall 303 at the top of the groove 302a can be modified to be converted into a second sidewall 303b, the portion covered by the second sidewall 303b and not penetrated by the hydrogen ions is the first sidewall 303a not modified by a material, the first sidewall 303a still maintains the same characteristics as the initial sidewall 303a, and in the subsequent etching process of removing the dummy gate in step S3, the etching selection ratio of the second sidewall 303b to the first sidewall 303a can reach 6, the second side walls 303b are easily removed by the etching process for removing the dummy gate.

Referring to fig. 3D, in step S3, one or more alkaline solutions of KOH (mass fraction may be 5% to 50%) and tetramethylammonium hydroxide (TMAH, mass fraction may be 1% to 50%) are first used as a first etching solution to perform wet etching on the dummy gate 302, and the temperature of the etching process is strictly controlled at the same time until all or most of the dummy gate 302 is removed, because the second sidewall 303b is modified by a material, the etching selectivity is smaller than that of the dummy gate 302, and a part of the dummy gate 302 is removed; then, acid solution such as hydrofluoric acid (DHF) is used as second etching solution to perform a certain over-etching on the dummy gate 302 to remove the remaining second sidewall 303b, because the second sidewall 303b is located at the upper portion and is mainly close to the sidewall of the groove 302a, the upper portion of the opening 302b after the dummy gate 302 is removed can be trimmed to be an inverted trapezoid structure with a wide upper portion and a narrow lower portion, and because the first sidewall 303a is not modified by material at the lower portion of the opening 302b, the etching selectivity between the first sidewall 303a and the dummy gate 302 is kept higher, so that the opening 302 is still not easily etched in the etching process for removing the dummy gate 302, and the shape of the opening 302 is basically the same as that of the portion of the dummy gate 302 (i.e., the shape of the portion of the opening formed in the original process is basically the same), thereby increasing the aspect ratio of the opening. Meanwhile, the second sidewalls 302b on the sidewalls of the grooves 302a are etched to a certain extent when the first etching solution is used to etch and remove all or most of the dummy gates 302, so that a relatively large etching window can be provided, and the subsequent etching speed and effect of the dummy gates 302 are improved. In this embodiment, the thickness of the second sidewall 303 is not more than 50 angstroms, and the width between the bottom and the top of the single side of the opening 302b is not more than 100 angstroms.

Referring to fig. 3E, in step S4, first, a high-K dielectric layer 304a and a work function metal layer (work function layer)304b are sequentially deposited on the interlayer dielectric layer 301 and the sidewalls and the bottom of the opening 302b, and at this time, the opening 302b is still not filled; the high-K dielectric layer 304a is typically formed by Atomic Layer Deposition (ALD), so as to ensure that the deposited high-K dielectric layer 304a has excellent coverage (uniformity) on the sidewall of the opening 302b, and the material thereof may be one or more of hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, and hafnium zirconium oxide; the work function metal layer 304b is formed by Radio Frequency Physical Vapor Deposition (RFPVD), and may be made of one or more of Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, and TiAlN, where TiN is commonly used as a work function metal layer in a metal gate of a P-type metal oxide semiconductor (PMOS) transistor, and TiAl is commonly used as a work function metal layer in a metal gate of an N-type metal oxide semiconductor (NMOS) transistor; then, a metal gate electrode material 304c is continuously deposited on the surface of the work function metal layer 304b by using a process such as vacuum evaporation, sputtering, electroplating or chemical vapor deposition, and the like, wherein the deposited thickness is enough to fill the opening 302b, that is, the metal gate electrode material 304c is filled in the opening 302 b; next, the metal gate electrode material 304c is planarized to the top of the interlayer dielectric layer 301 to form a metal gate 304, so as to provide a planar process surface for the subsequent processes. The material of the metal gate electrode material can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN and WSi. In addition, in this step, before depositing the work function metal layer 304b, at least one metal barrier layer for blocking diffusion of the metal gate electrode material and the metal in the work function metal layer into the high-K gate dielectric layer 304a may be formed on the surface of the high-K dielectric layer 304a, and after depositing the work function metal layer 304b and before depositing the metal gate electrode material 304c, at least one metal barrier layer for blocking downward diffusion of the metal in the metal gate electrode material 304c may be formed on the surface of the work function metal layer 304 b.

In the manufacturing method of the metal gate, before the dummy gate is removed to form the opening for filling the metal gate, material modification is performed on part of the initial sidewall on the sidewall of the dummy gate, so that the initial sidewall is changed into the first sidewall which is not subjected to material modification and the second sidewall which is located on the first sidewall and is subjected to material modification, and thus, part or all of the second sidewall can be removed while the dummy gate is removed, so that the opening which is wide at the top and narrow at the bottom and is used for filling the metal gate can be formed at the position where the dummy gate is removed, and the aspect ratio of the opening is reduced, thereby improving the gap filling capability of the subsequent metal gate, and reducing the defects such as filling holes and gaps of the metal gate.

The invention also provides a manufacturing method of the semiconductor device, and the required metal grid is formed by adopting the manufacturing method of the metal grid. The semiconductor device finally manufactured by the manufacturing method of the semiconductor device can be a planar MOS device, a FinFET device or a memory device. Taking a FinFET device as an example, the manufacturing method of the semiconductor device comprises the following steps:

s1, providing a semiconductor substrate with a fin, forming a virtual grid on the surface of the fin, forming an initial side wall on the side wall of the virtual grid, and forming an interlayer dielectric layer covering the whole surface of the semiconductor substrate including the fin, wherein the interlayer dielectric layer exposes the side wall and the top of the virtual grid; etching to remove the partial thickness of the virtual grid electrode so that the top of the virtual grid electrode is lower than the top of the initial side wall to form a groove;

s3, removing the dummy gate and the second side wall to form an opening with a wide upper part and a narrow lower part;

and S4, forming a metal gate filled in the opening.

According to the manufacturing method of the semiconductor device, the required metal grid is formed by adopting the manufacturing method of the metal grid, so that the defects of filling holes, gaps and the like of the metal grid are avoided, and the performance of the finally manufactured semiconductor device can be improved.

It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for manufacturing a metal gate electrode comprises the following steps:

etching to remove part of the thickness of the dummy gate, so that the top of the dummy gate is lower than the top of the initial side wall to form a groove;

performing material modification on the initial side walls exposed at two sides of the groove to form a first side wall which is not subjected to material modification and a second side wall which is located on the first side wall and is subjected to material modification, wherein the second side wall is gradually thinned from top to bottom;

removing the dummy gate and the second side wall along the groove by adopting a wet etching process, wherein the first side wall is not etched in the wet etching process so as to form an opening with a wide upper part and a narrow lower part;

and forming a metal gate filled in the opening.

2. The method of claim 1, wherein the step of providing an interlayer dielectric layer with the dummy gate and the initial sidewall spacers comprises:

forming the initial side wall on the side wall of the virtual grid;

3. The method of claim 1, wherein the dummy gate is etched to remove a portion of the thickness by a dry etching process.

4. The method according to any of claims 1 to 3, wherein the initial sidewall is ion-implanted by an ion implantation process and/or a plasma surface treatment process is performed on the surface of the initial sidewall to modify the material of a portion of the initial sidewall, thereby forming a first sidewall without material modification and a second sidewall which is located on the first sidewall and is material-modified.

5. The method of claim 4, wherein the implanted ions of the ion implantation process comprise at least one of hydrogen, carbon, sulfur, phosphorus, fluorine, chlorine, and oxygen.

6. The method according to claim 4, wherein the initial sidewall spacer has a single-layer structure or a stacked structure, and the initial sidewall spacer is made of silicon nitride.

7. The method of manufacturing a metal gate of claim 1, wherein the wet etching process comprises: removing the virtual grid electrode by adopting first etching liquid; and etching and removing the second side wall by using second etching liquid different from the first etching liquid.

8. The method of claim 7, wherein the first etching solution is an alkaline solution, and/or the second etching solution is an acidic solution.

9. The method of claim 8, wherein the first etching solution comprises a potassium hydroxide solution or a tetramethylammonium hydroxide solution; and/or the second etching liquid comprises hydrofluoric acid.

10. The method of claim 1, wherein the second sidewall spacers have a lateral thickness of no more than 50 angstroms.

11. The method of claim 1, wherein the step of forming the metal gate filled in the opening comprises:

depositing a work function metal layer on the side wall and the bottom wall of the opening, wherein the deposited work function metal layer partially fills the opening;

filling metal gate electrode material in the opening;

and flattening the top of the metal gate electrode material until the metal gate electrode material is flush with the top of the interlayer dielectric layer so as to form a metal gate.

12. The method of claim 11, further comprising depositing a high-K dielectric layer and a metal barrier layer on the sidewalls and bottom walls of the opening prior to depositing the work function metal layer on the sidewalls and bottom walls of the opening; and/or, before filling of the metal gate electrode material in the opening, a metal barrier layer is further deposited on the surface of the work function metal layer.

13. A method for manufacturing a semiconductor device, characterized in that a desired metal gate is formed by the method for manufacturing a metal gate according to any one of claims 1 to 12.