CN119063865A

CN119063865A - Temperature Sensors and Chips

Info

Publication number: CN119063865A
Application number: CN202310618581.4A
Authority: CN
Inventors: 庄凌艺; 刘莹
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-05-26
Filing date: 2023-05-26
Publication date: 2024-12-03

Abstract

The present disclosure provides a temperature sensor and a chip, which are applied in the field of integrated circuit technology. The temperature sensor includes one or more varistors, a detection circuit and a power supply circuit, wherein the varistors are arranged in a forbidden area around a through silicon via, and the varistors are formed by a substrate in the forbidden area; the varistors are connected to the power supply circuit and the detection circuit, the power supply circuit is used to supply power to one or more varistors, and the detection circuit is used to detect the resistance change value of one or more varistors to obtain the temperature change value of the forbidden area around the through silicon via. The embodiments of the present disclosure can improve the chip area utilization rate.

Description

Temperature sensor and chip

Technical Field

The disclosure relates to the technical field of integrated circuit manufacturing, in particular to a temperature sensor and a chip applying the same.

Background

TSV (Through-Silicon Via) is an integrated circuit packaging technology, and Through punching holes in the chip, metal filling holes are used, so that signal connection can be expanded from the edge of the chip to the surface of the whole chip, the number of connection between the chips or between the chips and a board can be greatly increased, and high-density and high-speed signal transmission is realized.

Since the CTE (Coefficient of Thermal Expansion ) value of the metal material filled in the TSV structure and the CTE value of silicon are greatly different, devices or circuits cannot be placed in a certain area around the TSV due to thermal mechanical stress, i.e., a Keep Out Zone (KOZ) occurs, resulting in a reduction in wafer utilization.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a temperature sensor and a chip applying the temperature sensor, which are used for improving the utilization rate of a wafer.

According to a first aspect of the disclosure, a temperature sensor is provided, wherein the temperature sensor is arranged in a forbidden area around a through silicon via and comprises one or more piezoresistors, the forbidden area is arranged around the through silicon via, the piezoresistors are formed through a substrate of the forbidden area, a power circuit is connected with the one or more piezoresistors and used for supplying power to the one or more piezoresistors, and a detection circuit is connected with the one or more piezoresistors and used for detecting resistance change values of the one or more piezoresistors so as to obtain the temperature change values of the forbidden area around the through silicon via.

In an exemplary embodiment of the disclosure, the varistor includes a first doped region and a second doped region, the first doped region and the second doped region are formed by doping a substrate of the forbidden region, a first preset value of a space exists between the first doped region and the second doped region, and the first preset value is determined according to a preset resistance value corresponding to the varistor.

In an exemplary embodiment of the present disclosure, the doping type of the first doping region and the doping type of the second doping region are the same, and the doping concentration of the first doping region and the doping concentration of the second doping region are the same.

In an exemplary embodiment of the present disclosure, the doping type of the first doping region and the doping type of the second doping region are both P-type doping.

In an exemplary embodiment of the disclosure, the temperature sensor includes four piezoresistors, where the four piezoresistors are a first piezoresistor, a second piezoresistor, a third piezoresistor, and a fourth piezoresistor, the first piezoresistor, the through silicon via, and the fourth piezoresistor are sequentially arranged in a first direction, the second piezoresistor, the through silicon via, and the third piezoresistor are sequentially arranged in a second direction, and the second direction is perpendicular to the first direction.

In an exemplary embodiment of the present disclosure, the resistances of the first varistor, the second varistor, the third varistor, and the fourth varistor are the same, the first varistor has a first end and a second end, a first predetermined value of spacing is provided between the first end and the second end, the second varistor has a first end and a second end, a first predetermined value of spacing is provided between the first end and the second end of the second varistor, the third varistor has a first end and a second end, a first predetermined value of spacing is provided between the first end and the second end of the third varistor, a first end and a second end of the fourth varistor, and a first predetermined value of spacing is provided between the first end and the second end of the fourth varistor.

In an exemplary embodiment of the present disclosure, the first and second ends of the first piezoresistor, the first and second ends of the fourth piezoresistor are sequentially arranged in the first direction, the first and second ends of the second piezoresistor are sequentially arranged in the first direction, the first and second ends of the third piezoresistor are sequentially arranged in the first direction, the first and first ends of the second piezoresistor are sequentially arranged in the second direction, and the second and second ends of the second piezoresistor are sequentially arranged in the second direction.

In an exemplary embodiment of the disclosure, the detection circuit has a first input terminal and a second input terminal, the power supply circuit has a first pole and a second pole, the first terminal of the first varistor and the first terminal of the third varistor are both connected to the first pole of the power supply circuit, the second terminal of the first varistor is connected to the first terminal of the second varistor and the first input terminal of the detection circuit, the second terminal of the third varistor is connected to the first terminal of the fourth varistor and the second input terminal of the detection circuit, and the second terminal of the second varistor and the second terminal of the fourth varistor are both connected to the second pole of the power supply circuit.

In an exemplary embodiment of the disclosure, the detecting circuit is configured to detect resistance change values of the one or more piezoresistors to obtain a temperature change value of a forbidden region around the through silicon via, where the detecting circuit obtains one voltage detection value corresponding to one detection time point by detecting a voltage difference between the first input end and the second input end, obtains resistance change values of four piezoresistors by two voltage detection values corresponding to two adjacent detection time points, and obtains a temperature change value of the forbidden region at the two adjacent detection time points according to the resistance change values of the piezoresistors and a thermal expansion coefficient of a substrate of the forbidden region.

In one exemplary embodiment of the present disclosure, the one or more piezoresistors are connected in series to form a piezoresistor string having a first end and a second end.

In one exemplary embodiment of the present disclosure, the detection circuit has an input terminal and an output terminal, the power supply circuit has a first pole and a second pole, the first terminal of the varistor string is connected to the first pole of the power supply circuit, the second terminal is connected to the input terminal of the detection circuit, and the output terminal of the detection circuit is connected to the second pole of the power supply circuit.

In an exemplary embodiment of the present disclosure, the detection circuit has a first input terminal and a second input terminal, the power supply circuit has a first pole and a second pole, the first terminal of the varistor string is connected to the first input terminal of the detection circuit and the first pole of the power supply circuit, the second terminal is connected to the second input terminal of the detection circuit and the first terminal of the fixed resistor, and the second terminal of the fixed resistor is connected to the second pole of the power supply circuit.

In one exemplary embodiment of the present disclosure, the second pole of the power circuit is a ground terminal.

In one exemplary embodiment of the present disclosure, the one or more piezoresistors are disposed around the through-silicon via, and the first and second ends of the piezoresistors are sequentially arranged in a radial direction of the through-silicon via.

According to a second aspect of the present disclosure, there is provided a chip comprising a temperature sensor as claimed in any one of the preceding claims.

According to the embodiment of the disclosure, the temperature sensor is manufactured by utilizing the material characteristics of the forbidden area around the through silicon via, the concentrated thermal mechanical stress around the TSV is changed from harmful factors into the measurement quantity of the sensor, and the temperature of the wafer/device can be monitored better while the wafer utilization rate is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic diagram of a temperature sensor in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a varistor in an embodiment of the present disclosure.

Fig. 3A and 3B are schematic diagrams of the placement of the piezoresistors in the disable region 20 in one embodiment of the present disclosure.

Fig. 4 is an equivalent circuit of the wheatstone bridge in the embodiment shown in fig. 3A, 3B.

Fig. 5A and 5B are schematic views of an arrangement of piezoresistors in another embodiment of the present disclosure.

Fig. 6A and 6B are schematic diagrams of connection of detection circuits based on the piezo-resistor arrangement shown in fig. 5A and 5B according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of detection circuit connections in one embodiment of the present disclosure.

Fig. 8 is a schematic diagram of detection circuit connections in another embodiment of the present disclosure.

Fig. 9 is a schematic diagram of detection circuit connections in yet another embodiment of the present disclosure.

Fig. 10 is a schematic diagram of the connection of the detection circuit in one embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are only schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

The following describes example embodiments of the present disclosure in detail with reference to the accompanying drawings.

Referring to fig. 1, a temperature sensor 100 may include one or more piezoresistors R, a power supply circuit 11, and a detection circuit 12.

The power supply circuit 11 is connected with the one or more piezoresistors R for supplying power to the one or more piezoresistors R, and the detection circuit 12 is connected with the one or more piezoresistors R for detecting the resistance change value of the one or more piezoresistors R so as to obtain the temperature change value of the forbidden region 20 around the through silicon via 10.

The detection circuit 12 may measure the resistance change value of the varistor R by various measurement methods. The connection relationship between the piezoresistors R and the power supply circuit 11 and the detection circuit 12 may be various due to different measurement methods, and will be shown in the following embodiments, so the embodiment of fig. 1 does not limit the connection relationship between the piezoresistors R and the power supply circuit 11 and the detection circuit 12.

In the disclosed embodiment, the through-silicon via 10 is circular in cross-section and the keep-out area 20 around the through-silicon via 10 is annular. The radius of the through silicon via 10 is r1, and the distance between the edge of the forbidden region 20 and the center of the through silicon via 10 is r2, and r2> r1.

The through silicon vias 10 are also referred to as TSV structures, which are commonly applied in the fabrication of three-dimensional stacked 3DS (3 DStacked, three-dimensional stacked) and HBM (High Bandwidth Memory ) products. The TSV is formed by etching deep holes in a wafer and then electroplating metal in the deep holes so as to improve the number of metal interconnections in the chip, and in the multilayer chip stacking technology, the signal transmission density of chips in different layers can be improved, and the difficulty of connecting wires between the chips is reduced.

Copper (Cu) is a metal filling material commonly used for TSV structures, and its CTE value is greatly different from that of a silicon (Si) material (wafer material), for example, the CDT value of Cu is 18ppm/°c, and the CDT value of Si is 6ppm/°c, so during the temperature change, a stress concentration region is formed near the TSV, and the stress in the region is obviously affected by the temperature change, so that in order to ensure that the device and circuit performance and reliability are not affected, a method is adopted at present, in which the device or circuit is not placed, that is, a Keep Out Zone (KOZ) is defined.

Therefore, when the filling metal of the through-silicon via 10 is copper, the wafer substrate material is silicon, and the radius of the through-silicon via 10 is r1, the value of r2 corresponding to the forbidden region 20 can be determined according to the CET value difference between copper and silicon and the value of r1, so as to define the forbidden region 20 corresponding to the through-silicon via 10. In general, the greater the r1 value, the greater the stress impact range of the through silicon via 10 on the surrounding substrate, and the greater the r2 value. When r1 is 10 microns or less, the KOZ region typically requires a surrounding region of tens of microns to be delineated. In one embodiment, the value of r2 is about 4-5 times the value of r 1.

In other embodiments, the through-silicon via 10 may have other cross-sectional shapes, such as rectangular, oval, etc., and accordingly, the shape and size of the disabling region 20 may be determined according to the shape of the through-silicon via 10 and the filling material, which is not particularly limited by the present disclosure.

In order to solve the problems that devices cannot be placed around the TSV (forming a forbidden area) and wafer utilization rate is reduced due to stress factors, the embodiment of the disclosure places piezoresistance devices in the forbidden area around the TSV to form a temperature sensor, and changes the thermo-mechanical stress of the forbidden area from harmful factors to the sensing quantity of the temperature sensor. The specific principle is that when the monocrystalline silicon material (substrate material of forbidden area) is subjected to external force and generates microscopic strain which can not be perceived by naked eyes, the state of electron energy level in the atomic structure changes, so that the resistivity of the monocrystalline silicon material changes drastically, and the resistance value of the resistor made of the monocrystalline silicon material also changes greatly, and the physical effect is called piezoresistive effect. Therefore, the embodiment of the disclosure forms one or more piezoresistors by using the substrate of the forbidden area around the TSV, so that the resistance value of each piezoresistor can linearly change along with the stress change based on the piezoresistance effect, and the stress change of the forbidden area changes along with the temperature, therefore, the temperature change around the TSV, namely the temperature change of a device, can be measured by measuring the resistance value change of the piezoresistor, and the temperature of a wafer/device can be better monitored while the wafer utilization rate is improved.

Referring to fig. 2, in one embodiment, the varistor R may be formed by a silicon substrate and two ohmic contact regions (formed by doping as two pins of the varistor R).

The piezoresistor R comprises a first doped region 21 and a second doped region 22, the first doped region 21 and the second doped region 22 are formed by doping the substrate in the forbidden region, a first preset value L1 is arranged between the first doped region 21 and the second doped region 22, and the first preset value L1 is determined according to a preset resistance value corresponding to the piezoresistor R. The resistances of the different piezoresistors R may be the same or different, depending on the actual measurement as shown in the following embodiments. In an embodiment, the shapes, sizes and resistance values of the piezoresistors R are the same, the first doped region 21 and the second doped region 22 have a distance of a first preset value L1, in practical application, the distances between the first doped region 21 and the second doped region 22 of different piezoresistors R may also be different values, the shapes of different piezoresistors R are different, the resistance values are different, and the embodiment of the disclosure is not limited by the values and the numbers of the distances.

In addition to the fact that the spacing between the first doped region 21 and the second doped region 22 can affect the resistance of the varistor R, the relative areas of the first doped region 21 and the second doped region 22, such as the doping depth of the first doped region 21 and the second doped region 22, and the length of the first doped region 21 and the second doped region 22 perpendicular to the screen direction, can also affect the resistance of the varistor R. With a certain distance, the longer the doping depth of the first doped region 21 and the second doped region 22 or the length perpendicular to the screen direction, the wider the charge path, the smaller the resistance, and conversely the larger the resistance. The process of the piezoresistor R can be adjusted according to actual requirements by a person skilled in the art to adjust the resistance of the piezoresistor R.

Illustratively, the resistance of the varistor R may be set to be greater than the hundred European level in order to accurately detect resistance changes.

Doped regions are formed in the inactive region 20 in order to form ohmic contacts. Ohmic contacts are a non-rectifying electrical connection, the connection between two conductors having a linear current-voltage (I-V) curve conforming to ohm's law. This connection may allow free flow of charge between the two conductors (i.e., the doped region and the substrate of the forbidden region 20 in the disclosed embodiment) while creating a voltage drop at the connection that is related to the resistance of each conductor. In ohmic contact, the resistance between the two conductors is usually very small, and the resistance value at the connection is very close to zero, which is beneficial to input and output of current, so that the embodiment of the disclosure forms the piezoresistor R by forming two doped regions in the substrate of the forbidden region 20 and the substrate of the forbidden region 20 between the two doped regions, which not only simplifies the manufacturing process of the piezoresistor R, but also changes the resistance of the piezoresistor R along with the stress change of the substrate of the forbidden region 20.

In one embodiment, the doping type of the first doped region 21 is the same as the doping type of the second doped region 22, and the doping concentration of the first doped region 21 is the same as the doping concentration of the second doped region 22. For example, the doping type of the first doping region 21 and the doping type of the second doping region 22 may be both P-type doping.

Other methods of manufacturing the varistor R using the forbidden region 20 are possible, for example, forming a semiconductor device such as a switch tube or a diode using the substrate of the forbidden region 20, so that when the semiconductor device is used as a resistor, the resistance value can be changed along with the stress change of the substrate of the forbidden region 20, and the detection circuit 12 can detect the stress change of the substrate of the forbidden region 20 by detecting the change of the resistance of one or more piezoresistors R, so as to obtain the temperature change value around the through silicon via 10.

In the following, the method for setting the varistor R in the forbidden area 20 and the connection of the varistor R to the power supply circuit 11 and the detection circuit 12 will be described with different measuring methods.

Referring to fig. 3A, in one embodiment, the temperature sensor 100 includes four piezoresistors, which are a first piezoresistor R1, a second piezoresistor R2, a third piezoresistor R3, and a fourth piezoresistor R4, respectively, wherein the first piezoresistor R1, the through silicon via 10, and the fourth piezoresistor R4 are sequentially arranged in a first direction, and the second piezoresistor R2, the through silicon via 10, and the third piezoresistor R3 are sequentially arranged in a second direction, which is perpendicular to the first direction.

In the embodiment shown in fig. 3A, the stress of the through silicon via 10 is uniformly released to the periphery, the resistance change trend of the first piezoresistor R1 and the fourth piezoresistor R4 is the same, and the resistance change trend of the second piezoresistor R2 and the third piezoresistor R3 is the same.

At this time, a wheatstone bridge may be constructed using this resistance change relationship to measure the resistance change of the four piezoresistors.

As shown in fig. 3A, when the wheatstone bridge is constructed, the resistance values of the first piezoresistor R1, the second piezoresistor R2, the third piezoresistor R3, and the fourth piezoresistor R4 may be the same, where the first piezoresistor R1 has a first end and a second end, a first preset value L1 is located between the first end and the second end, the second piezoresistor R2 has a first end and a second end, a first preset value L1 is located between the first end and the second end, the third piezoresistor R3 has a first end and a second end, a first preset value L1 is located between the first end and the second end, the fourth piezoresistor R4 has a first end and a second end, and a first preset value L1 is located between the first end and the second end. That is, the first varistor R1, the second varistor R2, the third varistor R3, and the fourth varistor R4 have the same shape and size to ensure the same resistance.

The first end and the second end of the first piezoresistor R1, the first end and the second end of the fourth piezoresistor R4 are sequentially arranged in the first direction, the first end and the second end of the second piezoresistor R2 are sequentially arranged in the first direction, the first end and the second end of the third piezoresistor R3 are sequentially arranged in the first direction, the first end of the second piezoresistor R2 and the first end of the third piezoresistor R3 are sequentially arranged in the second direction, and the second end of the second piezoresistor R2 and the second end of the third piezoresistor R3 are sequentially arranged in the second direction.

Through setting up the first end, the second end of four piezo-resistors all extend along first direction, can make the resistance value variation trend of first piezo-resistor R1, fourth piezo-resistor R4 opposite with the resistance value variation trend of second piezo-resistor R2, third piezo-resistor R3. For example, when the stress released from the through silicon via 10 to the periphery is uniformly increased, the first varistor R1 and the fourth varistor R4 are both stressed in the first direction, the charge path is shortened, the charge transfer rate is increased, and the resistance is reduced, and the second varistor R2 and the third varistor R3 are both stressed in the second direction, the charge path is narrowed, the charge transfer rate is reduced, and the resistance is increased. And vice versa.

By aligning the pins of the first varistor R1 and the fourth varistor R4 and aligning the pins of the second varistor R2 and the third varistor R3, the resistance change values of the first varistor R1 and the fourth varistor R4 can be made as identical as possible, and the resistance change values of the second varistor R2 and the third varistor R3 can be made as identical as possible.

Further, referring to fig. 3B, a distance between the first piezo-resistor R1 and the fourth piezo-resistor R4 and the center of the through silicon via 10 may be set, and a distance between the second piezo-resistor R2 and the third piezo-resistor R3 and the center of the through silicon via 10 may be set, so that the resistance change values of the first piezo-resistor R1 and the fourth piezo-resistor R4 are identical, and the resistance change values of the second piezo-resistor R2 and the third piezo-resistor R3 are identical.

In addition, the values of the second preset value L2 and the third preset value L3 can be adjusted, so that the numerical relation between the resistance change values of the first piezoresistor R1 and the fourth piezoresistor R4 and the resistance change values of the second piezoresistor R2 and the third piezoresistor R3 can be adjusted, and the two resistance change values are completely the same and opposite in direction. For example, the resistance values of the first piezoresistor R1 and the fourth piezoresistor R4 are increased by x ohms under the same stress condition, the resistance values of the second piezoresistor R2 and the third piezoresistor R3 are reduced by x ohms, or the resistance values of the first piezoresistor R1 and the fourth piezoresistor R4 are reduced by x ohms, and the resistance values of the second piezoresistor R2 and the third piezoresistor R3 are increased by x ohms, wherein x is a preset value.

In one embodiment, let the radius of through silicon via 1 be r1, the radius r2 of the forbidden region 2 be about 4-5 times r1, L2 be about 2-3 times r1, and L3 be about 2-3 times r 1. The geometric center of each piezoresistor R coincides with the geometric center of the through silicon via 1. The reason for this is that, on the one hand, it is necessary to bring the varistor R as close as possible to the stress in the centre of the TSV, but too close, the expansion of the TSV itself will also have an effect on the varistor R, interfering with the detection of the forbidden region 2 by the varistor R. Through experiments, when TSV is made of copper, the number relation can achieve accurate temperature detection.

Referring to fig. 4, when a plurality of piezoresistors are provided in the form shown in fig. 3A and 3B, a wheatstone bridge for detecting a change in the resistance value of each piezoresistor may be constructed by the connection relationship shown in fig. 4.

As shown in fig. 4, the detection circuit 12 has a first input terminal and a second input terminal, the power supply circuit 11 has a first pole and a second pole, the first terminal of the first varistor R1 and the first terminal of the third varistor R3 are both connected to the first pole of the power supply circuit 11, the second terminal of the first varistor R1 is connected to the first terminal of the second varistor R2 and the first input terminal of the detection circuit 12, the second terminal of the third varistor R3 is connected to the first terminal of the fourth varistor R4 and the second input terminal of the detection circuit 12, and the second terminal of the second varistor R2 and the second terminal of the fourth varistor R4 are both connected to the second pole of the power supply circuit 11.

The detection principle of the detection circuit 12 at this time is that the detection circuit 12 obtains a voltage detection value corresponding to one detection time point by detecting the voltage difference between the first input end and the second input end, obtains resistance change values of four piezoresistors by two voltage detection values corresponding to two adjacent detection time points, and obtains a temperature change value of the forbidden region at two adjacent detection time points according to the resistance change values of the piezoresistors and a Coefficient of Thermal Expansion (CTE) value of a substrate of the forbidden region.

In fig. 4, the power circuit 11 is provided to provide a constant voltage V, a first electrode of the power circuit 11 is at a positive electrode, a potential of a first input terminal of the detection circuit 12 is equal to v×r2/(r1+r2), a potential of a second input terminal of the detection circuit 12 is equal to v×r4 (r3+r4), and a difference between the two voltages, i.e., a voltage difference detected by the detection circuit 12 is equal to v×r2/(r1+r2) -r4 (r3+r4) ]. Wherein R1, R2, R3 and R4 are respectively the resistance values of the first piezoresistor R1, the second piezoresistor R2, the third piezoresistor R3 and the fourth piezoresistor R4.

Assuming that r1=r4 and r2=r3, the voltage difference Vt0 detected by the detection circuit 12 at time t0 is:

Vt0=V*(R2-R1)/(R1+R2) (1)

when the stress of the through silicon via 10 changes, and the resistance values of the first piezoresistor R1 and the fourth piezoresistor R4 increase by Δr at time t1, and the resistance values of the second piezoresistor R2 and the third piezoresistor R3 decrease by Δr, the voltage difference Vt1 detected by the detection circuit 12 at time t1 includes:

Vt1=V*(R2-R1-2ΔR)/(R1+R2) (2)

Thus, the voltage difference change value detected by the detection circuit 12 between time t1 and time t0 is Vt1-Vt0, i.e. -2v×Δr/(r1+r2). Since V, R and R2 are both known amounts, the resistance change Δr can be obtained through the above calculation process, and since the resistance change Δr has a certain functional relationship with the temperature change under a certain material, the temperature change around the through-silicon via 10 can be monitored, and the device temperature can be monitored, through the resistance change Δr and the coefficient of thermal expansion (CTE value) of the substrate of the disabling region 20, to obtain the temperature change value of the disabling region 20 between two adjacent detection time points t0 and t 1.

The change in resistance value can be amplified by the wheatstone bridge so that measuring the graphic voltage difference can measure the change in temperature with higher sensitivity. Before calculating the temperature change value, a standard temperature calibration sensor is provided through an environmental test box, so that a curve of T/DeltaV can be obtained, and DeltaV is obtained through measurement when actual measurement is carried out, and the temperature T is reversely deduced, wherein DeltaV is a voltage difference detection value of the detection circuit 12 between two adjacent time points.

Therefore, by placing piezoresistors in the peripheral KOZ area of the common TSV, the concentrated thermal mechanical stress around the TSV can be changed into the measurement quantity of the sensor from harmful factors, and the wafer area utilization rate is improved.

It should be noted that, the power supply circuit 11 and the detection circuit 12 may be disposed at positions other than the forbidden region 20 on the wafer, and when the forbidden regions corresponding to the through silicon vias on the wafer are all provided with piezoresistors, the piezoresistors in the forbidden regions of the through silicon vias may share the power supply circuit 11, and the piezoresistors in the forbidden regions of the adjacent through silicon vias may also share the detection circuit 12, so that the detection circuit 12 may comprehensively calculate the temperature variation values of the forbidden regions of the adjacent through silicon vias by respectively detecting the resistance variation of the piezoresistors in each forbidden region, thereby improving the temperature detection accuracy.

Referring to fig. 5A and 5B, in another embodiment, one or more piezoresistors R may be connected in series to form a piezoresistor string 50, the piezoresistor string 50 having a first end and a second end. In this way, a plurality of piezoresistors R are connected into one piezoresistor for measurement, so as to improve measurement accuracy.

Since the through silicon via 10 is generally smaller in size, the corresponding forbidden area 20 is also smaller in size, and thus, each varistor R disposed in the forbidden area 20 is smaller in size, and its resistance change is also smaller, which makes the measurement of the resistance change difficult, and the measurement accuracy is not high enough. Therefore, the embodiment of the present disclosure may improve the accuracy of measuring the resistance variation of the piezoresistor R by the detection circuit 12 by disposing the piezoresistor R in the disable area 20 and connecting the piezoresistors R in series to form a resistor with a larger resistance. Note that, since the resistance change amount of the varistor string 50 measured in this case is the total change amount of the plurality of varistors R, the detection circuit 12 needs to process the measured resistance change amount to obtain a correct temperature change detection result when the temperature change calculation is finally performed.

Referring to fig. 5B, since the piezoresistors are equal in position in the varistor string 50, a plurality of piezoresistors R connected in series may be disposed around the through-silicon via 10, each of the piezoresistors R having the same shape, the same size, and the same resistance, and the first and second ends of each of the piezoresistors R are sequentially arranged in the radial direction of the through-silicon via 10. In addition, the distances between the centers of the piezoresistors R and the through silicon vias 10 are the same, so that the same resistance and the same resistance variation of the piezoresistors R under the same stress condition can be ensured.

In the embodiment shown in fig. 3A and 3B, a plurality of piezoresistors R may be connected in series to form a first piezoresistor R1, a second piezoresistor R2, a third piezoresistor R3, and a fourth piezoresistor R4, so as to increase the resistance variable amounts of the first piezoresistor R1, the second piezoresistor R2, the third piezoresistor R3, and the fourth piezoresistor R4, so that the resistance variable amounts are easier to be detected, and the detection accuracy of the detection circuit 12 is improved.

Referring to fig. 6A, in one embodiment, the piezo-resistive string 50 may be measured as one resistor in a wheatstone bridge, with three fixed resistors Rc1, rc2, rc3 having fixed values of the piezo-resistive string 50 collectively forming the wheatstone bridge. The power supply circuit 11 is also provided with a first electrode having a positive polarity and a second electrode having a negative polarity, and the detection circuit 12 has a first input terminal and a second input terminal. The second terminal of the varistor string 50 is connected to the second pole of the power supply circuit 11, the first terminal of the varistor string 50 is connected to the second terminal of the fixed resistor Rc1 and the first input terminal of the detection circuit 12, and the first terminal of the fixed resistor Rc1 is connected to the first pole of the power supply circuit 11. The fixed resistors Rc2 and Rc3 are connected in series and connected in parallel between the first pole and the second stage of the power supply circuit 11, and the series node is connected to the second input terminal of the detection circuit 12.

Fig. 6B is an equivalent circuit diagram of the connection relationship shown in fig. 6A.

Referring to fig. 6A and 6B, let the voltage difference between the first pole and the second pole of the power supply circuit 11 be V, the potential of the first input terminal of the detection circuit 12 be equal to v×r50/(rc1+r50), and the potential of the second input terminal of the detection circuit 12 be equal to v×rc3 (rc2+rc3), that is, the voltage difference detected by the detection circuit 12 be equal to v×r50/(rc1+r50) -rc3 (rc2+rc3). Wherein Rc1, rc2, rc3, R50 are the resistances of the fixed resistors Rc1, rc2, rc3 and the varistor string 50, respectively.

At time t0, the voltage difference Vt0 detected by the detection circuit 12 is:

Vt0=V*[R50/(Rc1+R50)- Rc3*(Rc2+Rc3)] (3)

when the stress changes at time t1, and the resistance change value of the varistor string 50 is set to be increased Δr, the voltage difference Vt1 detected by the detection circuit 12 at time t1 includes:

Vt1=V*[(R50+ΔR)/(Rc1+R50+ΔR)- Rc3*(Rc2+Rc3)] (4)

Thus, the voltage difference change value detected by the detection circuit 12 between time t1 and time t0 is Vt1-Vt0, i.e. V [ (r50+Δr)/(r1+r50+Δr) -r50/(r1+r50) ]. Since V, rc are known values, the resistance of the varistor 50 can be measured in advance, and thus the resistance change Δr can be obtained from the voltage difference change detected by the detection circuit 12, and since the resistance change Δr is in a certain functional relationship with the temperature change under a certain material, the temperature change of the forbidden region 20 between two adjacent detection time points t0 and t1 can be obtained from the resistance change Δr and the Coefficient of Thermal Expansion (CTE) of the substrate of the forbidden region 20, and the temperature change around the through-silicon via 10 can be monitored, and the device temperature can be monitored.

In the embodiment shown in fig. 6A and 6B, only the resistance of the piezo-resistor string 50 in the wheatstone bridge will change, and the resistance change value of the piezo-resistor string 50 is the sum of the resistance change values of the plurality of piezo-resistors R, which is far greater than the resistance change value of a single piezo-resistor R, so that the resistance change value of the piezo-resistor string 50 can be accurately detected by the principle shown in the above formula, the temperature change value of the disabling area 20 is obtained, and the measurement accuracy of the temperature sensor 100 is improved.

In other embodiments, the resistance change of the piezoresistor can also be obtained directly through voltage or current measurement.

Referring to fig. 7, in one embodiment, the power supply circuit 11, the detection circuit 12, and the varistor string 50 may be directly connected in series to detect the resistance change of the varistor string 50 by detecting the current and the current change value.

In this embodiment, the detection circuit 12 has an input terminal and an output terminal, the power supply circuit 11 has a first pole and a second pole, the first terminal of the varistor string 50 is connected to the first pole of the power supply circuit 11, the second terminal is connected to the input terminal of the detection circuit 12, and the output terminal of the detection circuit 12 is connected to the second pole of the power supply circuit 11.

In this measurement mode, the detection circuit 12 is equivalent to an ammeter, and has a low internal resistance, so that the resistance change of the varistor string 50 can be obtained through current change calculation, and the temperature change value of the forbidden area 20 can be obtained.

This measurement is suitable for the case where the resistance of the varistor string 50 is large or the voltage supplied by the supply voltage 11 is small, so that the current is small. When the resistance of the varistor string 50 is still small, or the supply voltage 11 cannot be reduced to a large value, resulting in a large current being detected by the detection circuit 12, one or more large constant resistances may be connected in series in the series link to reduce the resistance detected by the detection circuit 12.

Referring to fig. 8, unlike fig. 7, the power supply circuit 11 and the detection circuit 12 are connected in series with the varistor string 50 and the constant resistance Rc, and the resistance of the constant resistance Rc is greater than or equal to the resistance of the varistor string 50, so that the current flowing through the detection circuit 12 is small, and the detection circuit 12 can detect the resistance change of the varistor string 50 by detecting the current and the current change value.

At this time, it should be noted that the resistance of the constant resistor Rc should not be so large as to be an overwhelming factor of the current, making the resistance change of the varistor string 50 difficult to be reflected, and the resistance of the constant resistor Rc should be as free from temperature influence as possible, so as to ensure the detection accuracy of the resistance change of the varistor string 50.

Referring to fig. 9, in yet another embodiment, the detection circuit 12 has a first input terminal and a second input terminal, the power supply circuit 11 has a first pole and a second pole, the first terminal of the varistor string 50 is connected to the first input terminal of the detection circuit 12 and the first pole of the power supply circuit 11, the second terminal is connected to the second input terminal of the detection circuit 12 and the first terminal of the fixed resistor Rc, and the second terminal of the fixed resistor Rc is connected to the second pole of the power supply circuit 11.

In the embodiment shown in fig. 9, the detection circuit 12 corresponds to a voltmeter connected in parallel across the varistor string 50, and detects the voltage variation across the varistor string 50 to obtain the resistance variation value of the varistor string 50. The resistance value of the fixed resistor Rc may be smaller than or equal to the resistance value of the varistor string 50, so that the voltage detected by the detection circuit 12 is larger, and thus, when the resistance value of the varistor string 50 changes, the voltage detected by the detection circuit 12 can be changed greatly, so as to improve the detection accuracy.

The connection method shown in fig. 9 is suitable for the case that the resistance value of the varistor string 50 is large or the voltage of the power circuit 11 is small, so that the current flowing through the varistor string 50 is small and the power consumption is low. When the resistance of the varistor string 50 is small, the current flowing through the varistor string 50 can be reduced by connecting resistors in series in the circuit, thereby reducing power consumption.

Referring to fig. 10, unlike fig. 9, the second terminal of the varistor string 50 is connected to the first terminal of the first fixed resistor Rcx, the second input terminal of the detection circuit 12 is connected to the second terminal of the first fixed resistor Rcx and the first terminal of the second fixed resistor Rcy, and the second terminal of the second fixed resistor Rcy is connected to the second pole of the power circuit 11.

By connecting the varistor string 50 and the first fixed resistor Rcx together to detect a voltage, the voltage detected by the detection circuit 12 can be increased, while reducing the current flowing through the varistor string 50 and reducing the power consumption of the temperature sensor 50. The resistance value of the first fixed resistor Rcx should not be so large as to be a decisive factor affecting the voltage between the first input terminal and the second input terminal of the detection circuit 12, so that the resistance change of the varistor string 50 is difficult to react on the voltage detected by the detection circuit 12, and meanwhile, the resistance value of the first fixed resistor Rcx and the resistance value of the second fixed resistor Rcy should be set to be as low as possible, so that the values of the voltages detected by the detection circuit 12 are easy to identify, and finally, the resistance values of the first fixed resistor Rcx and the second fixed resistor Rcy should be kept stable as far as possible and not affected by temperature.

In the above embodiments, when the second pole of the power circuit 11 is the negative pole, the second poles of the power circuit 11 may be each represented as the ground.

In addition, various resistors mentioned in the embodiments of the present disclosure, including a constant resistor and a fixed resistor, may be formed by parallel connection and serial connection of one resistor or a plurality of resistors, which is not limited in this disclosure.

According to a second aspect of the present disclosure, there is provided a chip comprising a temperature sensor according to any of the embodiments above. The chip provided by the embodiment of the disclosure is provided with the piezoresistor in the forbidden area of one or more through silicon vias, and the piezoresistor is used for forming the temperature sensor, so that the chip has the device temperature monitoring capability and higher area utilization rate.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A temperature sensor, which is used for detecting the temperature of a liquid, characterized by comprising the following steps:

the piezoresistors are arranged in the forbidden area around the through silicon vias and are formed through a substrate of the forbidden area;

a power circuit connected to the one or more piezoresistors for powering the one or more piezoresistors;

and the detection circuit is connected with the one or more piezoresistors and is used for detecting the resistance change value of the one or more piezoresistors so as to obtain the temperature change value of the forbidden area around the through silicon via.

2. The temperature sensor of claim 1, wherein the varistor comprises a first doped region and a second doped region, the first doped region and the second doped region each being formed by doping the substrate in the forbidden region, a first predetermined value of spacing between the first doped region and the second doped region being present, the first predetermined value being determined in accordance with a predetermined resistance value corresponding to the varistor.

3. The temperature sensor of claim 2, wherein the doping type of the first doped region is the same as the doping type of the second doped region, and the doping concentration of the first doped region is the same as the doping concentration of the second doped region.

4. The temperature sensor of claim 3, wherein the doping type of the first doped region and the doping type of the second doped region are both P-type doping.

5. The temperature sensor of claim 1, wherein the temperature sensor comprises four piezoresistors, the four piezoresistors being a first piezoresistor, a second piezoresistor, a third piezoresistor, and a fourth piezoresistor, respectively, the first piezoresistor, the through silicon via, and the fourth piezoresistor being sequentially arranged in a first direction, the second piezoresistor, the through silicon via, and the third piezoresistor being sequentially arranged in a second direction, the second direction being perpendicular to the first direction.

6. The temperature sensor of claim 5, wherein the resistances of the first, second, third, and fourth piezoresistors are the same, the first piezoresistor has a first end and a second end, a first predetermined distance is provided between the first end and the second end, the second piezoresistor has a first end and a second end, a first predetermined distance is provided between the first end and the second end of the second piezoresistor, the third piezoresistor has a first end and a second end, a first predetermined distance is provided between the first end and the second end of the third piezoresistor, the fourth piezoresistor has a first end and a second end, and a first predetermined distance is provided between the first end and the second end of the fourth piezoresistor.

7. The temperature sensor of claim 6, wherein the first and second ends of the first varistor, the first and second ends of the fourth varistor are sequentially aligned in the first direction, the first and second ends of the second varistor are sequentially aligned in the first direction, the first and second ends of the third varistor are sequentially aligned in the first direction, the first and first ends of the second varistor are sequentially aligned in the second direction, and the second and second ends of the second varistor are sequentially aligned in the second direction.

8. The temperature sensor of claim 7, wherein the detection circuit has a first input terminal and a second input terminal, the power circuit has a first pole and a second pole, the first terminal of the first varistor and the first terminal of the third varistor are both connected to the first pole of the power circuit, the second terminal of the first varistor is connected to the first terminal of the second varistor and the first input terminal of the detection circuit, the second terminal of the third varistor is connected to the first terminal of the fourth varistor and the second input terminal of the detection circuit, and the second terminal of the second varistor and the second terminal of the fourth varistor are both connected to the second pole of the power circuit.

9. The temperature sensor of claim 8, wherein the detection circuit for detecting a change in resistance of the one or more piezoresistors to obtain a change in temperature of a disable region surrounding the through silicon via comprises:

The detection circuit obtains a voltage detection value corresponding to a detection time point by detecting the voltage difference between the first input end and the second input end;

Obtaining resistance change values of the four piezoresistors through two voltage detection values corresponding to two adjacent detection time points;

And obtaining the temperature change values of the forbidden region at the two adjacent detection time points according to the resistance change values of the piezoresistor and the thermal expansion coefficient of the substrate of the forbidden region.

10. The temperature sensor of claim 1, wherein the one or more piezoresistors are connected in series to form a piezoresistor string, the piezoresistor string having a first end and a second end.

11. The temperature sensor of claim 10, wherein the sensing circuit has an input and an output, the power circuit has a first pole and a second pole, the first end of the varistor string is connected to the first pole of the power circuit, the second end is connected to the input of the sensing circuit, and the output of the sensing circuit is connected to the second pole of the power circuit.

12. The temperature sensor of claim 10, wherein the sensing circuit has a first input and a second input, the power circuit has a first pole and a second pole, the first end of the varistor string is connected to the first input of the sensing circuit and the first pole of the power circuit, the second end is connected to the second input of the sensing circuit and the first end of a fixed resistor, and the second end of the fixed resistor is connected to the second pole of the power circuit.

13. A temperature sensor according to claims 8, 11, 12, wherein the second pole of the power circuit is grounded.

14. The temperature sensor of claim 10, wherein the one or more piezoresistors are disposed around the through-silicon via and the first and second ends of the piezoresistors are arranged sequentially in a radial direction of the through-silicon via.

15. A chip comprising a temperature sensor according to any one of claims 1-14.