CN118969899A - Patterning processing device and related method - Google Patents
Patterning processing device and related method Download PDFInfo
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- CN118969899A CN118969899A CN202411010848.2A CN202411010848A CN118969899A CN 118969899 A CN118969899 A CN 118969899A CN 202411010848 A CN202411010848 A CN 202411010848A CN 118969899 A CN118969899 A CN 118969899A
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Abstract
本申请实施例涉及光伏材料加工技术领域，并提供一种图案化处理装置及相关方法。该图案化处理装置包括接地电极、激励电极以及电源。接地电极用于接收样品。激励电极位于接地电极用于接收样品的一侧。激励电极包括用于接收气体的匀气腔体。匀气腔体包括多个开口。电源与激励电极电连接，以向激励电极施加电压来激发匀气腔体内的气体产生等离子体。激励电极被设置为与样品的待处理表面的距离小于等于1mm，使得等离子体在多个开口的位置处被选择性通过，进而在待处理表面上形成与多个开口的图案相对应的图案化等离子体，来实现对待处理表面的图案化处理。
The embodiments of the present application relate to the technical field of photovoltaic material processing, and provide a patterned processing device and related methods. The patterned processing device includes a ground electrode, an excitation electrode, and a power supply. The ground electrode is used to receive a sample. The excitation electrode is located on a side of the ground electrode for receiving the sample. The excitation electrode includes a uniform gas cavity for receiving a gas. The uniform gas cavity includes a plurality of openings. The power supply is electrically connected to the excitation electrode to apply a voltage to the excitation electrode to excite the gas in the uniform gas cavity to generate plasma. The excitation electrode is set to be less than or equal to 1 mm away from the surface to be processed of the sample, so that the plasma is selectively passed at the position of the plurality of openings, thereby forming a patterned plasma corresponding to the pattern of the plurality of openings on the surface to be processed, so as to achieve patterned processing of the surface to be processed.
Description
Technical Field
The application relates to the technical field of photovoltaic material processing, in particular to a patterning device, a patterning method and a solar cell preparation method.
Background
Tunnel oxide passivation contact (tunnel oxide passivated contact, TOPCon) solar cell technology has been greatly developed due to its excellent passivation properties. However, the localized passivation contact structures in existing TOPCon solar cells require laser grooving or complex and costly masking methods to form.
Disclosure of Invention
The first aspect of the present application provides a patterning device. The patterning device includes a ground electrode, an excitation electrode, and a power supply. The ground electrode is for receiving a sample. The excitation electrode is located on the side of the ground electrode that receives the sample. The excitation electrode comprises a gas-homogenizing cavity, the gas-homogenizing cavity is used for receiving gas, the gas-homogenizing cavity comprises a bottom plate facing the grounding electrode, the bottom plate is provided with an inner surface and an outer surface which are opposite, the outer surface is closer to the grounding electrode than the inner surface, and the bottom plate is provided with a plurality of openings penetrating through the inner surface and the outer surface. The power supply is electrically connected with the excitation electrode so as to apply voltage to the excitation electrode to excite the gas in the uniform gas cavity to generate plasma. The excitation electrode is arranged such that the distance between the outer surface of the bottom plate and the surface to be treated of the sample is 1mm or less, so that the plasma is selectively passed through the positions of the plurality of openings, and further, patterned plasmas corresponding to the patterns of the plurality of openings are formed on the surface to be treated, thereby realizing the patterning treatment of the surface to be treated.
According to the patterning device provided by the first aspect of the application, the exciting electrode is designed to be hollow and provided with the structure with the plurality of openings, the distance between the exciting electrode and the surface to be treated of the sample is smaller than or equal to the threshold distance (1 mm), and under the action of the voltage applied by the power supply, the plasma in the uniform air cavity selectively passes through the plurality of openings, so that the plasma exists between the surface to be treated of the sample and the plurality of openings, but does not exist between the outer surface of the uniform air cavity of the exciting electrode and the surface to be treated of the sample, and further, the patterning plasma corresponding to the pattern of the plurality of openings can be formed on the surface to be treated of the sample without additionally arranging a mask between the exciting cathode and the sample, so that the patterning treatment of the surface to be treated is realized. Thus, the patterned plasma formed by the patterning device according to the first aspect of the present application may be used for forming a patterned thin film by plasma deposition or for forming patterned openings by plasma etching, and compared with the conventional mask or laser processing method, the patterning device of the first aspect of the present application has the advantages of simplified process and reduced cost.
In a specific application scenario, the patterning device described above may be applied to the preparation of a locally passivated contact structure in TOPCon solar cells. Wherein the pattern of the patterned plasma formed by the patterning device may be made to coincide with the pattern of the locally passivated contact structure by designing the pattern of the plurality of openings on the excitation cathode to coincide with the pattern of the locally passivated contact structure. Therefore, the patterning plasma can be formed without additionally arranging a mask, and further, the patterning deposition of the local passivation contact structure is realized, and the use of laser grooving and the mask can be effectively avoided. It is understood that the patterning device described above may also be applied to the fabrication of other semiconductor devices.
In some embodiments, the width of each opening ranges from 0.1mm to 3.0mm.
In some embodiments, the plurality of openings are a plurality of bar-shaped holes spaced apart, or the plurality of openings are interdigitated.
The second aspect of the application provides a patterning method. The patterning processing method comprises the following steps: the patterning device comprises a grounding electrode, an excitation electrode and a power supply, wherein the grounding electrode is used for receiving a sample, the excitation electrode is positioned on one side of the grounding electrode, which is used for receiving the sample, the excitation electrode comprises a uniform air cavity, the uniform air cavity is used for receiving air, the uniform air cavity comprises a bottom plate close to the grounding electrode, the bottom plate is provided with an inner surface and an outer surface which are opposite, the outer surface is closer to the grounding electrode than the inner surface, the bottom plate is provided with a plurality of openings penetrating through the inner surface and the outer surface, and the power supply is electrically connected with the excitation electrode; placing the sample on a ground electrode; inputting gas into the uniform gas cavity; and applying a voltage to the excitation electrode by a power supply to excite the gas in the uniform gas cavity to generate plasma. The excitation electrode is arranged in such a way that the distance between the outer surface of the bottom plate and the surface to be treated of the sample is less than or equal to 1mm, so that plasma selectively passes through the positions of the plurality of openings, and further, patterned plasma corresponding to the patterns of the plurality of openings is formed on the surface to be treated, so that the patterning treatment of the surface to be treated is realized.
The patterning method according to the second aspect of the present application has at least the same advantages as the patterning device according to the first aspect of the present application, and will not be described in detail.
In some embodiments, the patterning of the surface to be treated includes: and carrying out patterned deposition on the surface to be treated by the patterned plasma or carrying out patterned etching on the surface to be treated by the patterned plasma.
The third aspect of the application provides a method for manufacturing a solar cell. The preparation method of the solar cell comprises the following steps: a silicon substrate and a patterning method provided by the second aspect of the application are provided, and a passivation layer and a doped polysilicon layer are sequentially and patternwise deposited on the silicon substrate by using the patterning plasma so as to form a local passivation contact structure formed by the passivation layer and the doped polysilicon layer.
The method for manufacturing a solar cell according to the third aspect of the present application has at least the same advantages as the patterning method according to the second aspect of the present application, and will not be described in detail.
In some embodiments, providing a silicon substrate includes: providing an n-type silicon wafer, wherein the n-type silicon wafer comprises a front surface and a back surface which are opposite; and depositing an emitter layer on the front side. The passivation layer is deposited on the emitter layer in a patterning way, and the doped polysilicon layer is a p-type polysilicon layer. After forming the local passivation contact structure, the preparation method of the solar cell further comprises the following steps: depositing a front passivation anti-reflection layer on the front surface; sequentially depositing a back passivation layer, a back doped polysilicon layer and a back passivation anti-reflection layer on the back, wherein the back doped polysilicon layer is an n-type polysilicon layer; and forming a plurality of front grid lines on one side of the front surface of the n-type silicon wafer and a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein the front grid lines are in direct contact with the doped polysilicon layer, and the back grid lines penetrate through the back passivation anti-reflection layer and are in direct contact with the back doped polysilicon layer.
In some embodiments, providing a silicon substrate includes: an n-type silicon wafer is provided, the n-type silicon wafer comprising opposing front and back sides. And forming a patterned deposited layer on the front surface, wherein the doped polysilicon layer is an n-type polysilicon layer. After forming the local passivation contact structure, the preparation method of the solar cell further comprises the following steps: depositing a front passivation anti-reflection layer on the front surface; sequentially depositing a back passivation layer, a back doped polysilicon layer and a back passivation anti-reflection layer on the back, wherein the back doped polysilicon layer is a p-type polysilicon layer; and forming a plurality of front grid lines on one side of the front surface of the n-type silicon wafer and a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein the front grid lines are in direct contact with the doped polysilicon layer, and the back grid lines penetrate through the back passivation anti-reflection layer and are in direct contact with the back doped polysilicon layer.
In some embodiments, providing a silicon substrate includes: providing an n-type silicon wafer, wherein the n-type silicon wafer comprises a front surface and a back surface which are opposite; and sequentially depositing a shallow diffusion front field region and a front passivation anti-reflection layer on the front surface. A passivation layer is deposited on the back surface in a patterned manner, the passivation layer being interdigitated. The patterning deposition of the doped polysilicon layer comprises sequentially patterning deposition of an n-type polysilicon layer and a p-type polysilicon layer on the passivation layer, wherein the n-type polysilicon layer and the p-type polysilicon layer are alternately arranged in an interdigital mode at intervals. After patterning and depositing the local passivation contact structure, the preparation method of the solar cell further comprises the following steps: depositing a back passivation anti-reflection layer on one side of the back; and forming a plurality of back grid lines on one side of the back of the n-type silicon wafer, wherein part of the back grid lines are in direct contact with the n-type polysilicon layer through the back passivation anti-reflection layer, and the other part of the back grid lines are in direct contact with the p-type polysilicon layer through the back passivation anti-reflection layer.
In some embodiments, the front passivation anti-reflection layer and/or the back passivation anti-reflection layer is deposited by disposing the excitation electrode at a distance of greater than 1mm from the outer surface of the backplane to the surface of the sample to be treated.
Drawings
FIG. 1 is a schematic cross-sectional view of a patterning device according to an embodiment of the application.
Fig. 2 is a schematic structural diagram of a solar cell according to a first embodiment of the present application.
Fig. 3 is a schematic structural diagram of a solar cell according to a second embodiment of the present application.
Fig. 4 is a schematic structural diagram of a solar cell according to a third embodiment of the present application.
Description of main reference numerals: 10. a patterning device; 11. a ground electrode; 12. an excitation electrode; r, the uniform air cavity; 121. a bottom plate; 121a, an inner surface; 121b, an outer surface; o, opening; PA, plasma; D. a distance; w, width; 20. a sample; 20a, a surface to be treated; 30a, 30b, 30c, solar cell; 30. a silicon substrate; 31. an n-type silicon wafer; 31a, front face; 31b, the back; 32. an emitter layer; 33. shallow diffusion front field region; t, locally passivating the contact structure; 341. a passivation layer; 351. a doped polysilicon layer; 361. front passivation anti-reflection layer; 342. a back passivation layer; 352. a back-side doped polysilicon layer; 352N, n type polysilicon layer; 352P, p type polysilicon layer; 362. a back passivation anti-reflection layer; 371. a front gate line; 372. and a back gate line.
Detailed Description
The first aspect of the present application provides a patterning device 10. As shown in fig. 1, the patterning device 10 includes a ground electrode 11 and an excitation electrode 12. The excitation electrode 12 is also called an upper electrode plate, and the ground electrode 11 is also called a lower electrode plate. The ground electrode 11 and the excitation electrode 12 constitute a vacuum discharge unit. The ground electrode 11 is grounded, and the ground electrode 11 also serves as a sample holder for receiving the sample 20. The excitation electrode 12 is located on the side of the ground electrode 11 for receiving the sample 20. The excitation electrode 12 includes a uniform gas cavity R. The homogenizing cavity R is used for receiving gas. The air homogenizing cavity R comprises a bottom plate 121 adjacent to the ground electrode 11. The bottom plate 121 has opposite inner and outer surfaces 121a, 121b. The outer surface 121b is closer to the ground electrode 11 than the inner surface 121 a. The bottom plate 121 is provided with a plurality of openings O penetrating the inner surface 121a and the outer surface 121b.
The patterning device 10 further includes a gas source (not shown) and a power source (not shown). The homogenizing chamber R of the excitation electrode 12 communicates with a gas source to receive the gas. A power supply is electrically connected to the excitation electrode 12 to apply a voltage to the excitation electrode 12 to excite the gas within the gas homogenizing cavity R to generate plasma PA.
In some embodiments, the power source is a radio frequency power source to apply a radio frequency voltage to the excitation electrode 12, but is not limited thereto. The power source may also be a microwave type power source, for example.
In some embodiments, the excitation electrode 12 is disposed such that a distance D between the outer surface 121b of the bottom plate 121 and the surface 20a to be treated of the sample 20 is 1mm or less, so that the plasma PA is selectively passed at the plurality of openings O, and further, patterned plasma PA corresponding to the pattern of the plurality of openings O is formed on the surface 20a to be treated, to achieve the patterning treatment of the surface 20a to be treated.
In the patterning device 10, by placing the exciting electrode 12 at a position at a threshold distance (1 mm) or less from the surface 20a to be treated of the sample 20, under the voltage applied by the power supply, the plasma PA exists between the surface 20a to be treated and the plurality of openings O due to the hollow cathode effect without existing between the outer surface 121b and the surface 20a to be treated, and further, the patterning plasma PA corresponding to the pattern of the plurality of openings O can be formed on the surface 20a to be treated without additionally providing a mask between the exciting cathode 12 and the sample 20, so as to realize the patterning treatment of the surface 20a to be treated. Specifically, the patterned plasma formed by the patterning device 10 may be used for plasma deposition to form patterned films or plasma etching to form patterned openings, which may be simplified in process and reduced in cost compared to conventional masking or laser processing.
In some embodiments, the distance D between the outer surface 121b of the bottom plate 121 of the excitation electrode 12 and the surface 20a to be treated of the sample 20 is 0.5mm, but is not limited thereto. For example, the distance D between the outer surface 121b of the bottom plate 121 of the excitation electrode 12 and the surface 20a to be treated of the sample 20 is 0.1mm to 0.3mm, 0.3mm to 0.5mm, 0.5mm to 0.7mm, 0.7mm to 1mm.
In some embodiments, the patterning of the surface 20a to be treated is a patterned deposition of the surface 20a to be treated. The patterning device 10 is a Plasma Enhanced Chemical Vapor Deposition (PECVD) device. The PECVD device adopts a capacitive coupling discharge mode of parallel electrode plates. The outer surface 121b of the excitation electrode 12 and the surface of the ground electrode 11 on which the sample 20 is placed are parallel to each other.
It should be noted that, when the distance D between the outer surface 121b of the bottom plate 121 of the excitation electrode 12 and the surface 20a to be treated of the sample 20 is increased so that the distance D between the outer surface 121b of the bottom plate 121 of the excitation electrode 12 and the surface 20a to be treated of the sample 20 is greater than the threshold distance (1 mm), the plasma PA in the gas homogenizing cavity R is gradually expanded into the plasma PA uniformly spread and acts on the entire surface 20a to be treated after passing through the plurality of openings O, so that the above-mentioned patterning device 10 can further realize the conventional PECVD plating.
In a specific application scenario, the preparation of the emitter layer, the front passivation anti-reflection layer, the back passivation anti-reflection layer, and the like in TOPcon solar cells is achieved by the patterning device 10 described above by adjusting the distance D between the excitation electrode 12 and the surface 20a to be treated of the sample 20 to be greater than a threshold distance.
In other embodiments, the patterning device 10 is a plasma etching device. The patterning of the surface to be treated 20a is performed by patterning the surface to be treated 20a.
Specifically, the size of each opening O, the shape of each opening O, and the arrangement of the plurality of openings O are not limited to the above, and may be adjusted according to the deposition or etching requirements required for the patterning process.
It should be noted that the patterned deposition or patterned etching occurs in a region of the surface 20a to be treated smaller than the size of the opening O; alternatively, the dimensions of the patterned features (e.g., the dimensions of the line widths formed by patterned deposition, or the dimensions of the openings formed by patterned etching) formed on the surface 20a to be treated have smaller dimensions than the openings O. Thus, the overall size of the opening O is slightly larger than the size of the deposition to be patterned or the size of the etch to be patterned. In practical application, the width W of the opening O of the excitation electrode 12 is appropriately adjusted according to the required line width requirement for matching.
In some embodiments, the patterning device 10 described above is used to fabricate poly-finger structures for TOPcon solar cells. The size of each opening O, the shape of each opening O, and the arrangement of the plurality of openings O may be determined according to the size of the grid line, the shape of the grid line, and the arrangement of the grid line of the TOPcon solar cell. Specifically, the size of each opening O is slightly larger than the size of the gate line. For example, each opening O has a width W of 1.0mm and the patterned deposited film has a line width of approximately 750 μm.
In some embodiments, the plurality of openings O are spaced apart, each opening O being a generally rectangular slit. The length of each opening O corresponds to the length of the gate line, and the width W of each opening O ranges from 0.1mm to 3.0mm (e.g., 0.1mm to 0.5mm, 0.5mm to 1.0mm, 1.0mm to 1.5mm, 1.5mm to 2.0mm, 2.0mm to 2.5mm, 2.5mm to 3mm, etc.).
In some embodiments, TOPcon solar cells used in the patterning device 10 are interdigitated back contact solar cells. The plurality of openings O are interdigitated.
In some embodiments, the plurality of openings O are laser machined, and the spacing between adjacent openings O does not affect a stable uniform discharge.
In some embodiments, the material of the excitation electrode 12 and the ground electrode 11 are both metal. The material of the excitation electrode 12 and the ground electrode 11 may be, for example, but not limited to, aluminum.
It should be noted that the surface 20a to be treated of the sample 20 illustrated in fig. 1 is a flat surface, but is not limited thereto.
In other embodiments, the surface 20a of the sample 20 to be treated may be a rugged surface. In particular, the sample 20 may be crystalline silicon or a semiconductor substrate with a stack of film layers.
The second aspect of the application provides a patterning method. The patterning method includes the following steps S11 to S14. The order of certain steps or sub-steps of the patterning process may be changed, and certain steps or sub-steps may be omitted or combined, as desired.
Steps S11 to S14 are specifically described below in conjunction with the structure of the apparatus for patterning in fig. 1.
Step S11: a patterning device is provided.
In some embodiments, the patterning device 10 is a PECVD device. The PECVD device adopts a capacitive coupling discharge mode of parallel electrode plates. The patterning process is used to pattern deposit the surface 20a of the sample 20 to be treated. For example, patterned plasmas formed by maskless are used in the fabrication of poly-finger structures for TOPCon solar cells to effectively avoid the use of laser grooving and masking, but are not limited thereto.
In other embodiments, the patterning device 10 is a plasma etching device. The patterning process is used to pattern the surface 20a to be processed.
Step S12: the sample is placed on a grounded electrode.
Specifically, the surface 20a of the sample 20 to be treated is directed toward the excitation electrode 12. The surface of the sample 20 opposite to the surface 20a to be treated is in direct contact with the ground electrode 11.
In some embodiments, the patterning process is used to pattern the surface 20a to be processed of the sample 20, and the sample 20 may be a silicon substrate 30 for preparing a solar cell, but is not limited thereto.
In other embodiments, the patterning process is used to pattern the surface 20a of the sample 20 to be treated.
Step S13: and inputting gas into the uniform gas cavity.
In some embodiments, the patterning process is used to pattern deposit the surface 20a of the sample 20 to be treated, and the gas is a reactive gas used for the patterning deposition.
In other embodiments, the patterning process is used to pattern the surface 20a of the sample 20 to be processed, and the gas is an etching gas used for the patterning process.
Step S14: a voltage is applied to the excitation electrode by a power supply to excite the gas in the gas homogenizing cavity to generate plasma. The exciting electrode is arranged so that the distance between the outer surface of the bottom plate and the surface to be treated of the sample is less than or equal to 1mm, so that plasma selectively passes through the openings, and further, patterned plasma corresponding to the patterns of the openings is formed on the surface to be treated, so that patterning treatment of the surface to be treated is realized.
The third aspect of the application provides a method for manufacturing a solar cell. The preparation method of the solar cell comprises the following steps S21 to S22. The order of certain steps or sub-steps of the patterning process may be changed, and certain steps or sub-steps may be omitted or combined, as desired. In particular, the method for preparing the solar cell can be used for preparing a poly-finger structure of TOPCon solar cell.
Step S21: a silicon substrate is provided.
Step S22: with the patterning process of the second aspect of the present application, a partially passivated contact structure comprised of a passivation layer/doped polysilicon layer is patterned deposited on a silicon substrate.
With the increasing efficiency of TOPCon solar cells, recombination losses due to front-side contact have become a major limiting factor in efficiency. To reduce front-end recombination losses, one common approach is to fabricate a Selective Emitter (SE) structure on the front side. First, the SE structure reduces carrier recombination at the emitter region and improves surface passivation. Second, the SE structure reduces the contact resistivity (ρ c), thereby increasing the Fill Factor (FF). The laser SE technology currently used can only raise the open circuit voltage Voc by about 5mV to 8mV, and the recombination of the metal regions is still as high as 600fA/cm 2 to 1000fA/cm 2. The degree of recombination of the laser SE region electrodes is still too high compared to the rear SiOx/poly-Si. Therefore, the most advanced laser SE technology is not sufficient to further increase the efficiency of TOPCon solar cells, making front-end recombination a limiting factor for efficiency improvement.
In some embodiments, the passivation layer in the local passivation contact structure is made of SiOx, and the application of the SiOx/poly-Si (polysilicon) structure can effectively isolate the direct contact between the metal electrode and the crystalline silicon (c-Si), so that carrier recombination is significantly reduced. The SiOx/poly-Si is used as the SE structure, so that the defects of a laser SE technology can be overcome, the direct contact between c-Si and a metal electrode can be avoided, the saturation current density (J 0) is greatly reduced, and the short-circuit current density (J SC) and the open-circuit voltage Voc are improved. The SiOx/poly-Si structure is capable of selectively collecting carriers, reducing electron-hole recombination rate, and extending effective minority carrier lifetime (τ eff). Meanwhile, the high-temperature annealing process in the preparation process of the polysilicon is compatible with the high-temperature process of screen printing.
In some embodiments, the method of manufacturing a solar cell described above is used to manufacture a solar cell 10a as shown in fig. 2.
Specifically, the solar cell 10a includes an n-type silicon wafer 31. The n-type silicon wafer 31 includes opposite front and back surfaces 31a and 31b. The p/n junction is located on the side of the front face 31a of the solar cell 30 a. The solar cell 10a further includes an emitter layer 32 on the front surface 31a, a partially passivated contact structure T composed of a passivation layer 341/doped polysilicon layer 351 stacked on the emitter layer 32, a back passivation layer 342, a back doped polysilicon layer 352 and a back passivation anti-reflection layer 362 sequentially stacked on the back surface 31b, a front gate line 371 on the partially passivated contact structure T, and a back gate line 372 passing through the back passivation anti-reflection layer 362 and directly contacting the back doped polysilicon layer 352.
The following describes the steps S21 and S22 in detail with reference to the structure of the solar cell 30a shown in fig. 2.
Step S21: a silicon substrate is provided.
In this embodiment, step S21 specifically includes providing an n-type silicon wafer 31, and depositing an emitter layer 32 on the front surface 31a of the n-type silicon wafer 31.
In this embodiment, the emitter layer 32 is a boron doped emitter layer, which may be deposited in a conventional manner using the patterning device 10 described above, but is not limited thereto.
Specifically, in the step of depositing the emitter layer 32, the boron source may be PECVD deposited by using a mixed gas of 2% borane and 98% hydrogen, together with hydrogen and silane.
Step S22: with the patterning process of the second aspect of the present application, a partially passivated contact structure comprised of a passivation layer/doped polysilicon layer is patterned deposited on a silicon substrate.
In this embodiment, a partially passivated contact structure T is patterned and deposited on the emitter layer 32, the passivation layer 341 is made of SiOx, and the doped polysilicon layer 351 (i.e., poly-finger) is a p-type polysilicon layer.
In this embodiment, after step S22, the method for manufacturing a solar cell further includes the following steps S23 to S25.
Step S23: and depositing a front passivation anti-reflection layer on the front surface.
Specifically, the front passivation anti-reflection layer 361 may be deposited in a conventional manner using the patterning device 10 described above, but is not limited thereto.
Step S24: and sequentially depositing a back passivation layer, a back doped polysilicon layer and a back passivation anti-reflection layer on the back, wherein the back doped polysilicon layer is an n-type polysilicon layer.
Specifically, the backside passivation layer 342, the backside doped polysilicon layer 352, and the backside passivation anti-reflection layer 362 may be deposited in a conventional manner of the patterning device 10 described above, but is not limited thereto. The material of the back passivation layer 342 is, for example, siOx, and the back doped polysilicon layer 352 is, for example, phosphorus doped polysilicon, but is not limited thereto.
Step S25: forming a plurality of front grid lines on one side of the front surface of the n-type silicon wafer and a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein the front grid lines are in direct contact with the doped polysilicon layer, and the back grid lines penetrate through the back passivation anti-reflection layer and are in direct contact with the back doped polysilicon layer.
Specifically, the front gate line 371 and the back gate line 372 may each be formed by screen printing, but is not limited thereto.
In some embodiments, the method of manufacturing a solar cell described above is used to manufacture a solar cell 30b as shown in fig. 3.
Specifically, the solar cell 30b includes an n-type silicon wafer 31. The n-type silicon wafer 31 includes opposite front and back surfaces 31a and 31b. The solar cell 30b further includes a local passivation contact structure T composed of a passivation layer 341/a doped polysilicon layer 351 at the front surface 31a, a back passivation layer 342, a back doped polysilicon layer 352 and a back passivation anti-reflection layer 362 sequentially stacked on the back surface 31b, a front gate line 371 on the local passivation contact structure T, and a back gate line 372 passing through the back passivation anti-reflection layer 362 and directly contacting the back doped polysilicon layer 352.
The following describes the steps S21 and S22 in detail with reference to the structure of the solar cell 30b shown in fig. 3.
Step S21: a silicon substrate is provided.
In this embodiment, the silicon substrate 30 is provided as an n-type silicon wafer 31.
Step S22: with the patterning process of the second aspect of the present application, a partially passivated contact structure comprised of a passivation layer/doped polysilicon layer is patterned deposited on a silicon substrate.
In this embodiment, the partially passivated contact structure T is patterned and deposited on the front surface 31a of the n-type silicon wafer 31, the passivation layer 341 is made of SiOx, and the doped polysilicon layer 351 is an n-type polysilicon layer.
In this embodiment, after step S22, the method for manufacturing a solar cell further includes the following steps S23 to S25.
Step S23: and depositing a front passivation anti-reflection layer on the front surface.
Specifically, the front passivation anti-reflection layer 361 may be deposited in a conventional manner using the patterning device 10 described above, but is not limited thereto.
Step S24: and sequentially depositing a back passivation layer, a back doped polysilicon layer and a back passivation anti-reflection layer on the back, wherein the back doped polysilicon layer is a p-type polysilicon layer.
Specifically, the backside passivation layer 342, the backside doped polysilicon layer 352, and the backside passivation anti-reflection layer 362 may be deposited in a conventional manner of the patterning device 10 described above, but is not limited thereto. The material of the back passivation layer 342 is, for example, siOx, and the back doped polysilicon layer 352 is, for example, boron doped polysilicon, but is not limited thereto.
Step S25: forming a plurality of front grid lines on one side of the front surface of the n-type silicon wafer and a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein the front grid lines are in direct contact with the doped polysilicon layer, and the back grid lines penetrate through the back passivation anti-reflection layer and are in direct contact with the back doped polysilicon layer.
Specifically, the front gate line 371 and the back gate line 372 may each be formed by screen printing, but is not limited thereto.
In some embodiments, the method of manufacturing a solar cell described above is used to manufacture a solar cell 30c as shown in fig. 4.
Specifically, the solar cell 30c includes an n-type silicon wafer 31. The n-type silicon wafer 31 includes opposite front and back surfaces 31a and 31b. The solar cell 30c further includes a shallow diffusion front field region 33 and a front passivation anti-reflection layer 361 laminated in this order on the front surface 31a, a local passivation contact structure T composed of a passivation layer 341/a doped polysilicon layer 351 on the back surface 31b, a back passivation anti-reflection layer 362, and a back gate line 372 on the side where the back surface 31b of the n-type silicon wafer 31 is located. The passivation layer 341 is interdigitated. The doped polysilicon layer 351 includes an N-type polysilicon layer 352N and a P-type polysilicon layer 352P. The N-type polysilicon layer 352N and the P-type polysilicon layer 352P are alternately arranged in an interdigitated manner at intervals. A portion of the back gate line 372 is in direct contact with the N-type polysilicon layer 352N through the back passivation anti-reflection layer 362, and another portion of the back gate line 372 is in direct contact with the P-type polysilicon layer 352P through the back passivation anti-reflection layer 362.
The above-described steps S21 and S22 will be specifically described below with reference to the solar cell 30c shown in fig. 4.
Step S21: a silicon substrate is provided.
In this embodiment, providing the silicon substrate 30 includes providing an n-type silicon wafer 31, and sequentially depositing a shallow diffusion front field region 33 and a front passivation anti-reflection layer 361 on the front surface 31 a.
Specifically, the shallow diffusion front field region 33 and the front passivation anti-reflection layer 361 may be deposited using the conventional manner of the patterning device 10 described above, but is not limited thereto.
Step S22: with the patterning process of the second aspect of the present application, a partially passivated contact structure comprised of a passivation layer/doped polysilicon layer is patterned deposited on a silicon substrate.
In this embodiment, step S22 includes pattern depositing a passivation layer 341 on the back surface 31b, the passivation layer 341 being interdigitated. A doped polysilicon layer 352 is then pattern deposited over the passivation layer 341. The patterned deposition of the doped polysilicon layer 352 includes sequentially patterned deposition of an N-type polysilicon layer 352N and a P-type polysilicon layer 352P. The N-type polysilicon layer 352N and the P-type polysilicon layer 352P are alternately arranged in an interdigitated manner at intervals.
In this embodiment, after step S22, the method for manufacturing a solar cell further includes the following steps S23 to S24.
Step S23: a backside passivation anti-reflection layer is deposited on one side of the backside.
Specifically, the backside passivation anti-reflection layer 362 may be deposited in a conventional manner of the patterning device 10 described above, but is not limited thereto.
Step S24: and forming a plurality of back grid lines on one side of the back of the n-type silicon wafer, wherein part of the back grid lines are in direct contact with the n-type polysilicon layer through the back passivation anti-reflection layer, and the other part of the back grid lines are in direct contact with the p-type polysilicon layer through the back passivation anti-reflection layer.
Specifically, the back gate line 372 may be formed by screen printing, but is not limited thereto.
In summary, the apparatus for patterning of the first aspect of the application and the method of patterning of the second aspect allow for non-contact and maskless plasma-enhanced chemical vapor deposition or etching by the principle that when an excitation electrode having a plurality of openings is placed very close to the surface to be treated of the sample, the plasma is selectively excited within the openings due to the hollow cathode effect, so that deposition or etching only occurs in areas smaller than the size of the openings. Thus, when the above-described apparatus for patterning is used for manufacturing a solar cell, a patterned plasma corresponding to the position of a gate line of the solar cell can be formed by setting the size and shape of the plurality of openings. Furthermore, the width of the deposited or etched patterned poly-finger may be controlled by adjusting the size of the plurality of openings. In addition, the desired SiOx/poly-Si, passivation anti-reflection layer, etc. are deposited by adjusting the parameters of the above-described means for patterning during deposition, including but not limited to gas pressure, gas flow, gas species, gas ratio, distance of the actuation electrode from the silicon substrate.
The above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present application.
Claims (10)
1. A kind of pattern processing device, characterized by comprising the following steps:
A ground electrode for receiving a sample;
an excitation electrode positioned on one side of the ground electrode for receiving the sample, the excitation electrode comprising a gas-homogenizing cavity for receiving a gas, the gas-homogenizing cavity comprising a floor facing the ground electrode, the floor having opposite inner and outer surfaces, the outer surface being closer to the ground electrode than the inner surface, the floor defining a plurality of openings therethrough; and
The power supply is electrically connected with the excitation electrode so as to apply voltage to the excitation electrode to excite the gas in the uniform gas cavity to generate plasma;
Wherein the excitation electrode is disposed such that a distance from the outer surface of the base plate to a surface to be treated of the sample is 1mm or less, such that the plasma is selectively passed at positions of the plurality of openings, thereby forming patterned plasma corresponding to a pattern of the plurality of openings on the surface to be treated, to effect patterning of the surface to be treated.
2. The patterning device of claim 1, wherein,
The width of each of the openings ranges from 0.1mm to 3.0mm.
3. The patterning device according to claim 1 or 2, wherein,
The openings are a plurality of strip-shaped holes which are distributed at intervals, or the openings are distributed in an interdigital mode.
4. A method for processing a pattern, which comprises the steps of, characterized by comprising the following steps:
Providing a patterning device, wherein the patterning device comprises a grounding electrode, an excitation electrode and a power supply, the grounding electrode is used for receiving a sample, the excitation electrode is positioned on one side of the grounding electrode, which is used for receiving the sample, the excitation electrode comprises a uniform air cavity, which is used for receiving air, the uniform air cavity comprises a bottom plate facing the grounding electrode, the bottom plate is provided with an inner surface and an outer surface which are opposite, the outer surface is closer to the grounding electrode than the inner surface, the bottom plate is provided with a plurality of openings penetrating through the inner surface and the outer surface, and the power supply is electrically connected with the excitation electrode;
Placing a sample on the ground electrode;
inputting gas into the uniform gas cavity; and
Applying a voltage to the excitation electrode through the power supply to excite the gas in the uniform gas cavity to generate plasma;
Wherein the excitation electrode is disposed such that a distance from the outer surface of the base plate to a surface to be treated of the sample is 1mm or less, such that the plasma is selectively passed at positions of the plurality of openings, thereby forming patterned plasma corresponding to a pattern of the plurality of openings on the surface to be treated, to effect patterning of the surface to be treated.
5. The patterning process of claim 4, wherein,
The patterning of the surface to be treated comprises: and carrying out patterned deposition on the surface to be treated by the patterned plasma or carrying out patterned etching on the surface to be treated by the patterned plasma.
6. A method of manufacturing a solar cell, comprising:
Providing a silicon substrate; and
A passivation layer and a doped polysilicon layer are sequentially patterned deposited on the silicon substrate by the patterning plasma using the patterning process of claim 4 to form a partially passivated contact structure comprised of the passivation layer and the doped polysilicon layer.
7. The method of manufacturing a solar cell according to claim 6, wherein,
Providing the silicon substrate includes:
providing an n-type silicon wafer, wherein the n-type silicon wafer comprises a front surface and a back surface which are opposite; and
Depositing an emitter layer on the front surface;
The passivation layer is deposited on the emitter layer in a patterning way, and the doped polysilicon layer is a p-type polysilicon layer;
After the local passivation contact structure is formed, the preparation method of the solar cell further comprises the following steps:
depositing a front passivation anti-reflection layer on the front surface;
sequentially depositing a back passivation layer, a back doped polysilicon layer and a back passivation anti-reflection layer on the back, wherein the back doped polysilicon layer is an n-type polysilicon layer; and
Forming a plurality of front grid lines on one side of the front surface of the n-type silicon wafer and a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein the front grid lines are in direct contact with the doped polysilicon layer, and the back grid lines penetrate through the back passivation anti-reflection layer and are in direct contact with the back doped polysilicon layer.
8. The method of manufacturing a solar cell according to claim 6, wherein,
Providing the silicon substrate includes: providing an n-type silicon wafer, wherein the n-type silicon wafer comprises a front surface and a back surface which are opposite;
the passivation layer is deposited on the front surface in a patterning way, and the doped polysilicon layer is an n-type polysilicon layer;
After the local passivation contact structure is formed, the preparation method of the solar cell further comprises the following steps:
depositing a front passivation anti-reflection layer on the front surface;
Sequentially depositing a back passivation layer, a back doped polysilicon layer and a back passivation anti-reflection layer on the back, wherein the back doped polysilicon layer is a p-type polysilicon layer; and
Forming a plurality of front grid lines on one side of the front surface of the n-type silicon wafer and a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein the front grid lines are in direct contact with the doped polysilicon layer, and the back grid lines penetrate through the back passivation anti-reflection layer and are in direct contact with the back doped polysilicon layer.
9. The method of manufacturing a solar cell according to claim 6, wherein,
Providing the silicon substrate includes:
providing an n-type silicon wafer, wherein the n-type silicon wafer comprises a front surface and a back surface which are opposite; and
Sequentially depositing a shallow diffusion front field region and a front passivation anti-reflection layer on the front surface;
The passivation layer is deposited on the back surface in a patterning way, and the passivation layer is interdigital; the step of patterning and depositing the doped polysilicon layer comprises the step of sequentially patterning and depositing an n-type polysilicon layer and a p-type polysilicon layer on the passivation layer, wherein the n-type polysilicon layer and the p-type polysilicon layer are alternately arranged at intervals in an interdigital mode;
After the local passivation contact structure is formed, the preparation method of the solar cell further comprises the following steps:
depositing a back passivation anti-reflection layer on one side of the back surface; and
Forming a plurality of back grid lines on one side of the back surface of the n-type silicon wafer, wherein part of the back grid lines penetrate through the back passivation anti-reflection layer to be in direct contact with the n-type polysilicon layer, and the other part of the back grid lines penetrate through the back passivation anti-reflection layer to be in direct contact with the p-type polysilicon layer.
10. The method for producing a solar cell according to any one of claim 7 to 9, wherein,
The front passivation anti-reflection layer and/or the back passivation anti-reflection layer are deposited by arranging the excitation electrode such that the distance of the outer surface of the base plate from the surface to be treated of the sample is greater than 1 mm.
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