CN118801871A - A switch circuit - Google Patents

Abstract

The present application discloses a switch circuit, which is applied to the field of power supply technology, including: a first NMOS switch tube, whose drain is connected to the source of a second NMOS switch tube, and the connection end is used as the output end of the switch circuit, whose source is grounded, and the gate is connected to a first control signal; a second NMOS switch tube, whose drain is connected to a high-voltage power supply, and the gate is connected to a second control signal; a first end of a capacitor is connected to a drain of a PMOS switch tube and a high-voltage power supply port of a first level conversion circuit, and a second end is connected to the output end of the switch circuit; a PMOS switch tube, whose source is connected to a low-voltage power supply, and the gate is connected to a third control signal; when the external signal is a low-voltage power supply voltage, the second control signal output by the first level conversion circuit is the first terminal voltage of the capacitor; when the external signal is a ground voltage, the second control signal is a ground voltage. The application of the scheme of the present application is conducive to reducing the occupied area of the switch circuit without affecting the response speed of the switch.

Description

A switch circuit

Technical Field

The present invention relates to the technical field of power supply, and in particular to a switch circuit.

Background Art

Please refer to FIG1 , which is a schematic diagram of the structure of a commonly used switch circuit, which is a circuit structure of a PMOS switch tube + an NMOS switch tube. In FIG1 , the output level of VOUT can be switched by alternately conducting MP1 and MN1.

In high voltage situations, for a solution like FIG1, the chip area is relatively large. This is because in high voltage situations, in order to ensure a faster response speed, the MOS tube needs to have a large width-to-length ratio, so that the MOS tube occupies a large area. In addition, since the majority carriers of the PMOS switch tube are holes, and the majority carriers of the NMOS switch tube are electrons, the mobility of electrons is 2 to 3 times higher than that of holes. Therefore, under the same area, the on-resistance of the PMOS switch tube is 2 to 3 times higher than that of the NMOS switch tube. In other words, the area of the PMOS chip with the same on-resistance will be 2 to 3 times that of the NMOS chip. Therefore, in high voltage situations, for a solution like FIG1, especially MP1 in FIG1, a large chip area will be occupied.

In summary, how to effectively reduce the occupied area of a high-power switch circuit without affecting the response speed of the switch is a technical problem that those skilled in the art urgently need to solve.

Summary of the invention

The object of the present invention is to provide a switch circuit to effectively reduce the occupied area of a high-power switch circuit without affecting the response speed of the switch.

In order to solve the above technical problems, the present invention provides the following technical solutions:

In a first aspect, the present invention provides a switch circuit, comprising: a first NMOS switch tube, a second NMOS switch tube, a first level conversion circuit, a capacitor, and a PMOS switch tube;

The source of the PMOS switch tube is connected to a low voltage power supply, and the gate of the PMOS switch tube is connected to a third control signal;

The first end of the capacitor is connected to the drain of the PMOS switch tube, and the second end of the capacitor is connected to the output end of the switch circuit;

The drain of the first NMOS switch tube is connected to the source of the second NMOS switch tube, and the connection end serves as the output end of the switch circuit, the source of the first NMOS switch tube is grounded, and the gate of the first NMOS switch tube is connected to the first control signal;

The drain of the second NMOS switch tube is connected to a high voltage power supply, and the gate of the second NMOS switch tube is connected to a second control signal;

The high-voltage power supply port of the first level conversion circuit is connected to the first end of the capacitor, the first ground port of the first level conversion circuit is connected to the second end of the capacitor, the low-voltage power supply port of the first level conversion circuit is connected to the low-voltage power supply, the second ground port of the first level conversion circuit is connected to the ground voltage, the input port of the first level conversion circuit is connected to an external signal, and the output port of the first level conversion circuit is connected to the second control signal; the first level conversion circuit is used for outputting the second control signal as the first end voltage of the capacitor when the external signal is the low-voltage power supply voltage; and outputting the second control signal as the ground voltage when the external signal is the ground voltage;

The on and off states of the PMOS switch tube and the second NMOS switch tube are opposite, and the on and off states of the first NMOS switch tube and the second NMOS switch tube are opposite, so that the voltage at the output end of the switch circuit is the high voltage power supply voltage or the ground voltage.

In one embodiment, when the second control signal is 0v, the first control signal is the voltage of the low-voltage power supply, and the third control signal is 0v;

When the second control signal is a voltage higher than the high voltage power supply, the first control signal is 0 V, and the third control signal is a voltage higher than the high voltage power supply.

In one embodiment, the switch circuit further includes: a single-turn dual circuit and a drive circuit;

The input end of the single-to-dual circuit is connected to a switch control signal, the first output end of the single-to-dual circuit outputs a first switch signal, and the second output end of the single-to-dual circuit outputs a second switch signal; the first switch signal is in the opposite direction of the switch control signal, and the second switch signal is in the same direction as the switch control signal; the power port of the single-to-dual circuit is connected to the low-voltage power supply, and the ground port of the single-to-dual circuit is grounded;

The input terminal of the driving circuit is connected to the first switch signal, the output terminal of the driving circuit outputs the first control signal, the power port of the driving circuit is connected to the low-voltage power supply, and the ground port of the driving circuit is grounded;

The second switch signal is connected to an input terminal of the first level conversion circuit as the external signal.

In one implementation, the second control signal and the third control signal are connected together.

In one implementation, the switch circuit further includes: a second level conversion circuit;

The input end of the second level conversion circuit is connected to the second switch signal, the output end of the second level conversion circuit outputs the third control signal, the high-voltage power supply port of the second level conversion circuit is respectively connected to the first end of the capacitor and the drain of the PMOS switch tube, and the low-voltage power supply port of the second level conversion circuit is connected to the low-voltage power supply; the first ground port of the second level conversion circuit is connected to the source of the second NMOS switch tube, and the second ground port of the second level conversion circuit is grounded.

In one implementation, the second level conversion circuit is completely identical to the first level conversion circuit.

In one embodiment, the single-to-dual circuit includes: switching a first NMOS switch tube, switching a second NMOS switch tube, switching a first PMOS switch tube, and switching a second PMOS switch tube;

The drain of the first NMOS switch tube, the source of the first PMOS switch tube, the gate of the second PMOS switch tube, and the gate of the second NMOS switch tube are connected to each other, and the connection end serves as the input end of the single-to-dual circuit;

The source of the first NMOS switch tube is connected to the drain of the first PMOS switch tube, and the connection end serves as the second output end of the single-to-dual circuit to output the second switch signal, and the gate of the first PMOS switch tube is connected to the ground port of the single-to-dual circuit;

The gate of the first NMOS switch tube is connected to the source of the second PMOS switch tube and the connection terminal is connected to the power port of the single-to-dual circuit;

The drain of the second NMOS switch tube is connected to the drain of the second PMOS switch tube, and the connection end serves as the first output end of the single-to-dual circuit to output the first switching signal, and the source of the second NMOS switch tube is connected to the ground port of the single-to-dual circuit.

In one embodiment, the driving circuit includes: driving a first NMOS switch tube, driving a second NMOS switch tube, driving a first PMOS switch tube, and driving a second PMOS switch tube;

The gate of the first NMOS switch tube is connected to the gate of the first PMOS switch tube, and the connection end serves as the input end of the driving circuit;

The source electrode of the first NMOS switch tube is connected to the source electrode of the second NMOS switch tube, and the connection terminal is connected to the ground port of the driving circuit; the source electrode of the first PMOS switch tube is connected to the source electrode of the second PMOS switch tube, and the connection terminal is connected to the power port of the driving circuit;

The drain of the first NMOS switch tube, the drain of the first PMOS switch tube, the gate of the second NMOS switch tube, and the gate of the second PMOS switch tube are connected to each other;

The drain electrode of the second NMOS switch tube is connected to the drain electrode of the second PMOS switch tube, and the connection end serves as the output end of the driving circuit.

In one embodiment, the first level conversion circuit includes: an input inverter, a third NMOS switch tube, a fourth NMOS switch tube, a fifth NMOS switch tube, a sixth NMOS switch tube, a seventh NMOS switch tube, an eighth NMOS switch tube, a first PMOS switch tube, a second PMOS switch tube, a third PMOS switch tube, a fourth PMOS switch tube, a fifth PMOS switch tube, a sixth PMOS switch tube, and a seventh PMOS switch tube;

The input end of the input inverter is connected to the gate of the fourth NMOS switch tube and the connection end serves as the input end of the first level conversion circuit; the output end of the input inverter is connected to the gate of the third NMOS switch tube; the power supply end of the input inverter is connected to the low-voltage power supply port of the second level conversion circuit; the ground end of the input inverter, the source of the third NMOS switch tube and the source of the fourth NMOS switch tube are all connected to the second ground port of the second level conversion circuit;

The drain of the fourth NMOS switch tube is connected to the drain of the fourth PMOS switch tube, and the drain of the third NMOS switch tube is connected to the drain of the third PMOS switch tube;

The gate of the third PMOS switch tube, the gate of the fourth PMOS switch tube, the source of the fifth NMOS switch tube, the source of the sixth NMOS switch tube, the source of the seventh NMOS switch tube and the source of the eighth NMOS switch tube are connected to each other and connected to the first ground port of the first level conversion circuit;

The source of the first PMOS switch tube, the source of the second PMOS switch tube, the source of the fifth PMOS switch tube, the source of the sixth PMOS switch tube and the source of the seventh PMOS switch tube are connected to each other and connected to the high-voltage power supply port of the first level conversion circuit;

The gate of the first PMOS switch tube, the source of the fourth PMOS switch tube, the drain of the fifth NMOS switch tube, the gate of the sixth NMOS switch tube and the gate of the fifth PMOS switch tube are connected to each other;

The gate of the second PMOS switch tube is respectively connected to the source of the third PMOS switch tube and the drain of the first PMOS switch tube;

The drain of the sixth NMOS switch tube, the gate of the seventh NMOS switch tube, the drain of the fifth PMOS switch tube and the gate of the sixth PMOS switch tube are connected to each other;

The drain of the sixth PMOS switch tube, the gate of the seventh PMOS switch tube, the drain of the seventh NMOS switch tube and the gate of the eighth NMOS switch tube are connected to each other;

The drain of the seventh NMOS switch tube is connected to the drain of the eighth NMOS switch tube, and the connection end serves as the output end of the first level conversion circuit.

In one embodiment, the voltage of the high voltage power supply is 60V, the voltage of the low voltage power supply is 5V; the width-to-length ratio of the second NMOS switch tube is greater than 10000, the width-to-length ratio of the first NMOS switch tube is greater than 1000, and the width-to-length ratio of any other MOS tube is less than 100.

By applying the technical solution provided in the embodiment of the present invention, an NMOS circuit structure is used on both the high-voltage side and the low-voltage side, that is, the present application solution uses a circuit structure of a first NMOS switch tube + a second NMOS switch tube to realize the required switching circuit.

Specifically, in the switching circuit of the present application, the MOSFETs on the high-voltage side and the low-voltage side are both NMOS, that is, the first NMOS switch tube and the second NMOS switch tube. In order to enable the circuit to work, the present application scheme introduces capacitors and PMOS switch tubes to act as bootstrap circuits, and through the first level conversion circuit, high voltage can be applied to the second NMOS switch tube to ensure the conduction of the second NMOS switch tube. Specifically, the drain of the second NMOS switch tube is connected to the high voltage power supply, and the gate of the second NMOS switch tube is connected to the second control signal; the first end of the capacitor is connected to the drain of the PMOS switch tube, and the second end of the capacitor is connected to the output end of the switch circuit; the source of the PMOS switch tube is connected to the low voltage power supply, and the gate of the PMOS switch tube is connected to the third control signal; the drain of the first NMOS switch tube is connected to the source of the second NMOS switch tube, and the connection end serves as the output end of the switch circuit, the source of the first NMOS switch tube is grounded, and the gate of the first NMOS switch tube is connected to the first control signal, the high voltage power supply port of the first level conversion circuit is connected to the first end of the capacitor, the first ground port of the first level conversion circuit is connected to the second end of the capacitor, the low voltage power supply port of the first level conversion circuit is connected to the low voltage power supply, the second ground port of the first level conversion circuit is connected to the ground voltage, the input port of the first level conversion circuit is connected to an external signal, and the output port of the first level conversion circuit is connected to the second control signal; the first level conversion circuit is used for, when the external signal is the low voltage power supply voltage, the output second control signal is the first terminal voltage of the capacitor; when the external signal is the ground voltage, the output second control signal is the ground voltage. The on and off states of the PMOS switch tube and the second NMOS switch tube are opposite, and the on and off states of the first NMOS switch tube and the second NMOS switch tube are opposite, so that the voltage at the output end of the switch circuit is the high voltage power supply voltage or the ground voltage.

It can be seen from the circuit structure that when the first NMOS switch tube is turned on and the switch circuit outputs the ground voltage, the second NMOS switch tube is turned off, and the low-voltage power supply can charge the capacitor through the PMOS switch tube. When the second NMOS switch tube is turned on, since the voltage across the capacitor cannot change suddenly, at this time, the voltage of the capacitor to the ground will rise to (the voltage of the low-voltage power supply + the voltage at the output end of the current switch circuit), and the voltage at the output end of the current switch circuit is equal to the voltage of the high-voltage power supply connected to the drain of the second NMOS switch tube, and the PMOS switch tube is turned off to achieve isolation between the high voltage of the capacitor and the low-voltage power supply at the source of the PMOS switch tube. It should be noted that when the second NMOS switch tube is turned on, its drain is connected to the voltage of the high-voltage power supply, so in order to ensure the conduction of the second NMOS switch tube, the gate of the second NMOS switch tube needs to apply a high voltage to ensure that the second NMOS switch tube has a certain gate-source voltage. In this regard, a first level conversion circuit is provided in the present application scheme. When the external signal of the first level conversion circuit is a low-voltage power supply voltage, the second control signal output by the first level conversion circuit can be the first terminal voltage of the capacitor, that is, the first terminal voltage of the capacitor is applied to the gate of the second NMOS switch tube at this time. There will always be a certain voltage difference between the gate and source of the second NMOS switch tube, which can ensure that the second NMOS switch tube is always turned on while its source voltage continues to increase.

It can be seen that in the present application, the voltage at the output end of the switch circuit is the high voltage power supply voltage or the ground voltage, which effectively realizes a switch circuit whose output level can switch between high and low voltage without affecting the response speed of the switch. In addition, both the high voltage side and the low voltage side use the NMOS circuit structure, which is conducive to reducing the occupied area of the switch circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the structure of a commonly used switch circuit;

FIG2 is a schematic diagram of the structure of a switch circuit provided in a specific embodiment of the present invention;

FIG3 is a schematic diagram of the structure of a switch circuit provided in another specific embodiment of the present invention;

FIG4 is a schematic structural diagram of a switch circuit provided in another specific embodiment of the present invention;

FIG5 is a schematic diagram of the structure of a single-conversion dual-circuit provided in a specific embodiment of the present invention;

FIG6 is a schematic diagram of the structure of a driving circuit provided in a specific embodiment of the present invention;

FIG. 7 is a schematic diagram of the structure of a first level conversion circuit provided in a specific embodiment of the present invention.

DETAILED DESCRIPTION

The core of the present invention is to provide a switch circuit, which is beneficial to reducing the occupied area of the switch circuit without affecting the response speed of the switch.

In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

Please refer to FIG. 2 , which is a schematic diagram of the structure of a switch circuit provided by a specific embodiment of the present invention. The switch circuit may include: a first NMOS switch tube MN1, a second NMOS switch tube MN2, a first level conversion circuit 20, a capacitor C1, and a PMOS switch tube Q1;

The source of the PMOS switch tube Q1 is connected to the low voltage power supply, and the gate of the PMOS switch tube Q1 is connected to the third control signal;

A first end of the capacitor C1 is connected to the drain of the PMOS switch tube Q1, and a second end of the capacitor C1 is connected to the output end of the switch circuit;

The drain of the first NMOS switch tube MN1 is connected to the source of the second NMOS switch tube MN2, and the connection end serves as the output end of the switch circuit. The source of the first NMOS switch tube MN1 is grounded, and the gate of the first NMOS switch tube MN1 is connected to the first control signal.

The drain of the second NMOS switch tube MN2 is connected to the high voltage power supply, and the gate of the second NMOS switch tube MN2 is connected to the second control signal;

The high-voltage power supply port of the first level conversion circuit 20 is connected to the first end of the capacitor C1, the first ground port of the first level conversion circuit 20 is connected to the second end of the capacitor C1, the low-voltage power supply port of the first level conversion circuit 20 is connected to the low-voltage power supply, the second ground port of the first level conversion circuit 20 is connected to the ground voltage, the input port of the first level conversion circuit 20 is connected to an external signal, and the output port of the first level conversion circuit 20 is connected to the second control signal; the first level conversion circuit 20 is used for outputting the second control signal as the first end voltage of the capacitor C1 when the external signal is the low-voltage power supply voltage; and the outputting the second control signal as the ground voltage when the external signal is the ground voltage;

The on and off states of the PMOS switch tube Q1 and the second NMOS switch tube MN2 are opposite, and the on and off states of the first NMOS switch tube MN1 and the second NMOS switch tube MN2 are opposite, so that the voltage at the output end of the switch circuit is a high voltage power supply voltage or a ground voltage.

Specifically, in the scheme of the present application, a switch circuit whose output level can be switched between high and low voltages is realized. It can be seen from the circuit structure that when the first NMOS switch tube MN1 is turned on, the output end of the switch circuit is grounded through the first NMOS switch tube MN1. At this time, the voltage at the output end of the switch circuit is 0V, that is, the voltage of the lower plate of the capacitor C1 is 0v. In Figure 2, the output end of the switch circuit is recorded as VOUT. In addition, when the first NMOS switch tube MN1 is turned on, the second control signal is the ground voltage, which makes the second NMOS switch tube MN2 turn off, and at this time the PMOS switch tube Q1 is turned on. At this time, the low-voltage power supply can charge the upper plate of the capacitor C1 through the PMOS switch tube Q1. In the scheme of the present application, the low-voltage power supply plays the function of charging the capacitor C1. The specific voltage level can be set and adjusted as needed. For example, it can usually be set to 5v. In Figure 2, the low-voltage power supply is recorded as VDD.

When the first NMOS switch tube MN1 is turned off, the second NMOS switch tube MN2 is turned on, and the PMOS switch tube Q1 is turned off. Since the second NMOS switch tube MN2 is turned on, the output of the switch circuit is a high level, which is specifically equal to the amplitude of the high voltage power supply. For example, the high voltage power supply can be set to 60v in this embodiment. In Figure 2, the high voltage power supply is recorded as HV. Therefore, in this example, the voltage at the output end VOUT of the switch circuit is 60v. In addition, since the voltage across the capacitor C1 cannot change suddenly, when the second NMOS switch tube MN2 is turned on, the voltage at the lower plate of the capacitor C1 will gradually increase to 60v, and the voltage at the upper plate of the capacitor C1 is equal to the voltage of the low voltage power supply + the voltage at the output end of the current switch circuit. In the above example, the PMOS switch tube Q1 is turned off, and the voltage at the upper plate of the capacitor C1 is equal to VDD+HV=5v+60v=65v.

In addition, the present application takes into account that when the second NMOS switch tube MN2 is turned on, since the drain of the second NMOS switch tube MN2 is connected to a high voltage power supply, to ensure the conduction of the second NMOS switch tube MN2, a higher voltage needs to be applied to the gate of the second NMOS switch tube MN2.

The present application considers that if the upper plate voltage of the capacitor C1 is used as the second control signal connected to the gate of the second NMOS switch tube MN2, there will always be a voltage difference of 5v between the gate source of the second NMOS switch tube MN2, which can ensure that the second NMOS switch tube MN2 is always turned on during the continuous increase of the VOUT voltage. In addition, when the second NMOS switch tube MN2 is turned off, the PMOS switch tube Q1 is turned on, because the voltage of the upper plate of the capacitor C1 is 65v and will not be backflowed to the low-voltage power supply VDD, thereby protecting the relevant reference circuit of the output VDD. In addition, when the PMOS switch tube Q1 is turned on, there is almost no conduction voltage drop, and no additional power consumption will be generated.

In this regard, the present application scheme provides a first level conversion circuit 20, the high voltage power port of the first level conversion circuit 20 is denoted as VB in FIG. 2 and is connected to the first end of the capacitor C1. The first ground port of the first level conversion circuit 20 is denoted as VS and is connected to the second end of the capacitor C1. The low voltage power port of the first level conversion circuit 20 is connected to the low voltage power supply VDD, for example, VDD is 5v in the above example. The second ground port of the first level conversion circuit 20 is connected to the ground voltage GND. The input port of the first level conversion circuit is connected to an external signal to play a control function, and the output port of the first level conversion circuit 20 is connected to the second control signal.

The gate of the first NMOS switch tube MN1 is connected to the first control signal, the gate of the second NMOS switch tube MN2 is connected to the second control signal, and the gate of the PMOS switch tube Q1 is connected to the third control signal. In Figure 2, the first control signal is recorded as LSG, the second control signal is recorded as HSG, and the third control signal is recorded as PG. It can be understood that the level state setting of LSG, HSG and PG should meet the functional requirements of this application, that is, the on-off state of the corresponding switch tube should conform to the above description.

Combined with the above description, it can be known that when the first NMOS switch tube MN1 is turned on, the lower plate voltage of the capacitor C1 is 0v, the PMOS switch tube Q1 is turned on, and the second NMOS switch tube MN2 is turned off. At this time, the external signal should be the ground voltage, so that the second control signal output by the first level conversion circuit 20 at this time is the ground voltage, that is, HSG in Figure 2 is equal to VS at this time, which is the ground voltage, that is, 0v.

Correspondingly, when the first NMOS switch tube MN1 is turned off, the second NMOS switch tube MN2 is turned on, and the PMOS switch tube Q1 is turned off. At this time, the external signal should be a low-voltage power supply voltage, and the second control signal HSG output by the first level conversion circuit 20 is the first terminal voltage of the capacitor C1, that is, HSG in FIG2 is equal to VB at this time, for example, 65v in the above example. And because HSG is maintained at 65v, there is always a voltage difference of 5v between the gate and source of the second NMOS switch tube MN2, which ensures that the second NMOS switch tube MN2 is always turned on during the continuous increase of the VOUT voltage.

In a specific embodiment of the present invention, when the second control signal is 0v, the first control signal is the voltage of the low voltage power supply, and the third control signal is 0v;

When the second control signal is a voltage higher than the high voltage power supply, the first control signal is 0V, and the third control signal is a voltage higher than the high voltage power supply.

This embodiment takes into account that the second control signal HSG can be set to 0v, at which time the second NMOS switch tube MN2 is turned off, and the first control signal LSG at this time can be the voltage VDD of the low-voltage power supply, so that the first NMOS switch tube MN1 is turned on, and the third control signal PG at this time can be 0V to turn on the PMOS switch tube Q1.

In this implementation, when the first control signal LSG is 0V, the first NMOS switch tube MN1 is turned off. At this time, the second control signal HSG can be set to a voltage higher than the high voltage power supply to ensure that the second NMOS switch tube MN2 is turned on. For example, in one occasion, the second control signal HSG is set to 65V. In addition, the third control signal PG can also be set to a voltage higher than the high voltage power supply, such as 50V, at which time the PMOS switch tube Q1 is turned off.

Referring to FIG. 3 , in a specific embodiment of the present invention, the switch circuit may further include: a single-turn dual circuit 10 and a drive circuit 30;

The input end of the single-to-dual circuit 10 is connected to the switch control signal, the first output end of the single-to-dual circuit 10 outputs the first switch signal, and the second output end of the single-to-dual circuit 10 outputs the second switch signal; the first switch signal is in the opposite direction to the switch control signal, and the second switch signal is in the same direction as the switch control signal; the power port of the single-to-dual circuit 10 is connected to the low-voltage power supply, and the ground port of the single-to-dual circuit 10 is grounded;

The input terminal of the driving circuit 30 is connected to the first switch signal, the output terminal of the driving circuit 30 outputs the first control signal, the power port of the driving circuit 30 is connected to the low-voltage power supply, and the ground port of the driving circuit 30 is grounded;

The second switch signal is connected to the input terminal of the first level conversion circuit 20 as the external signal.

This embodiment takes into account that in the present application, the on and off states of the first NMOS switch tube MN1 and the second NMOS switch tube MN2 are required to be opposite. Therefore, a single-turn dual circuit 10 can be set, the input end of the single-turn dual circuit 10 is connected to the switch control signal IN, and the first output end of the single-turn dual circuit 10 outputs the first switch signal INN, and the second output end of the single-turn dual circuit 10 outputs the second switch signal INP. The first switch signal INN is opposite to the switch control signal IN, and the second switch signal INP is in the same direction as the switch control signal IN. Therefore, the function of the single-turn dual circuit 10 is to output the first switch signal INN and the second switch signal INP which is opposite to the first switch signal INN based on the input switch control signal IN, so as to control the on and off of the first NMOS switch tube MN1 and the second NMOS switch tube MN2, and achieve the purpose of opposite on and off states of the first NMOS switch tube MN1 and the second NMOS switch tube MN2. It can be understood that, in this embodiment, the second switch signal INP, that is, the external signal connected to the input terminal of the first level conversion circuit 20 as described above, realizes the state control of the first level conversion circuit 20 .

In practical applications, IN is usually a periodic pulse signal, for example, a periodic pulse signal with a high level time of 1 ms and a low level time of 70 ms.

Furthermore, this embodiment takes into account that the width-to-length ratio of the first NMOS switch tube MN1 is large, and the current driving capability may not be sufficient if the first switch signal INN is used directly for driving, so a drive circuit 30 for improving the driving capability is provided. The input end of the drive circuit 30 is connected to the first switch signal INN, and the output end of the drive circuit 30 outputs the first control signal LSG. The drive circuit 30 needs to have a power port and a ground port. In this embodiment, the power port of the drive circuit 30 is connected to the low-voltage power supply VDD, and the ground port of the drive circuit 30 is connected to GND.

In FIG3 , the high-voltage power supply port of the first level conversion circuit 20 is also denoted as VB, the low-voltage power supply port is connected to the low-voltage power supply VDD, the first ground port of the first level conversion circuit 20 is denoted as VS, and the first ground port is specifically connected to the source of the second NMOS switch tube MN2, that is, connected to VOUT of FIG3 , and the second ground port of the first level conversion circuit 20 is connected to GND.

When the input INP of the first level conversion circuit 20 is at a high level (5v), the output HSG of the first level conversion circuit 20 may be equal to VB (65v), and when the input INP of the first level conversion circuit 20 is at a low level (0v), the output HSG of the first level conversion circuit 20 may be equal to VS (0v), that is, equal to VOUT.

In a specific implementation of the present invention, the second control signal and the third control signal are connected together.

As described above, in the present application, the on and off states of the PMOS switch tube Q1 and the second NMOS switch tube MN2 are opposite, so a relatively simple implementation is to directly connect the second control signal and the third control signal together. Please refer to Figure 3, which adopts this implementation. Since the second control signal and the third control signal are connected together, in Figure 3, the second control signal and the third control signal are directly recorded as HSG. At this time, the second control signal HSG outputted by the output end of the first level conversion circuit 20 is connected to both the gate of the second NMOS switch tube MN2 and the gate of the PMOS switch tube Q1.

In a specific implementation of the present invention, the second control signal and the third control signal are not connected together. Please refer to FIG. 4 . The switch circuit further includes: a second level conversion circuit 40 .

The input end of the second level conversion circuit 40 is connected to the second switch signal, the output end of the second level conversion circuit 40 outputs the third control signal, the high voltage power supply port of the second level conversion circuit 40 is respectively connected to the first end of the capacitor C1 and the drain of the PMOS switch tube Q1, and the low voltage power supply port of the second level conversion circuit 40 is connected to the low voltage power supply; the first ground port of the second level conversion circuit 40 is connected to the source of the second NMOS switch tube MN2, and the second ground port of the second level conversion circuit 40 is grounded.

Referring to FIG. 4 , in this embodiment, a second level conversion circuit 40 is provided, and in practical applications, in order to facilitate circuit structure design and reduce production and maintenance costs, the second level conversion circuit 40 can be completely identical to the first level conversion circuit 20 .

Similar to the first level conversion circuit 20, the high-voltage power supply port of the second level conversion circuit 40 in this embodiment can also be connected to VB, and the low-voltage power supply port can be connected to the low-voltage power supply VDD. The first ground port of the second level conversion circuit 40 can also be connected to the source of the second NMOS switch tube MN2, that is, connected to VOUT in Figure 4, and the second ground port of the second level conversion circuit 40 is connected to GND.

When the input INP of the second level conversion circuit 40 is at a high level, the third control signal PG output by the second level conversion circuit 40 is equal to VB, and when the input INP of the second level conversion circuit 40 is at a low level, the third control signal PG output by the second level conversion circuit 40 is equal to VOUT.

It should also be noted that in this embodiment, a second level conversion circuit 40 is provided. Compared with FIG. 3 , the circuit structure is more complicated, but it is helpful to speed up the conduction speed of the PMOS switch tube Q1, because the output end of the second level conversion circuit is connected to the gate of the PMOS switch tube Q1 and has nothing to do with the working state of the second NMOS switch tube MN2.

The specific structure of the single-to-dual circuit 10 can be set and adjusted according to actual needs. For example, in a specific embodiment of the present invention, referring to FIG. 5 , the single-to-dual circuit 10 can specifically include: a first NMOS switch tube Z-MN1, a second NMOS switch tube Z-MN2, a first PMOS switch tube Z-MP1, and a second PMOS switch tube Z-MP2;

The drain of the first NMOS switch tube Z-MN1, the source of the first PMOS switch tube Z-MP1, the gate of the second PMOS switch tube Z-MP2, and the gate of the second NMOS switch tube Z-MN2 are connected to each other, and the connection end serves as the input end of the single-to-dual circuit 10;

The source of the first NMOS switch tube Z-MN1 is connected to the drain of the first PMOS switch tube Z-MP1, and the connection end serves as the second output end of the single-to-dual circuit 10 to output the second switch signal INP, and the gate of the first PMOS switch tube Z-MP1 is connected to the ground port of the single-to-dual circuit 10;

The gate of the first NMOS switch tube Z-MN1 is connected to the source of the second PMOS switch tube Z-MP2 and the connection terminal is connected to the power port of the single-to-dual circuit 10;

The drain of the second NMOS switch tube Z-MN2 is connected to the drain of the second PMOS switch tube Z-MP2, and the connection end serves as the first output end of the single-to-dual circuit 10 to output the first switching signal INN, and the source of the second NMOS switch tube Z-MN2 is connected to the ground port of the single-to-dual circuit 10.

In this implementation, the required single-to-dual circuit 10 can be realized by four MOS switch tubes, namely, the first NMOS switch tube Z-MN1, the second NMOS switch tube Z-MN2, the first PMOS switch tube Z-MP1 and the second PMOS switch tube Z-MP2, with a simple structure and high reliability. In Figure 5, the ground port of the single-to-dual circuit 10 is connected to GND, and the power port is connected to VDD, for example, VDD is specifically 5v. In a specific implementation, when the input terminal IN of the single-to-dual circuit 10 is 0v, the first switch signal INN is 5v, and the second switch signal INP is 0v. Correspondingly, when the input terminal IN of the single-to-dual circuit 10 is 5v, the first switch signal INN is 0v, and the second switch signal INP is 5v.

The specific structure of the driving circuit 30 can be set and adjusted according to actual needs. For example, in a specific embodiment of the present invention, referring to FIG. 6 , the driving circuit 30 includes: driving a first NMOS switch tube Q-MN1, driving a second NMOS switch tube Q-MN2, driving a first PMOS switch tube Q-MP1, and driving a second PMOS switch tube Q-MP2;

The gate of the first NMOS switch tube Q-MN1 is connected to the gate of the first PMOS switch tube Q-MP1, and the connection end serves as the input end of the driving circuit 30;

The source of the first NMOS switch tube Q-MN1 is connected to the source of the second NMOS switch tube Q-MN2, and is connected to the ground port of the termination drive circuit 30; the source of the first PMOS switch tube Q-MP1 is connected to the source of the second PMOS switch tube Q-MP2, and is connected to the power port of the termination drive circuit 30;

The drain of the first NMOS switch tube Q-MN1 is driven, the drain of the first PMOS switch tube Q-MP1 is driven, the gate of the second NMOS switch tube Q-MN2 is driven, and the gate of the second PMOS switch tube Q-MP2 is driven to be connected to each other;

The drain of the second NMOS switch transistor Q- MN2 is connected to the drain of the second PMOS switch transistor Q- MP2 , and the connection end serves as the output end of the driving circuit 30 .

In this implementation, the required driving circuit 30 can be realized by driving four MOS switch tubes, namely, driving the first NMOS switch tube Q-MN1, driving the second NMOS switch tube Q-MN2, driving the first PMOS switch tube Q-MP1 and driving the second PMOS switch tube Q-MP2, with a simple structure and high reliability.

In Fig. 6, the ground port of the driving circuit 30 is connected to GND, and the power port is connected to VDD. In a specific implementation, when the input terminal INN of the driving circuit 30 is 0v, the first control signal LSG outputted by the output terminal of the driving circuit 30 is 0v, and correspondingly, when the input terminal INN of the driving circuit 30 is 5v, the first control signal LSG outputted by the output terminal of the driving circuit 30 is 5v, but the driving current increases step by step, and a larger load can be driven.

The specific structure of the first level conversion circuit 20 can be set and adjusted according to actual needs. For example, in a specific embodiment of the present invention, referring to FIG. 7 , the first level conversion circuit 20 includes: an input inverter INV, a third NMOS switch tube H-MN3, a fourth NMOS switch tube H-MN4, a fifth NMOS switch tube H-MN5, a sixth NMOS switch tube H-MN6, a seventh NMOS switch tube H-MN7, an eighth NMOS switch tube H-MN8, a first PMOS switch tube H-MP1, a second PMOS switch tube H-MP2, a third PMOS switch tube H-MP3, a fourth PMOS switch tube H-MP4, a fifth PMOS switch tube H-MP5, a sixth PMOS switch tube H-MP6 and a seventh PMOS switch tube H-MP7;

The input end of the input inverter INV is connected to the gate of the fourth NMOS switch tube H-MN4 and the connection end serves as the input end of the first level conversion circuit 20; the output end of the input inverter INV is connected to the gate of the third NMOS switch tube H-MN3; the power supply end of the input inverter INV is connected to the low-voltage power supply port of the second level conversion circuit 40; the ground end of the input inverter INV, the source of the third NMOS switch tube H-MN3 and the source of the fourth NMOS switch tube H-MN4 are all connected to the second ground port of the second level conversion circuit 40;

The drain of the fourth NMOS switch tube H-MN4 is connected to the drain of the fourth PMOS switch tube H-MP4, and the drain of the third NMOS switch tube H-MN3 is connected to the drain of the third PMOS switch tube H-MP3;

The gate of the third PMOS switch tube H-MP3 is replaced, the gate of the fourth PMOS switch tube H-MP4 is replaced, the source of the fifth NMOS switch tube H-MN5 is replaced, the source of the sixth NMOS switch tube H-MN6 is replaced, the source of the seventh NMOS switch tube H-MN7 is replaced, and the source of the eighth NMOS switch tube H-MN8 is replaced, and they are connected to each other and connected to the first ground port of the first level conversion circuit 20;

The source of the first PMOS switch tube H-MP1, the source of the second PMOS switch tube H-MP2, the source of the fifth PMOS switch tube H-MP5, the source of the sixth PMOS switch tube H-MP6 and the source of the seventh PMOS switch tube H-MP7 are connected to each other and connected to the high-voltage power supply port of the first level conversion circuit 20;

Replace the gate of the first PMOS switch tube H-MP1, replace the source of the fourth PMOS switch tube H-MP4, replace the drain of the fifth NMOS switch tube H-MN5, replace the gate of the sixth NMOS switch tube H-MN6 and replace the gate of the fifth PMOS switch tube H-MP5 to be connected to each other;

The gate of the second PMOS switch tube H-MP2 is respectively connected to the source of the third PMOS switch tube H-MP3 and the drain of the first PMOS switch tube H-MP1;

Replace the drain of the sixth NMOS switch tube H-MN6, replace the gate of the seventh NMOS switch tube H-MN7, replace the drain of the fifth PMOS switch tube H-MP5 and replace the gate of the sixth PMOS switch tube H-MP6 to be connected to each other;

Replace the drain of the sixth PMOS switch tube H-MP6, replace the gate of the seventh PMOS switch tube H-MP7, replace the drain of the seventh NMOS switch tube H-MN7 and replace the gate of the eighth NMOS switch tube H-MN8 to be connected to each other;

The drain of the seventh NMOS switch tube H- MN7 is connected to the drain of the eighth NMOS switch tube H- MN8 , and the connection end serves as the output end of the first level conversion circuit 20 .

In the solution of the present application, the first level conversion circuit 20 is used to switch from the low voltage domain to the high voltage domain. In FIG7 , the low voltage power supply port is specifically VDD, the high voltage power supply port is VB, the first ground port is VS, and the second ground port is GND.

In the specific implementation of FIG. 7 , the input end of the input inverter INV is connected to the gate of the fourth NMOS switch tube H-MN4 and the connection end is used as the input end of the first level conversion circuit 20. The second switch signal INP input in the low voltage domain is input to the inverter INV to generate INB. INP and INB are respectively connected to the fourth NMOS switch tube H-MN4 and the third NMOS switch tube H-MN3. In practical applications, the fourth NMOS switch tube H-MN4 and the third NMOS switch tube H-MN3 can both be devices with a gate-source voltage VGS=5V and a drain-source voltage VDS that can withstand high voltage.

The pulses INP and INB in the low-voltage domain are converted into X1 and X2 in the high-voltage domain. The third PMOS switch tube H-MP3 and the fourth PMOS switch tube H-MP4 can also be devices with a gate-source voltage VGS=5V and a drain-source voltage VDS that can withstand high voltage. The third PMOS switch tube H-MP3 and the fourth PMOS switch tube H-MP4 play a role in isolating high voltage, so that the relative voltage of each port of the first PMOS switch tube H-MP1 and the second PMOS switch tube H-MP2 is within 5V. X1 and X2 are generated into X3 and X4 after the third PMOS switch tube H-MP3 and the fourth PMOS switch tube H-MP4 are replaced. The voltage difference between X3, X4 and VB is less than 5V. H-MP1, H-MP2, H-MP5, H-MP6, H-MP7, H-MN5, H-MN6, H-MN7 and H-MN8 are all low voltage 5V devices, built in high voltage nwell. The absolute values of the 4 ports of these devices can withstand high voltage, but the relative voltage of the ports is still within 5V.

In Figure 7, X4 passes through the inverter composed of H-MN6 and H-MP5, and then passes through the buffer circuit composed of H-MN7, H-MN8, H-MP6, and H-MP7, and can output a voltage HSG with driving capability, so that when the input INP is low level (0v), the output HSG is VS (0v), and when the input INP is high level (5v), the output HSG is VB (65v). In addition, it should be noted that the first ground port in this implementation is VS, which is a floating ground, which can be a real GND or other potentials.

In a specific embodiment of the present invention, the voltage of the high voltage power supply is 60V, the voltage of the low voltage power supply is 5V; the width-to-length ratio of the second NMOS switch tube MN2 is greater than 10000, the width-to-length ratio of the first NMOS switch tube MN1 is greater than 1000, and the width-to-length ratio of any other MOS tube is less than 100.

As described above, in the solution of the present application, the first NMOS switch tube MN1 and the second NMOS switch tube MN2 both have a large width-to-length ratio, especially the second NMOS switch tube MN2 on the high-voltage side, which needs to have a very high width-to-length ratio so that it takes a very short time to be turned on, that is, when it is turned on, the voltage of the high-voltage power supply can be quickly applied to the output terminal VOUT of the switching circuit.

By applying the technical solution provided in the embodiment of the present invention, an NMOS circuit structure is used on both the high-voltage side and the low-voltage side, that is, the present application solution uses a circuit structure of a first NMOS switch tube MN1 + a second NMOS switch tube MN2 to realize the required switching circuit.

Specifically, in the switching circuit of the present application, the MOSFETs on the high-voltage side and the low-voltage side are both NMOS, that is, the first NMOS switch tube and the second NMOS switch tube. In order to enable the circuit to work, the present application scheme introduces capacitors and PMOS switch tubes to act as bootstrap circuits, and through the first level conversion circuit, high voltage can be applied to the second NMOS switch tube to ensure the conduction of the second NMOS switch tube. Specifically, the drain of the second NMOS switch tube is connected to the high voltage power supply, and the gate of the second NMOS switch tube is connected to the second control signal; the first end of the capacitor is connected to the drain of the PMOS switch tube, and the second end of the capacitor is connected to the output end of the switch circuit; the source of the PMOS switch tube is connected to the low voltage power supply, and the gate of the PMOS switch tube is connected to the third control signal; the drain of the first NMOS switch tube is connected to the source of the second NMOS switch tube, and the connection end serves as the output end of the switch circuit, the source of the first NMOS switch tube is grounded, and the gate of the first NMOS switch tube is connected to the first control signal, the high voltage power supply port of the first level conversion circuit is connected to the first end of the capacitor, the first ground port of the first level conversion circuit is connected to the second end of the capacitor, the low voltage power supply port of the first level conversion circuit is connected to the low voltage power supply, the second ground port of the first level conversion circuit is connected to the ground voltage, the input port of the first level conversion circuit is connected to an external signal, and the output port of the first level conversion circuit is connected to the second control signal; the first level conversion circuit is used for, when the external signal is the low voltage power supply voltage, the output second control signal is the first terminal voltage of the capacitor; when the external signal is the ground voltage, the output second control signal is the ground voltage. The on and off states of the PMOS switch tube and the second NMOS switch tube are opposite, and the on and off states of the first NMOS switch tube and the second NMOS switch tube are opposite, so that the voltage at the output end of the switching circuit is the high voltage power supply voltage or the ground voltage.

It can be seen from the circuit structure that when the first NMOS switch tube is turned on and the switch circuit outputs the ground voltage, the second NMOS switch tube is turned off, and the low-voltage power supply can charge the capacitor through the PMOS switch tube. When the second NMOS switch tube is turned on, since the voltage across the capacitor cannot change suddenly, at this time, the voltage of the capacitor to the ground will rise to (the voltage of the low-voltage power supply + the voltage at the output end of the current switch circuit), and the voltage at the output end of the current switch circuit is equal to the voltage of the high-voltage power supply connected to the drain of the second NMOS switch tube, and the PMOS switch tube is turned off to achieve isolation between the high voltage of the capacitor and the low-voltage power supply at the source of the PMOS switch tube. It should be noted that when the second NMOS switch tube is turned on, its drain is connected to the voltage of the high-voltage power supply, so in order to ensure the conduction of the second NMOS switch tube, the gate of the second NMOS switch tube needs to apply a high voltage to ensure that the second NMOS switch tube has a certain gate-source voltage. In this regard, a first level conversion circuit is provided in the present application scheme. When the external signal of the first level conversion circuit is a low-voltage power supply voltage, the second control signal output by the first level conversion circuit can be the first terminal voltage of the capacitor, that is, the first terminal voltage of the capacitor is applied to the gate of the second NMOS switch tube at this time. There will always be a certain voltage difference between the gate and source of the second NMOS switch tube, which can ensure that the second NMOS switch tube is always turned on while its source voltage continues to increase.

It can be seen that in the present application, the voltage at the output end of the switch circuit is the high voltage power supply voltage or the ground voltage, which effectively realizes a switch circuit whose output level can switch between high and low voltage without affecting the response speed of the switch. In addition, both the high voltage side and the low voltage side use the NMOS circuit structure, which is conducive to reducing the occupied area of the switch circuit.

It should also be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

The present application uses specific examples to illustrate the principles and implementation methods of the present invention, and the description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims (10)

1. A switch circuit, comprising: a first NMOS switch tube, a second NMOS switch tube, a first level conversion circuit, a capacitor and a PMOS switch tube; The source of the PMOS switch tube is connected to a low voltage power supply, and the gate of the PMOS switch tube is connected to a third control signal; The first end of the capacitor is connected to the drain of the PMOS switch tube, and the second end of the capacitor is connected to the output end of the switch circuit; The drain of the first NMOS switch tube is connected to the source of the second NMOS switch tube, and the connection end serves as the output end of the switch circuit, the source of the first NMOS switch tube is grounded, and the gate of the first NMOS switch tube is connected to the first control signal; The drain of the second NMOS switch tube is connected to a high voltage power supply, and the gate of the second NMOS switch tube is connected to a second control signal; The high-voltage power supply port of the first level conversion circuit is connected to the first end of the capacitor, the first ground port of the first level conversion circuit is connected to the second end of the capacitor, the low-voltage power supply port of the first level conversion circuit is connected to the low-voltage power supply, the second ground port of the first level conversion circuit is connected to the ground voltage, the input port of the first level conversion circuit is connected to an external signal, and the output port of the first level conversion circuit is connected to the second control signal; the first level conversion circuit is used for outputting the second control signal as the first end voltage of the capacitor when the external signal is the low-voltage power supply voltage; and outputting the second control signal as the ground voltage when the external signal is the ground voltage; The on and off states of the PMOS switch tube and the second NMOS switch tube are opposite, and the on and off states of the first NMOS switch tube and the second NMOS switch tube are opposite, so that the voltage at the output end of the switch circuit is the high voltage power supply voltage or the ground voltage. 2. The switch circuit according to claim 1, characterized in that when the second control signal is 0v, the first control signal is the voltage of the low-voltage power supply, and the third control signal is 0v; When the second control signal is a voltage higher than the high voltage power supply, the first control signal is 0 V, and the third control signal is a voltage higher than the high voltage power supply. 3. The switch circuit according to claim 1, characterized in that the switch circuit further comprises: a single-turn dual circuit and a drive circuit; The input end of the single-to-dual circuit is connected to a switch control signal, the first output end of the single-to-dual circuit outputs a first switch signal, and the second output end of the single-to-dual circuit outputs a second switch signal; the first switch signal is in the opposite direction of the switch control signal, and the second switch signal is in the same direction as the switch control signal; the power port of the single-to-dual circuit is connected to the low-voltage power supply, and the ground port of the single-to-dual circuit is grounded; The input terminal of the driving circuit is connected to the first switch signal, the output terminal of the driving circuit outputs the first control signal, the power port of the driving circuit is connected to the low-voltage power supply, and the ground port of the driving circuit is grounded; The second switch signal is connected to an input terminal of the first level conversion circuit as the external signal. 4 . The switch circuit according to claim 3 , wherein the second control signal and the third control signal are connected together. 5. The switch circuit according to claim 3, characterized in that the switch circuit further comprises: a second level conversion circuit; The input end of the second level conversion circuit is connected to the second switch signal, the output end of the second level conversion circuit outputs the third control signal, the high-voltage power supply port of the second level conversion circuit is respectively connected to the first end of the capacitor and the drain of the PMOS switch tube, and the low-voltage power supply port of the second level conversion circuit is connected to the low-voltage power supply; the first ground port of the second level conversion circuit is connected to the source of the second NMOS switch tube, and the second ground port of the second level conversion circuit is grounded. 6 . The switch circuit according to claim 5 , wherein the second level conversion circuit is completely identical to the first level conversion circuit. 7. The switch circuit according to claim 3, characterized in that the single-to-dual circuit comprises: switching a first NMOS switch tube, switching a second NMOS switch tube, switching a first PMOS switch tube, and switching a second PMOS switch tube; The drain of the first NMOS switch tube, the source of the first PMOS switch tube, the gate of the second PMOS switch tube, and the gate of the second NMOS switch tube are connected to each other, and the connection end serves as the input end of the single-to-dual circuit; The source of the first NMOS switch tube is connected to the drain of the first PMOS switch tube, and the connection end serves as the second output end of the single-to-dual circuit to output the second switch signal, and the gate of the first PMOS switch tube is connected to the ground port of the single-to-dual circuit; The gate of the first NMOS switch tube is connected to the source of the second PMOS switch tube and the connection terminal is connected to the power port of the single-to-dual circuit; The drain of the second NMOS switch tube is connected to the drain of the second PMOS switch tube, and the connection end serves as the first output end of the single-to-dual circuit to output the first switching signal, and the source of the second NMOS switch tube is connected to the ground port of the single-to-dual circuit. 8. The switch circuit according to claim 3, characterized in that the driving circuit comprises: driving a first NMOS switch tube, driving a second NMOS switch tube, driving a first PMOS switch tube and driving a second PMOS switch tube; The gate of the first NMOS switch tube is connected to the gate of the first PMOS switch tube, and the connection end serves as the input end of the driving circuit; The source electrode of the first NMOS switch tube is connected to the source electrode of the second NMOS switch tube, and the connection terminal is connected to the ground port of the driving circuit; the source electrode of the first PMOS switch tube is connected to the source electrode of the second PMOS switch tube, and the connection terminal is connected to the power port of the driving circuit; The drain of the first NMOS switch tube, the drain of the first PMOS switch tube, the gate of the second NMOS switch tube, and the gate of the second PMOS switch tube are connected to each other; The drain electrode of the second NMOS switch tube is connected to the drain electrode of the second PMOS switch tube, and the connection end serves as the output end of the driving circuit. 9. The switch circuit according to claim 3, characterized in that the first level conversion circuit comprises: an input inverter, a third NMOS switch tube, a fourth NMOS switch tube, a fifth NMOS switch tube, a sixth NMOS switch tube, a seventh NMOS switch tube, an eighth NMOS switch tube, a first PMOS switch tube, a second PMOS switch tube, a third PMOS switch tube, a fourth PMOS switch tube, a fifth PMOS switch tube, a sixth PMOS switch tube and a seventh PMOS switch tube; The input end of the input inverter is connected to the gate of the fourth NMOS switch tube and the connection end serves as the input end of the first level conversion circuit; the output end of the input inverter is connected to the gate of the third NMOS switch tube; the power supply end of the input inverter is connected to the low-voltage power supply port of the second level conversion circuit; the ground end of the input inverter, the source of the third NMOS switch tube and the source of the fourth NMOS switch tube are all connected to the second ground port of the second level conversion circuit; The drain of the fourth NMOS switch tube is connected to the drain of the fourth PMOS switch tube, and the drain of the third NMOS switch tube is connected to the drain of the third PMOS switch tube; The gate of the third PMOS switch tube, the gate of the fourth PMOS switch tube, the source of the fifth NMOS switch tube, the source of the sixth NMOS switch tube, the source of the seventh NMOS switch tube and the source of the eighth NMOS switch tube are connected to each other and connected to the first ground port of the first level conversion circuit; The source of the first PMOS switch tube, the source of the second PMOS switch tube, the source of the fifth PMOS switch tube, the source of the sixth PMOS switch tube and the source of the seventh PMOS switch tube are connected to each other and connected to the high-voltage power supply port of the first level conversion circuit; The gate of the first PMOS switch tube, the source of the fourth PMOS switch tube, the drain of the fifth NMOS switch tube, the gate of the sixth NMOS switch tube and the gate of the fifth PMOS switch tube are connected to each other; The gate of the second PMOS switch tube is respectively connected to the source of the third PMOS switch tube and the drain of the first PMOS switch tube; The drain of the sixth NMOS switch tube, the gate of the seventh NMOS switch tube, the drain of the fifth PMOS switch tube and the gate of the sixth PMOS switch tube are connected to each other; The drain of the sixth PMOS switch tube, the gate of the seventh PMOS switch tube, the drain of the seventh NMOS switch tube and the gate of the eighth NMOS switch tube are connected to each other; The drain of the seventh NMOS switch tube is connected to the drain of the eighth NMOS switch tube, and the connection end serves as the output end of the first level conversion circuit. 10. The switching circuit according to any one of claims 1 to 9 is characterized in that the voltage of the high-voltage power supply is 60V, the voltage of the low-voltage power supply is 5V; the width-to-length ratio of the second NMOS switch tube is greater than 10000, the width-to-length ratio of the first NMOS switch tube is greater than 1000, and the width-to-length ratio of any other MOS tube is less than 100.