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CN118795756B - A calibration method and system for a digital time converter - Google Patents

A calibration method and system for a digital time converter Download PDF

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Publication number
CN118795756B
CN118795756B CN202411263263.1A CN202411263263A CN118795756B CN 118795756 B CN118795756 B CN 118795756B CN 202411263263 A CN202411263263 A CN 202411263263A CN 118795756 B CN118795756 B CN 118795756B
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China
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phase
digital
information
time
delay
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CN118795756A (en
Inventor
曹辉
耿莉
申佳
伍民顺
马彦飞
赵妍
许江涛
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Zhejiang Science Electronic Tech Co ltd
Xian Jiaotong University
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Zhejiang Science Electronic Tech Co ltd
Xian Jiaotong University
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention relates to a calibration method and a calibration system of a digital time converter in the technical field of electronic circuits, and the calibration method comprises the following steps of setting a preset phase difference, delaying a reference clock of a delay circuit to a preset phase, keeping the reference clock of the delay circuit at the preset phase, delaying the digital time converter for the first time to a target detection phase I, recording phase information I detected by the time digital converter and code value information I of the digital time converter corresponding to the phase information I, keeping the reference clock of the delay circuit at the preset phase, delaying the digital time converter again to a target detection phase II, recording the phase information II detected by the time digital converter and code value information II of the digital time converter corresponding to the phase information II, and calculating a calibration result based on the phase information I, the code value information I, the phase information II and the code value information II, thereby solving the problem that the digital time converter is unstable and cannot provide an accurate value.

Description

Calibration method and system of digital time converter
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a method and a system for calibrating a digital time converter.
Background
Fractional division means that the division ratio is not an integer but comprises an integer part and a fractional part, e.g. if a divider with a division ratio of 2.5 is required, it will switch the division ratio between different periods, e.g. with a division of 2 times in some periods and a division of 3 times in other periods. The problem of fractional frequency division (fractionl-n) is solved by an all-digital phase-locked loop (ADPLL) because the traditional analog phase-locked loop is difficult to realize, but the Digital Time Converter (DTC) is required to be used for realizing the fractional frequency division (fractionl-n), and the Digital Time Converter (DTC) is accompanied by reasons of process deviation, temperature transformation, unstable power supply voltage and the like, so that the performance of the Digital Time Converter (DTC) is influenced, and a fixed accurate value cannot be output, so that the calibration of the digital time converter is an important link before the fractional frequency division.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a calibration method and a calibration system of a D digital time converter, which solve the problem that the digital time converter is unstable and cannot provide accurate values.
In order to solve the technical problems, the invention is solved by the following technical scheme:
a method of calibrating a digital-to-time converter, comprising the steps of:
setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase based on the preset phase difference;
Keeping the reference clock of the delay circuit at a preset phase, delaying the digital time converter for the first time to a target detection phase I, and recording phase information I detected by the time digital converter and code value information I of the digital time converter corresponding to the phase information I, wherein the preset phase difference is a phase difference between the target detection phase I and the preset phase;
Keeping the reference clock of the delay circuit at a preset phase, delaying the digital time converter to a target detection phase II again, and recording phase information II detected by the time digital converter and code value information II of the digital time converter corresponding to the phase information II;
And calculating a calibration result of the digital time converter based on the first phase information, the first code value information, the second phase information and the second code value information.
Optionally, delaying the reference clock to a preset phase based on the preset phase difference includes the steps of:
adjusting delay information of a reference clock and detecting phase adjustment information of a time-to-digital converter;
when the phase adjustment information reaches a preset phase difference, the reference clock adjusts and reaches the preset phase according to the delay information when the phase adjustment information reaches the preset phase difference.
Optionally, calculating the calibration result of the digital-to-time converter includes the steps of:
Calculating the phase information difference between the first phase information and the second phase information, and calculating the code value information difference between the first code value information and the second code value information;
And calculating a calibration result based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference/phase information difference.
Optionally, when the digital-to-digital converter delays for the first time, the first phase information detected by the digital-to-digital converter and when the digital-to-digital converter delays again, the second phase information detected by the digital-to-digital converter is an adjacent phase or a non-adjacent phase.
A method of calibrating a digital-to-time converter, comprising the steps of:
Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase I based on the preset phase difference;
Keeping the reference clock of the delay circuit at a preset phase I, delaying the digital time converter for the first time to a target detection phase I, and recording phase information I detected by the time digital converter and code value information I of the digital time converter corresponding to the phase information I, wherein the preset phase difference is a phase difference between the target detection phase I and the preset phase I;
Delaying the reference clock of the delay circuit to a preset phase two based on the preset phase difference;
the reference clock of the delay circuit is kept at a preset phase II, the digital time converter is delayed again to a target detection phase II, phase information II detected by the time digital converter and code value information II of the digital time converter corresponding to the phase information II are recorded, wherein the preset phase difference is also the phase difference between the target detection phase II and the preset phase II;
And calculating a calibration result of the digital time converter based on the first phase information, the first code value information, the second phase information and the second code value information.
A calibration system of a digital-to-time converter performing the calibration method of a digital-to-time converter as described above, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit, and a time-to-digital conversion circuit;
the calibration logic is used for providing a preset phase difference;
The delay circuit is used for delaying the input reference clock to a preset phase based on the preset phase difference;
the digital time conversion circuit is used for carrying out delay processing on an input reference clock for a plurality of times so as to delay the input reference clock to a first target detection phase and a second target detection phase respectively and obtain code value information I and code value information II, wherein the preset phase difference is a phase difference between the first target detection phase and the preset phase;
the time-to-digital conversion circuit is used for detecting the first phase information after the first delay processing of the digital-to-time conversion circuit and detecting the second phase information after the second delay processing of the digital-to-time conversion circuit;
The calibration logic is further configured to output a calibration result based on the first phase information, the second phase information, the first code value information corresponding to the first phase information, and the second code value information corresponding to the second phase information.
Optionally, the delay circuit delays the reference clock to a preset phase based on the preset phase difference, including the steps of:
the delay circuit adjusts delay information of the reference clock;
the time-to-digital conversion circuit detects phase adjustment information, and when the phase adjustment information reaches a preset phase difference, delay information of a reference clock reaches a preset phase.
Optionally, the calibration logic outputs a calibration result, including the steps of:
Calculating the phase information difference between the first phase information and the second phase information, and calculating the code value information difference between the first code value information and the second code value information;
And calculating a calibration result based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference/phase information difference.
A calibration system of a digital-to-time converter performing the calibration method of a digital-to-time converter as described above, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit, and a time-to-digital conversion circuit;
the calibration logic is used for providing a preset phase difference;
The delay circuit is used for respectively delaying the input reference clock to a preset phase I and a preset phase II based on the preset phase difference;
The digital time conversion circuit is used for carrying out first delay processing on the input reference clock after the delay circuit delays the input reference clock to a preset phase I so as to delay the input reference clock to a target detection phase I and obtain code value information I; after the delay circuit delays the input reference clock to a preset phase II, performing delay processing on the input reference clock again to delay the input reference clock to a target detection phase II, and obtaining code value information II, wherein the preset phase difference is a phase difference between the target detection phase I and the preset phase I, and the preset phase difference is a phase difference between the target detection phase II and the preset phase II;
the time-to-digital conversion circuit is used for detecting the first phase information after the first delay processing of the digital-to-time conversion circuit and detecting the second phase information after the second delay processing of the digital-to-time conversion circuit;
The calibration logic is further configured to output a calibration result based on the first phase information, the second phase information, the first code value information corresponding to the first phase information, and the second code value information corresponding to the second phase information.
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
The method for delaying the reference clock to the preset phase avoids the problem of inaccurate output value of the time-to-digital converter caused by process deviation, temperature transformation, unstable power supply voltage and the like, and particularly, compared with the method without delay processing of the reference clock, the method for delaying the reference clock by the time-to-digital converter reduces the error of the time-to-digital converter in the phase measurement every time by adjusting the reference clock to the preset phase, improves the calibration precision and prevents clock jitter.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a flowchart of a calibration method of a digital time converter according to a first embodiment;
FIG. 2 is one of schematic time links for calibrating the chain lengths of 28-29 with the chain length of the time-to-digital converter being 40 in accordance with the first embodiment;
FIG. 3 is a second schematic diagram of a time link when the chain length of the time-to-digital converter is 40 chain lengths and the chain lengths of 28-29 are calibrated according to the second embodiment;
fig. 4 is a system configuration diagram of a calibration system of a digital time converter according to a second embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following examples, which are illustrative of the present invention and are not intended to limit the present invention thereto.
Example 1
As shown in fig. 1, a calibration method of a digital-to-time converter includes the steps of firstly, before the digital-to-time converter performs calibration, determining a phase difference value to be measured, wherein the phase difference value must be preset in a calibration logic circuit, so that a preset phase difference is set in the logic circuit, a reference clock in a delay circuit is delayed to a preset phase based on the preset phase difference, and a state of the delay circuit is kept unchanged, so that the reference clock is always located in the preset phase, and it is to be noted that in this embodiment, the preset phase difference is 0-3 phases.
The reference clock is adjusted according to the delay information when reaching the preset phase difference and reaches the preset phase when the phase adjustment information reaches the preset phase difference, so that the delay information when adjusting the reference clock is accurate by detecting the phase adjustment information of the time-to-digital converter, the preset phase difference can be reached, and the delay circuit keeps the circuit parameters unchanged after the preset phase is reached.
In this embodiment, as shown in fig. 2, the chain length of the time-to-digital converter is taken as 40 chain lengths, the chain lengths of 28 to 29 are calibrated, the reference clock is received at this time, and the 28 th link and the 29 th link need to be detected to calibrate, so that the received reference clock needs to be adjusted to the vicinity of the 28 th link, the adjustment range is a preset phase difference, the reference clock can be adjusted to the 27 th link according to the requirement that the preset phase difference is set to 0 to 3, and at this time, the phase adjustment information detected by the time-to-digital converter satisfies the range of 0 to 3, and the reference clock reaches the preset phase.
After the delay circuit is well adjusted, the delay circuit is kept, so that a reference clock in the delay circuit is always positioned in a preset phase, then the digital time converter is delayed to a target detection phase I (namely, delayed to a 28 th link position) for the first time, the phase information I detected by the digital time converter and the code value information I of the digital time converter corresponding to the phase information I are recorded, wherein the preset phase difference is the phase difference between the target detection phase I and the preset phase, then the delay circuit is kept unchanged (the reference clock in the delay circuit is always positioned in the preset phase), the digital time converter is further delayed to a target detection phase II (namely, delayed to a 29 th link position), the phase information II detected by the digital time converter and the code value information II of the digital time converter corresponding to the phase information II are recorded, and therefore the detection standard of the digital time converter and the digital time converter is adjusted in a mode of delaying the reference clock to the phase needing to be measured, namely, the preset phase position is adopted, and the problem of inaccurate output value of the digital time converter caused by process deviation, temperature transformation, unstable power supply voltage and the like is avoided.
On the other hand, when the reference clock delay processing is not performed, the reference detected by the time-to-digital converter is the 0 th link, namely, when the reference clock delay processing is performed for the first time, the time-to-digital converter detects the phases from the 0 th link to the 28 th link, and when the reference clock delay processing is performed for the second time, the reference is adjusted to the 27 th link from the 0 th link, so that when the reference clock delay processing is performed for the first time, the time-to-digital converter detects the phases from the 27 th link to the 28 th link, and when the reference clock delay processing is performed for the second time, the time-to-digital converter detects the phases from the 27 th link to the 29 th link, therefore, compared with the mode of adjusting the detection reference, the embodiment reduces the detection error, enables the output result to be more accurate, reduces the error range, avoids the problem of unstable digital time converter, and further ensures the accuracy of the calibration result.
Specifically, when the digital time converter delays the input reference clock for the first time, the detected phase information I is marked as phe1, meanwhile, the code value information I corresponding to the digital time converter is recorded, the code1 is marked, when the digital time converter delays the input reference clock again, the detected phase information II is marked as pheN, meanwhile, the code value information II corresponding to the digital time converter is recorded, the code value information II corresponding to the digital time converter is marked as codeN, in fig. 2, the first phase information measured at the first time delay is the first phase information detected at the 28 th link, and the second phase information measured at the second time delay is the second phase information detected at the 29 th link.
Further, calculating a calibration result of the digital time converter based on the first phase information, the first code value information, the second phase information and the second code value information, wherein calculating the calibration result of the digital time converter comprises the steps of calculating a phase information difference between the first phase information and the second phase information, and calculating a code value information difference between the first code value information and the second code value information, and calculating the calibration result based on the phase information difference and the code value information difference, wherein the calibration result = code value information difference/phase information difference.
Specifically, the phase information differencePheN-phe1, codeN-code1 code value information difference, and finally obtaining a calibration result。
It should be noted that, the input range of the reference clock may be flexibly set, the frequency and the duty ratio may be adjusted at any time according to the actual situation, when the digital time converter delays for the first time, the phase information detected by the time digital converter is adjacent or non-adjacent with the phase information detected by the time digital converter when the digital time converter delays again, and in this embodiment, no further limitation is made. .
On the other hand, differential nonlinear measurement can also be performed on the time-to-digital converter, in which case each link is measured according to the above method, specifically, when the ph=1 of the time-to-digital converter, the corresponding delay information is measured by the time-to-digital converter, the obtained measurement value (code value information difference) is code1-code0, when the ph=2 of the time-to-digital converter (the phase information at this time represents the delay between ph 1 and ph 2, i.e., the phase information difference), the corresponding delay information is measured by the time-to-digital converter, the obtained measurement value is code2-code1, and so on, the delay information of each basic unit of the whole time-to-digital converter is measured by the time-to-digital converter, and then the measured each phase information difference is accumulated to obtain the actual delay value of the delay chain lengthAnd obtain the theoretical delay value of the delay chain lengthThen, based on a differential nonlinear formula, the differential nonlinearity of the time-to-digital converter can be obtained, wherein the calculation formula is as follows:。
When the integral nonlinearity measurement is carried out on the time-to-digital converter, the integral nonlinearity measurement can be obtained according to differential nonlinearity, and the calculation formula is as follows: N represents the chain length.
Example 2
The difference between the embodiment and the embodiment is that the embodiment performs the reference clock delay processing twice, that is, performs the adjustment of the detection reference twice, and includes the steps of setting a preset phase difference, delaying the reference clock in the delay circuit to the preset phase one based on the preset phase difference, keeping the reference clock in the delay circuit at the preset phase one, delaying the digital time converter to the target detection phase one for the first time, recording the phase information one detected by the time digital converter and the code value information one of the digital time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one, delaying the reference clock in the delay circuit to the preset phase two based on the preset phase difference, keeping the reference clock in the delay circuit at the preset phase two, delaying the digital time converter to the target detection phase two when the reference clock is delayed again based on the preset phase two, recording the phase information two detected by the time digital time converter and the code value information two of the digital time converter corresponding to the phase information two, wherein the preset phase difference is also the phase information between the target detection phase two and the preset phase two, and calculating the code value information of the digital time converter based on the phase difference information.
Specifically, as shown in fig. 3, taking the chain length of the time-to-digital converter as 40 chain lengths, the chain length of 28-29 is calibrated, at this time, the reference clock is received, because the 28 th link and the 29 th link need to be detected, and then the calibration can be performed, before the first delay processing is performed, the embodiment adjusts the received reference clock to the vicinity of the 28 th link, according to the requirement that the preset phase difference is set to 0-3, the reference clock can be adjusted to the 27 th link, at this time, the phase adjustment information detected by the time-to-digital converter satisfies the range of 0-3, the reference clock reaches the preset phase one, then the delay circuit remains unchanged, so that the reference clock in the delay circuit is always located at the preset phase one, then the digital time-to-digital converter is delayed to the target detection phase one (i.e. to the position of the 28 th link), and the first phase information detected by the time-to-digital time-digital converter and the code value information of the digital time-to-digital converter corresponding to the 28 th link are recorded, at this time, the phase information recorded by the time-to the digital value of the digital converter is the first code value of the first link of the 27 to the digital converter of the first link of the 27.
Then, the reference clock is delayed again in the delay circuit, at this time, because the 29 th link is required to be detected, the reference clock can be delayed to the 28 th link based on the range requirement of the preset phase difference, so that the reference clock reaches the preset phase two, the delay circuit is kept unchanged, the reference clock in the delay circuit is always positioned at the preset phase two, then the digital time converter is delayed to the target detection phase two (namely, to the position of the 29 th link) for the second time, the phase information two detected by the time digital converter and the code value information two of the digital time converter corresponding to the phase information two are recorded, at this time, the phase information recorded by the time digital converter is the phase of the 28 th link to the 29 th link, and the code value information recorded by the digital time converter is the code value information of the 28 th link to the 29 th link.
Compared with the first embodiment, the reference clock delay processing of the delay circuit is performed twice, and the reference is respectively adjusted from the 0 th link to the 27 th link and the 28 th link, so that the time-to-digital converter detects the phase from the 27 th link to the 28 th link in the first delay, and detects the phase from the 28 th link to the 29 th link in the second delay, so that the detection output value is more accurate, the error range is smaller, and the problem of instability of the digital-to-time converter is avoided.
Example 3
As shown in FIG. 4, the calibration system of the digital-to-time converter comprises a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit, wherein the calibration logic circuit is used for providing a preset phase difference, the delay circuit is used for delaying an input reference clock to the preset phase based on the preset phase difference and keeping the state unchanged, the digital-to-time conversion circuit is used for carrying out delay processing on the input reference clock for a plurality of times so as to delay the input reference clock to a target detection phase I and a target detection phase II respectively and obtain code value information I and code value information II, the preset phase difference is a phase difference between the target detection phase I and the preset phase, the time-to-digital conversion circuit is used for detecting the phase information I after the first delay processing is carried out by the digital-to-time conversion circuit, and detecting the phase information II after the second delay processing is carried out by the digital-to-time conversion circuit, and outputting a calibration result based on the phase information I, the phase information II and the code value information II corresponding to the code value information I and the code value information II.
Further, the delay circuit delays the reference clock to a preset phase based on a preset phase difference, and the method comprises the steps of adjusting delay information of the reference clock by the delay circuit, detecting phase adjustment information by the time-to-digital conversion circuit, and enabling the delay information of the reference clock to reach the preset phase when the phase adjustment information reaches the preset phase difference.
Further, the calibration logic outputs a calibration result comprising the steps of calculating a phase information difference between the first phase information and the second phase information and a code value information difference between the first code value information and the second code value information, and calculating the calibration result based on the phase information difference and the code value information difference, wherein the calibration result = code value information difference/phase information difference.
Further, the time-to-digital conversion circuit performs the first delay processing on the detected phase information I and performs the second delay processing on the detected phase information II, and then the detected phase information I and the detected phase information II are adjacent phases or non-adjacent phases.
Specifically, before the digital time converter DTC is calibrated, the phase difference value to be measured must be preset in the calibration logic circuit to obtain a preset phase difference, the measured value may be two adjacent phases or a phase between two non-adjacent phases, the range of the input reference clock 100 is flexible, the input reference clock can be adjusted at any time, the frequency and the duty ratio can be changed, and the reference clock flows into the digital time converter circuit and the delay circuit respectively, which can cause the reference clock to generate delay signals 101 and 102.
In order to ensure that the phase difference to be measured is a preset phase difference, the calibration logic circuit firstly sends a control signal 104 to the delay circuit to generate expected delay, so that the delay circuit delays the reference clock to the preset phase, the time-to-digital conversion circuit detects the phase information 103 to ensure that the delay information generated by the delay circuit is accurate, and then the calibration logic circuit does not send information to the delay circuit any more, and the state of the delay circuit is kept unchanged.
The calibration logic circuit then sends information 105 to the digital-to-time converter circuit to start the operation, the digital-to-time converter circuit controls the code to be a thermometer code, the first detected phase information of the time-to-digital converter circuit is denoted as ph 1, the calibration logic circuit records the code value information of the digital-to-time converter circuit, the second detected phase information is denoted as ph 2, the calibration logic circuit records the code value information of the digital-to-time converter circuit, the second code2, the nth detected phase information is denoted as pheN, the calibration logic circuit records the code value information of the digital-to-time converter circuit, the N is denoted as codeN, and in the embodiment, the second detected and nth detected related data information can be understood as the data detected after the delay processing again.
Finally, the difference value between the code value information of the digital time conversion circuit is codeN-code1 is calculated asThe phase information difference value is pheN-phe1 and is recorded asThe calibration logic thus calculates and outputs the calibration result of the digital time conversion circuit as 106, and the calculated calibration value thereof is:。
since the calibration system of the digital time converter of the present embodiment performs the calibration method of the digital time converter of the first embodiment, a detailed description is not repeated in the present embodiment.
Example 4
The calibration system of the digital time converter comprises a calibration logic circuit, a digital time conversion circuit, a delay circuit and a time digital conversion circuit, wherein the calibration logic circuit is used for providing a preset phase difference, the delay circuit is used for delaying an input reference clock to a first preset phase and a second preset phase based on the preset phase difference, the digital time conversion circuit is used for carrying out first delay processing on the input reference clock after the delay circuit delays the input reference clock to the first preset phase so as to delay the input reference clock to the first target detection phase to obtain code value information, the delay circuit delays the input reference clock to the second preset phase again so as to delay the input reference clock to the second target detection phase to obtain code value information, the preset phase difference is the phase difference between the first target detection phase and the first preset phase, the time digital conversion circuit is used for detecting the first phase information after the delay processing of the delay circuit is carried out first time, and carrying out second delay processing on the input reference clock to the target detection phase so as to obtain the code value information, and the code value information is obtained after the delay circuit delays the input reference clock to the second target detection phase to obtain the code value information, wherein the preset phase difference is the phase difference between the first target detection phase and the first preset phase difference and the second preset phase difference, and the second phase difference is used for calibrating the phase information.
Compared with the third embodiment, the difference is that the delay circuit of the present embodiment performs the reference clock delay processing twice, thereby further improving the accuracy of calibration.
While the invention has been described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and additions may be made without departing from the scope of the invention. Those skilled in the art will appreciate that many modifications, adaptations and variations of the present invention can be made using the techniques disclosed herein without departing from the spirit and scope of the invention, and that many modifications, adaptations and variations of the present invention are within the scope of the invention as defined by the appended claims.

Claims (9)

1.一种数字时间转换器的校准方法，其特征在于，包括以下步骤：1. A method for calibrating a digital-to-time converter, comprising the following steps: 设定预设相位差，并基于所述预设相位差将延迟电路的参考时钟延迟至预设相位；Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase based on the preset phase difference; 保持延迟电路的参考时钟位于预设相位，将数字时间转换器进行第一次延迟至目标检测相位一，并记录时间数字转换器检测到的相位信息一，以及与所述相位信息一对应的数字时间转换器的码值信息一，其中，所述预设相位差为目标检测相位一与预设相位之间的相位差，且预设相位差的范围为0~3个相位；Keep the reference clock of the delay circuit at a preset phase, delay the digital-to-time converter for the first time to the target detection phase one, and record the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase, and the range of the preset phase difference is 0 to 3 phases; 保持延迟电路的参考时钟位于预设相位，将数字时间转换器进行再次延迟至目标检测相位二，并记录时间数字转换器检测到的相位信息二，以及与所述相位信息二对应的数字时间转换器的码值信息二；Keep the reference clock of the delay circuit at a preset phase, delay the digital-to-time converter again to the target detection phase 2, and record the phase information 2 detected by the time-to-digital converter and the code value information 2 of the digital-to-time converter corresponding to the phase information 2; 基于所述相位信息一、码值信息一、相位信息二以及码值信息二，计算数字时间转换器的校准结果。Based on the phase information one, the code value information one, the phase information two and the code value information two, a calibration result of the digital-to-time converter is calculated. 2.根据权利要求1所述的一种数字时间转换器的校准方法，其特征在于，基于所述预设相位差将参考时钟延迟至预设相位，包括以下步骤：2. A calibration method for a digital-to-time converter according to claim 1, characterized in that delaying the reference clock to a preset phase based on the preset phase difference comprises the following steps: 调整参考时钟的延迟信息，并检测时间数字转换器的相位调整信息；Adjusting the delay information of the reference clock and detecting the phase adjustment information of the time-to-digital converter; 当所述相位调整信息达到预设相位差时，参考时钟根据达到预设相位差时的延迟信息调整并达到预设相位。When the phase adjustment information reaches a preset phase difference, the reference clock is adjusted according to the delay information when the preset phase difference is reached and reaches a preset phase. 3.根据权利要求1所述的一种数字时间转换器的校准方法，其特征在于，计算数字时间转换器的校准结果，包括以下步骤：3. The calibration method of a digital-to-time converter according to claim 1, wherein calculating the calibration result of the digital-to-time converter comprises the following steps: 计算所述相位信息一与相位信息二的相位信息差，并计算所述码值信息一与码值信息二的码值信息差；Calculating a phase information difference between the phase information 1 and the phase information 2, and calculating a code value information difference between the code value information 1 and the code value information 2; 基于所述相位信息差与所述码值信息差计算校准结果，其中，所述校准结果=码值信息差/相位信息差。A calibration result is calculated based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference/phase information difference. 4.根据权利要求1-3任意一项所述的一种数字时间转换器的校准方法，其特征在于，数字时间转换器进行第一次延迟时，时间数字转换器检测到的相位信息一，与数字时间转换器进行再次延迟时，时间数字转换器检测到的相位信息二为相邻相位或非相邻相位。4. A calibration method for a digital-to-time converter according to any one of claims 1-3, characterized in that phase information one detected by the time-to-digital converter when the digital-to-time converter performs a first delay and phase information two detected by the time-to-digital converter when the digital-to-time converter performs a second delay are adjacent phases or non-adjacent phases. 5.一种数字时间转换器的校准方法，其特征在于，包括以下步骤：5. A method for calibrating a digital-to-time converter, comprising the following steps: 设定预设相位差，并基于所述预设相位差将延迟电路的参考时钟延迟至预设相位一；Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase one based on the preset phase difference; 保持延迟电路的参考时钟位于预设相位一，将数字时间转换器进行第一次延迟至目标检测相位一，并记录时间数字转换器检测到的相位信息一，以及与所述相位信息一对应的数字时间转换器的码值信息一，其中，所述预设相位差为目标检测相位一与预设相位一之间的相位差；Keep the reference clock of the delay circuit at the preset phase one, delay the digital-to-time converter for the first time to the target detection phase one, and record the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one; 基于所述预设相位差将延迟电路的参考时钟延迟至预设相位二；Delaying the reference clock of the delay circuit to a preset phase two based on the preset phase difference; 保持延迟电路的参考时钟位于预设相位二，将数字时间转换器进行再次延迟至目标检测相位二，并记录时间数字转换器检测到的相位信息二，以及与所述相位信息二对应的数字时间转换器的码值信息二，其中，所述预设相位差还为目标检测相位二与预设相位二之间的相位差；Keep the reference clock of the delay circuit at the preset phase 2, delay the digital-to-time converter again to the target detection phase 2, and record the phase information 2 detected by the time-to-digital converter and the code value information 2 of the digital-to-time converter corresponding to the phase information 2, wherein the preset phase difference is also the phase difference between the target detection phase 2 and the preset phase 2; 基于所述相位信息一、码值信息一、相位信息二以及码值信息二，计算数字时间转换器的校准结果。Based on the phase information one, the code value information one, the phase information two and the code value information two, a calibration result of the digital-to-time converter is calculated. 6.一种数字时间转换器的校准系统，其特征在于，所述数字时间转换器的校准系统执行如权利要求1-4任意一项所述的数字时间转换器的校准方法，包括校准逻辑电路、数字时间转换电路、延迟电路和时间数字转换电路；6. A calibration system for a digital-to-time converter, characterized in that the calibration system for a digital-to-time converter performs the calibration method for a digital-to-time converter according to any one of claims 1 to 4, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit; 所述校准逻辑电路用于提供预设相位差；The calibration logic circuit is used to provide a preset phase difference; 所述延迟电路用于基于所述预设相位差将输入的参考时钟延迟至预设相位；The delay circuit is used to delay the input reference clock to a preset phase based on the preset phase difference; 所述数字时间转换电路用于对输入的参考时钟进行多次延迟处理，以将输入的参考时钟分别延迟至目标检测相位一和目标检测相位二，并得到码值信息一和码值信息二，其中，所述预设相位差为目标检测相位一与预设相位之间的相位差；The digital time conversion circuit is used to perform multiple delay processing on the input reference clock to delay the input reference clock to target detection phase 1 and target detection phase 2 respectively, and obtain code value information 1 and code value information 2, wherein the preset phase difference is the phase difference between the target detection phase 1 and the preset phase; 所述时间数字转换电路用于在数字时间转换电路进行第一次延迟处理后，检测到相位信息一，以及在数字时间转换电路进行再次延迟处理后，检测到相位信息二；The time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs a first delay process, and to detect phase information two after the digital-to-time conversion circuit performs a second delay process; 所述校准逻辑电路还用于基于相位信息一、相位信息二、相位信息一所对应的码值信息一和相位信息二所对应的码值信息二输出校准结果。The calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two. 7.根据权利要求6所述的一种数字时间转换器的校准系统，其特征在于，所述延迟电路基于所述预设相位差将参考时钟延迟至预设相位，包括以下步骤：7. A calibration system for a digital-to-time converter according to claim 6, wherein the delay circuit delays the reference clock to a preset phase based on the preset phase difference, comprising the following steps: 延迟电路调整参考时钟的延迟信息；The delay circuit adjusts the delay information of the reference clock; 所述时间数字转换电路检测相位调整信息，当所述相位调整信息达到预设相位差时，参考时钟的延迟信息达到预设相位。The time-to-digital conversion circuit detects phase adjustment information, and when the phase adjustment information reaches a preset phase difference, the delay information of the reference clock reaches a preset phase. 8.根据权利要求6所述的一种数字时间转换器的校准系统，其特征在于，所述校准逻辑电路输出校准结果，包括以下步骤：8. The calibration system of a digital-to-time converter according to claim 6, wherein the calibration logic circuit outputs the calibration result, comprising the following steps: 计算所述相位信息一与相位信息二的相位信息差，并计算所述码值信息一与码值信息二的码值信息差；Calculating a phase information difference between the phase information 1 and the phase information 2, and calculating a code value information difference between the code value information 1 and the code value information 2; 基于所述相位信息差与所述码值信息差计算校准结果，其中，所述校准结果=码值信息差/相位信息差。A calibration result is calculated based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference/phase information difference. 9.一种数字时间转换器的校准系统，其特征在于，所述数字时间转换器的校准系统执行如权利要求5所述的数字时间转换器的校准方法，包括校准逻辑电路、数字时间转换电路、延迟电路和时间数字转换电路；9. A calibration system for a digital-to-time converter, characterized in that the calibration system for a digital-to-time converter performs the calibration method for a digital-to-time converter as claimed in claim 5, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit; 所述校准逻辑电路用于提供预设相位差；The calibration logic circuit is used to provide a preset phase difference; 所述延迟电路用于基于所述预设相位差将输入的参考时钟分别延迟至预设相位一和预设相位二；The delay circuit is used to delay the input reference clock to a preset phase one and a preset phase two respectively based on the preset phase difference; 所述数字时间转换电路用于在延迟电路将输入的参考时钟延迟至预设相位一后，对输入的参考时钟进行第一次延迟处理，以将输入的参考时钟延迟至目标检测相位一，得到码值信息一；在延迟电路将输入的参考时钟延迟至预设相位二后，对输入的参考时钟进行再次延迟处理，以将输入的参考时钟延迟至目标检测相位二，得到码值信息二，其中，所述预设相位差为目标检测相位一与预设相位一之间的相位差，所述预设相位差还为目标检测相位二与预设相位二之间的相位差；The digital time conversion circuit is used to perform a first delay process on the input reference clock after the delay circuit delays the input reference clock to the preset phase one, so as to delay the input reference clock to the target detection phase one, and obtain code value information one; after the delay circuit delays the input reference clock to the preset phase two, perform a second delay process on the input reference clock, so as to delay the input reference clock to the target detection phase two, and obtain code value information two, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one, and the preset phase difference is also the phase difference between the target detection phase two and the preset phase two; 所述时间数字转换电路用于在数字时间转换电路进行第一次延迟处理后，检测到相位信息一，以及在数字时间转换电路进行再次延迟处理后，检测到相位信息二；The time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs a first delay process, and to detect phase information two after the digital-to-time conversion circuit performs a second delay process; 所述校准逻辑电路还用于基于相位信息一、相位信息二、相位信息一所对应的码值信息一和相位信息二所对应的码值信息二输出校准结果。The calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.
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