CN118763115A - SiC MOSFET device with integrated channel accumulation diode - Google Patents
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Abstract
本发明涉及一种集成沟道积累型二极管的SiC MOSFET器件，属于功率半导体器件技术领域。该器件包括源极、N+接触区、P‑body区、CSL层、CSL层两侧的P‑shield区、多晶硅栅介质、连接栅极的多晶硅栅、连接源极的多晶硅栅、N型外延层、N型衬底以及漏极。本发明在器件体内形成沟道积累型二极管，其中沟道积累型二极管由右侧的N+接触区、N+接触区下面的CSL层、N+接触区左右两侧的多晶硅栅介质和连接源极的多晶硅栅组成。本发明可以提升第三象限性能，实现低反向导通电压和反向恢复电荷且避免双极退化问题；在提升第三象限性能的同时减少了开关损耗，降低了栅源电容，增强了高频工作性能。
The present invention relates to a SiC MOSFET device with an integrated channel accumulation diode, and belongs to the technical field of power semiconductor devices. The device includes a source, an N+ contact region, a P-body region, a CSL layer, a P-shield region on both sides of the CSL layer, a polysilicon gate dielectric, a polysilicon gate connected to the gate, a polysilicon gate connected to the source, an N-type epitaxial layer, an N-type substrate, and a drain. The present invention forms a channel accumulation diode in the device body, wherein the channel accumulation diode is composed of an N+ contact region on the right, a CSL layer below the N+ contact region, a polysilicon gate dielectric on the left and right sides of the N+ contact region, and a polysilicon gate connected to the source. The present invention can improve the third quadrant performance, achieve low reverse conduction voltage and reverse recovery charge, and avoid bipolar degradation problems; while improving the third quadrant performance, it reduces switching losses, reduces gate-source capacitance, and enhances high-frequency working performance.
Description
技术领域Technical Field
本发明属于功率半导体器件技术领域，涉及一种集成沟道积累型二极管的SiCMOSFET器件。The invention belongs to the technical field of power semiconductor devices and relates to a SiC MOSFET device with an integrated channel accumulation diode.
背景技术Background Art
作为第三代宽禁带半导体材料的代表之一，碳化硅(Silicon Carbide)材料具有比硅材料更宽的禁带宽度，更高的临界电场、更高的载流子饱和漂移速度、更高的热导率等优点，是制备高压电力电子器件绝佳的材料，在大功率、高温、高压及抗辐照电力电子领域有广阔的应用前景。As one of the representatives of the third generation of wide bandgap semiconductor materials, silicon carbide (SiC) has the advantages of wider bandgap width, higher critical electric field, higher carrier saturation drift velocity, higher thermal conductivity, etc. than silicon materials. It is an excellent material for preparing high-voltage power electronic devices and has broad application prospects in the fields of high-power, high-temperature, high-voltage and radiation-resistant power electronics.
MOSFET是SiC功率器件中应用最广泛的一种栅控型器件结构。由于SiC MOSFET是以单极输运工作机理为特点的器件，没有电荷存储效应，因此相比双极性器件能实现更低的开关损耗和更高的频率特性，同时其低的导通电阻以及优良的高温特性使SiC MOSFET成为新一代极具竞争力的低损耗功率器件。MOSFET is the most widely used gate-controlled device structure in SiC power devices. Since SiC MOSFET is a device characterized by unipolar transport working mechanism and has no charge storage effect, it can achieve lower switching loss and higher frequency characteristics compared to bipolar devices. At the same time, its low on-resistance and excellent high-temperature characteristics make SiC MOSFET a new generation of highly competitive low-loss power devices.
SiC MOSFET主要分为平面型和沟槽型两种。沟槽型MOSFET元胞尺寸相比较平面型MOSFET来说更小，沟道密度更大，导通电阻也更小，但沟槽在沟槽底部和拐角处引来了过多的电场需要增加额外的P+屏蔽层。目前业界领先的英飞凌非对称槽栅MOSFET，通过将P-well区一部分覆盖在沟槽下方用于保护栅氧化层，虽然牺牲了一条沟道，但非对称结构有着更小的元胞宽度，有效提高了器件的沟道密度，弥补了导通电阻上的损失。SiC MOSFET is mainly divided into two types: planar and trench. Compared with planar MOSFET, the cell size of trench MOSFET is smaller, the channel density is higher, and the on-resistance is also lower, but the trench introduces too much electric field at the bottom and corners of the trench, requiring the addition of an additional P+ shielding layer. The industry-leading Infineon asymmetric trench gate MOSFET, which covers part of the P-well area under the trench to protect the gate oxide layer, sacrifices a channel, but the asymmetric structure has a smaller cell width, effectively improving the channel density of the device and compensating for the loss in on-resistance.
随着业界对新一代电力电子系统在功率密度和效率等方面的更高要求，系统核心SiC MOSFET器件不仅需要具有出色的第一象限的电学性能，而且第三象限性能的优化也需特别关注。虽然MOSFET结构存在寄生体二极管，具有反向导通能力，但是由于SiC材料具有禁带宽度较宽的特点，其体二极管开启电压在3伏左右，因此体二极管反向导通时的损耗较大。同时由于SiC外延材料存在堆垛层错等尚未解决的缺陷问题，体二极管长时间工作极易引起双极退化，从而导致MOSFET电学性能也随之退化，如导通电阻增大、阻断泄漏电流增加等等。这将给整个功率系统的性能和可靠性带来严峻的挑战。As the industry places higher demands on the power density and efficiency of the new generation of power electronic systems, the core SiC MOSFET devices of the system not only need to have excellent electrical performance in the first quadrant, but also need to pay special attention to the optimization of the third quadrant performance. Although the MOSFET structure has a parasitic body diode and has the ability to conduct in the reverse direction, due to the wide bandgap of SiC materials, its body diode turn-on voltage is around 3 volts, so the loss of the body diode during reverse conduction is large. At the same time, due to the unresolved defects such as stacking faults in SiC epitaxial materials, the body diode can easily cause bipolar degradation after long-term operation, which leads to the degradation of the electrical performance of the MOSFET, such as increased on-resistance, increased blocking leakage current, etc. This will bring severe challenges to the performance and reliability of the entire power system.
为了优化SiC MOSFET器件在第三象限性能和避免双极退化现象，亟需一种能够抑制体二极管导通带来的双极退化，提高器件的可靠性和性能的SiC MOSFET器件。In order to optimize the performance of SiC MOSFET devices in the third quadrant and avoid bipolar degradation, there is an urgent need for a SiC MOSFET device that can suppress bipolar degradation caused by body diode conduction and improve the reliability and performance of the device.
发明内容Summary of the invention
有鉴于此，本发明的目的在于提供一种集成沟道积累型二极管的SiC MOSFET器件，提升SiC MOSFET第三象限性能(低反向导通电压及反向恢复电荷)，抑制体二极管导通带来的双极退化，提高器件的可靠性；提高开关速度，减少开关损耗，增强高频工作性能。In view of this, the object of the present invention is to provide a SiC MOSFET device with an integrated channel accumulation diode, to improve the third quadrant performance of SiC MOSFET (low reverse conduction voltage and reverse recovery charge), to suppress the bipolar degradation caused by body diode conduction, to improve the reliability of the device; to increase the switching speed, to reduce switching losses, and to enhance the high-frequency working performance.
为达到上述目的，本发明提供如下技术方案：In order to achieve the above object, the present invention provides the following technical solutions:
一种集成沟道积累型二极管的SiC MOSFET器件，包括：A SiC MOSFET device with an integrated channel accumulation diode, comprising:
源极1，位于器件最上方；Source 1, located at the top of the device;
P-shield区8，分为左右两部分，位于源极1下面的左右侧；The P-shield region 8 is divided into two parts, which are located on the left and right sides below the source electrode 1;
多晶硅栅介质7，分为左右两部分，位于源极1下面中部位置；The polysilicon gate dielectric 7 is divided into two parts, the left part and the right part, and is located in the middle below the source 1;
N+接触区2，分为左右两部分，位于源极1下面中部位置，其左侧部分的右表面与多晶硅栅介质7左侧部分的左表面接触，其左侧部分的左表面与P-shield区8左侧部分的右表面接触，其右侧部分的左表面与多晶硅栅介质7左侧部分的右表面接触，其右侧部分的右表面与多晶硅栅介质7右侧部分的左表面接触；The N+ contact region 2 is divided into two parts, the left part and the right part, and is located in the middle below the source 1. The right surface of the left part contacts the left surface of the left part of the polysilicon gate dielectric 7, the left surface of the left part contacts the right surface of the left part of the P-shield region 8, the left surface of the right part contacts the right surface of the left part of the polysilicon gate dielectric 7, and the right surface of the right part contacts the left surface of the right part of the polysilicon gate dielectric 7;
P-body区3，位于N+接触区2左侧部分的下面，其右侧与多晶硅栅介质7左侧部分的左表面接触，其左侧与P-shield区8左侧部分的右表面接触；The P-body region 3 is located below the left portion of the N+ contact region 2, with its right side in contact with the left surface of the left portion of the polysilicon gate dielectric 7, and its left side in contact with the right surface of the left portion of the P-shield region 8;
CSL层4，位于N+接触区2右侧部分、P-body区3和多晶硅栅介质7下面，其左右表面分别与P-shield区8左右侧部分接触；The CSL layer 4 is located at the right side of the N+ contact region 2, below the P-body region 3 and the polysilicon gate dielectric 7, and its left and right surfaces are in contact with the left and right sides of the P-shield region 8 respectively;
连接栅极的多晶硅栅5，位于多晶硅栅介质7左侧部分的内部左边；The polysilicon gate 5 connected to the gate is located on the left side inside the left part of the polysilicon gate dielectric 7;
连接源极的多晶硅栅6，位于多晶硅栅介质7左侧部分的内部右边和多晶硅栅介质7右侧部分内部；The polysilicon gate 6 connected to the source is located on the right side of the left side of the polysilicon gate dielectric 7 and on the right side of the polysilicon gate dielectric 7;
N型外延层9，位于CSL层4下面；N-type epitaxial layer 9, located below the CSL layer 4;
N型衬底10，位于N型外延层9下面；N-type substrate 10, located below the N-type epitaxial layer 9;
漏极11，位于N型衬底10下面；The drain 11 is located below the N-type substrate 10;
所述N+接触区2右侧部分、CSL层4、多晶硅栅6以及位于多晶硅栅6中间的多晶硅栅介质7构成沟道积累型二极管。The right side portion of the N+ contact region 2, the CSL layer 4, the polysilicon gate 6, and the polysilicon gate dielectric 7 located in the middle of the polysilicon gate 6 constitute a channel accumulation diode.
优选的，当器件处于阻断状态下，沟道区域可以被多晶硅栅完全耗尽，从而构建电子势垒，实现常关型器件，同时右侧的P-shield区和CSL层形成的PN结会将沟道全部耗尽，从而进一步保证器件的阻断能力。当器件工作在第三象限时，低开启电压的沟道积累型二极管提前导通，抑制体二极管导通带来的双极退化，提高器件的可靠性和性能。Preferably, when the device is in the blocking state, the channel region can be completely depleted by the polysilicon gate, thereby constructing an electron barrier and realizing a normally-off device. At the same time, the PN junction formed by the P-shield region and the CSL layer on the right will completely deplete the channel, thereby further ensuring the blocking capability of the device. When the device operates in the third quadrant, the low-turn-on voltage channel accumulation diode is turned on in advance, suppressing the bipolar degradation caused by the body diode conduction, and improving the reliability and performance of the device.
优选的，所述CSL层4的厚度T1为1.5～2μm，CSL层两侧的P-shield区8中间的沟道宽度W1为0.8～1.4μm。Preferably, the thickness T1 of the CSL layer 4 is 1.5-2 μm, and the channel width W1 in the middle of the P-shield region 8 on both sides of the CSL layer is 0.8-1.4 μm.
优选的，所述P-shield区8的厚度T2为1.5～2μm，P-shield区8左右部分的宽度W2、W3为0.5～1.6μm。Preferably, the thickness T 2 of the P-shield region 8 is 1.5-2 μm, and the widths W 2 and W 3 of the left and right parts of the P-shield region 8 are 0.5-1.6 μm.
优选的，所述多晶硅栅5的深度T3为1～1.5μm，宽度W4为0.5～1μm；所述多晶硅栅6的深度与多晶硅栅5一致，其左右部分的宽度W5、W8为0.2～0.5μm。Preferably, the depth T3 of the polysilicon gate 5 is 1-1.5 μm, and the width W4 is 0.5-1 μm; the depth of the polysilicon gate 6 is consistent with that of the polysilicon gate 5, and the widths W5 and W8 of the left and right parts thereof are 0.2-0.5 μm.
优选的，所述N+接触区2右侧部分的宽度W6为0.1～0.3μm，所述N+接触区2左侧部分的宽度W7为0.3～0.7μm。Preferably, the width W 6 of the right side of the N+ contact region 2 is 0.1-0.3 μm, and the width W 7 of the left side of the N+ contact region 2 is 0.3-0.7 μm.
优选的，环绕连接栅极的多晶硅栅5的多晶硅栅介质7的环形宽度为50nm；环绕连接源极的多晶硅栅6的多晶硅栅介质7的环形宽度为20～50nm；连接栅极的多晶硅栅5和连接源极的多晶硅栅6中间的多晶硅栅介质7宽度为100nm。Preferably, the annular width of the polysilicon gate dielectric 7 surrounding the polysilicon gate 5 connected to the gate is 50nm; the annular width of the polysilicon gate dielectric 7 surrounding the polysilicon gate 6 connected to the source is 20-50nm; the width of the polysilicon gate dielectric 7 between the polysilicon gate 5 connected to the gate and the polysilicon gate 6 connected to the source is 100nm.
优选的，所述N型外延层9的厚度T4为8～13μm。Preferably, the thickness T4 of the N-type epitaxial layer 9 is 8-13 μm.
优选的，所述N型衬底10的厚度T5为1～3μm。Preferably, the thickness T5 of the N-type substrate 10 is 1-3 μm.
本发明的有益效果在于：本发明提出的SiC MOSFET器件可以提升第三象限性能，实现低反向导通电压和反向恢复电荷且避免双极退化问题；在提升第三象限性能的同时减少了开关损耗，降低了栅源电容，增强了高频工作性能。The beneficial effects of the present invention are as follows: the SiC MOSFET device proposed in the present invention can improve the third quadrant performance, achieve low reverse conduction voltage and reverse recovery charge and avoid the bipolar degradation problem; while improving the third quadrant performance, it reduces switching losses, reduces gate-source capacitance and enhances high-frequency working performance.
本发明的其他优点、目标和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书来实现和获得。Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作优选的详细描述，其中：In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:
图1为本发明集成沟道积累型二极管的SiC MOSFET器件结构截面示意图；FIG1 is a schematic cross-sectional view of a SiC MOSFET device structure with an integrated channel accumulation diode according to the present invention;
图2为传统SiC MOSFET器件结构截面示意图；FIG2 is a schematic cross-sectional view of a conventional SiC MOSFET device structure;
图3为本发明与传统SiC MOSFET的转移特性曲线的对比图；FIG3 is a comparison diagram of transfer characteristic curves of the present invention and conventional SiC MOSFET;
图4为本发明与传统SiC MOSFET的输出特性曲线的对比图；FIG4 is a comparison diagram of output characteristic curves of the present invention and conventional SiC MOSFET;
图5为本发明与传统SiC MOSFET的反向导通特性曲线的对比图；FIG5 is a comparison diagram of reverse conduction characteristic curves of the present invention and conventional SiC MOSFET;
图6为本发明与传统SiC MOSFET的击穿特性曲线的对比图；FIG6 is a comparison diagram of breakdown characteristic curves of the present invention and conventional SiC MOSFET;
图7为本发明与传统SiC MOSFET的开关特性曲线的对比图；FIG7 is a comparison diagram of the switching characteristic curves of the present invention and the conventional SiC MOSFET;
图8为本发明与传统SiC MOSFET的反向恢复特性曲线的对比图；FIG8 is a comparison diagram of reverse recovery characteristic curves of the present invention and conventional SiC MOSFET;
附图标记：1-源极，2-N+接触区，3-P-body区，4-CSL层，5-连接栅极的多晶硅栅，6-连接源极的多晶硅栅，7-多晶硅栅介质，8-P-shield区，9-N型外延层，10-N型衬底，11-漏极。Figure numerals: 1-source, 2-N+ contact region, 3-P-body region, 4-CSL layer, 5-polysilicon gate connected to the gate, 6-polysilicon gate connected to the source, 7-polysilicon gate dielectric, 8-P-shield region, 9-N-type epitaxial layer, 10-N-type substrate, 11-drain.
具体实施方式DETAILED DESCRIPTION
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and the features in the embodiments can be combined with each other without conflict.
其中，附图仅用于示例性说明，表示的仅是示意图，而非实物图，不能理解为对本发明的限制；为了更好地说明本发明的实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；对本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.
本发明实施例的附图中相同或相似的标号对应相同或相似的部件；在本发明的描述中，需要理解的是，若有术语“上”、“下”、“左”、“右”、“前”、“后”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此附图中描述位置关系的用语仅用于示例性说明，不能理解为对本发明的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate directions or positional relationships, they are based on the directions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
如图1所示，本发明实施例提供一种集成沟道积累型二极管的SiC MOSFET器件，具体包括源极1、N+接触区2、P-body区3、CSL层4、CSL层两侧的P-shield区8、多晶硅栅介质7、连接栅极的多晶硅栅5、连接源极的多晶硅栅6、N型外延层9、N型衬底10以及漏极11。其中，右侧的N+接触区2、位于右侧的N+接触区3下面的CSL层4、位于右侧N+接触区2左右两侧的连接源极的多晶硅栅6以及位于右侧N+接触区2和左右两侧的连接源极的多晶硅栅6中间的多晶硅栅介质7构成了沟道积累型二极管。As shown in FIG1 , an embodiment of the present invention provides a SiC MOSFET device with an integrated channel accumulation diode, specifically including a source 1, an N+ contact region 2, a P-body region 3, a CSL layer 4, a P-shield region 8 on both sides of the CSL layer, a polysilicon gate dielectric 7, a polysilicon gate 5 connected to the gate, a polysilicon gate 6 connected to the source, an N-type epitaxial layer 9, an N-type substrate 10, and a drain 11. Among them, the N+ contact region 2 on the right, the CSL layer 4 below the N+ contact region 3 on the right, the polysilicon gate 6 connected to the source on the left and right sides of the N+ contact region 2 on the right, and the polysilicon gate dielectric 7 between the N+ contact region 2 on the right and the polysilicon gate 6 connected to the source on the left and right sides constitute a channel accumulation diode.
本实施例中，CSL层4厚度T1为1.8μm，CSL层两侧的P-shield区8中间的沟道宽度W1为0.9μm。In this embodiment, the thickness T1 of the CSL layer 4 is 1.8 μm, and the channel width W1 in the middle of the P-shield region 8 on both sides of the CSL layer is 0.9 μm.
P-shield区8厚度T2为1.6μm，左P-shield区8宽度W2为0.5μm，右P-shield区8最宽处W3为1.6μm。The thickness T2 of the P-shield region 8 is 1.6 μm, the width W2 of the left P-shield region 8 is 0.5 μm, and the widest point W3 of the right P-shield region 8 is 1.6 μm.
连接栅极的多晶硅栅5深度T3为1μm，宽度W4为0.5μm。The depth T3 of the polysilicon gate 5 connecting the gate electrode is 1 μm, and the width W4 is 0.5 μm.
连接源极的多晶硅栅6深度与连接栅极的多晶硅栅5一致，宽度W5、W8为0.2μm。右侧N+接触区2宽度W6为0.2μm，左侧N+接触区2宽度W7为0.5μm。The depth of the polysilicon gate 6 connected to the source is consistent with that of the polysilicon gate 5 connected to the gate, and the widths W5 and W8 are 0.2 μm. The width W6 of the right N+ contact area 2 is 0.2 μm, and the width W7 of the left N+ contact area 2 is 0.5 μm.
连接栅极的多晶硅栅5左边和下方的多晶硅栅介质7的厚度为50nm，左右连接源极的多晶硅栅6和右侧N+接触区2中间的多晶硅栅介质7的厚度为20nm，左侧多晶硅栅介质7内部连接栅极的多晶硅栅5和连接源极的多晶硅栅6中间的多晶硅栅介质7的厚度为100nm。The thickness of the polysilicon gate dielectric 7 on the left and below the polysilicon gate 5 connected to the gate is 50nm, the thickness of the polysilicon gate 6 connected to the source on the left and right and the polysilicon gate dielectric 7 between the N+ contact area 2 on the right is 20nm, and the thickness of the polysilicon gate dielectric 7 between the polysilicon gate 5 connected to the gate inside the left polysilicon gate dielectric 7 and the polysilicon gate 6 connected to the source is 100nm.
N型外延层9厚度T4为9.2μm，N型衬底10厚度T5为2μm。The thickness T4 of the N-type epitaxial layer 9 is 9.2 μm, and the thickness T5 of the N-type substrate 10 is 2 μm.
本发明通过在器件内形成沟道积累型二极管，当器件工作在第三象限时，低开启电压的沟道积累型二极管提前导通，抑制体二极管导通带来的双极退化，提高器件的可靠性和性能；与此同时，由于采用了分裂栅的结构，减小了栅源电容，加快了开关速度，减少了开关损耗。The present invention forms a channel accumulation diode in the device. When the device operates in the third quadrant, the channel accumulation diode with a low turn-on voltage is turned on in advance, thereby suppressing the bipolar degradation caused by the conduction of the body diode and improving the reliability and performance of the device. At the same time, due to the use of a split gate structure, the gate-source capacitance is reduced, the switching speed is accelerated, and the switching loss is reduced.
通过图3、图4可知，本发明实施例的结构器件栅控能力比传统结构器件(如图2所示)略好，本发明实施例的结构器件阈值电压为6.12V，传统结构器件阈值电压为6.15V。取栅极电压为15V，漏极电压为1V时的比导通电阻，本发明实施例的结构器件比导通电阻为2.99mΩ/cm2，传统结构器件比导通电阻为3.02mΩ/cm2。As shown in FIG3 and FIG4 , the gate control capability of the structure device of the embodiment of the present invention is slightly better than that of the conventional structure device (as shown in FIG2 ), and the threshold voltage of the structure device of the embodiment of the present invention is 6.12 V, while the threshold voltage of the conventional structure device is 6.15 V. When the gate voltage is 15 V and the drain voltage is 1 V, the specific on-resistance of the structure device of the embodiment of the present invention is 2.99 mΩ/cm 2 , while the specific on-resistance of the conventional structure device is 3.02 mΩ/cm 2 .
通过图5可知，本发明实施例的结构器件的反向导通电压明显低于传统结构器件，取100A/cm2时的电压为反向导通电压，本发明实施例的结构器件的反向导通电压为1.42V，传统结构器件的反向导通电压为2.80V，相比传统结构，本发明实施例的结构的反向导通电压减少了49.28％，并且抑制了二极管导通带来的双极退化，提高了器件的可靠性。It can be seen from Figure 5 that the reverse conduction voltage of the structural device of the embodiment of the present invention is significantly lower than that of the traditional structural device. Taking the voltage at 100A/ cm2 as the reverse conduction voltage, the reverse conduction voltage of the structural device of the embodiment of the present invention is 1.42V, and the reverse conduction voltage of the traditional structure device is 2.80V. Compared with the traditional structure, the reverse conduction voltage of the structure of the embodiment of the present invention is reduced by 49.28%, and the bipolar degradation caused by the diode conduction is suppressed, thereby improving the reliability of the device.
图6为本发明实施例的结构和传统结构的击穿特性图，本发明实施例的结构的击穿电压为1790V，传统结构的击穿电压为1823V，本发明实施例的结构击穿电压仅仅略小于传统结构。FIG6 is a breakdown characteristic diagram of the structure of the embodiment of the present invention and the traditional structure. The breakdown voltage of the structure of the embodiment of the present invention is 1790V, and the breakdown voltage of the traditional structure is 1823V. The breakdown voltage of the structure of the embodiment of the present invention is only slightly lower than that of the traditional structure.
图7为本发明实施例的结构和传统结构的开关特性图，本发明实施例的结构的开通损耗为1.892mJ/cm2，关断损耗为2.732mJ/cm2，总开关损耗为4.624mJ/cm2，传统结构的开通损耗为3.212mJ/cm2，关断损耗为4.733mJ/cm2，总开关损耗为7.945mJ/cm2，相比于传统结构，本发明示例结构的开通损耗减少了41.09％，关断损耗减少了42.27％，总开关损耗减少了41.79％。7 is a diagram of switching characteristics of the structure of the embodiment of the present invention and the conventional structure. The turn-on loss of the structure of the embodiment of the present invention is 1.892 mJ/cm 2 , the turn-off loss is 2.732 mJ/cm 2 , and the total switching loss is 4.624 mJ/cm 2 . The turn-on loss of the conventional structure is 3.212 mJ/cm 2 , the turn-off loss is 4.733 mJ/cm 2 , and the total switching loss is 7.945 mJ/cm 2 . Compared with the conventional structure, the turn-on loss of the exemplary structure of the present invention is reduced by 41.09%, the turn-off loss is reduced by 42.27%, and the total switching loss is reduced by 41.79%.
图8为本发明实施例的结构和传统结构的反向恢复特性图，由图可以明显看出本发明实施例的结构的反向恢复电荷少于传统结构。本发明实施例的结构的反向恢复电荷为1.09μC/cm2，传统结构的反向恢复电荷为2.864μC/cm2。相比传统结构，本发明实施例的结构的反向恢复电荷减少了61.94％，极大地改善了反向导通恢复特性。FIG8 is a reverse recovery characteristic diagram of the structure of the embodiment of the present invention and the conventional structure. It can be clearly seen from the figure that the reverse recovery charge of the structure of the embodiment of the present invention is less than that of the conventional structure. The reverse recovery charge of the structure of the embodiment of the present invention is 1.09μC/cm 2 , and the reverse recovery charge of the conventional structure is 2.864μC/cm 2 . Compared with the conventional structure, the reverse recovery charge of the structure of the embodiment of the present invention is reduced by 61.94%, which greatly improves the reverse conduction recovery characteristics.
最后说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.
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| US20160359029A1 (en) * | 2014-02-04 | 2016-12-08 | Maxpower Semiconductor, Inc. | Power mosfet having planar channel, vertical current path, and top drain electrode |
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