CN109599434B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Abstract

The present invention provides a semiconductor device, comprising a first electrode layer, a substrate layer, an N-type drift region, a source structure and a second electrode layer which are stacked in sequence; the source structure comprises independent N+ doped regions, and a P base region arranged around each N+ doped region, and adjacent P base regions are spaced apart from each other; the second electrode layer comprises a source electrode and a gate electrode, the source electrode is arranged corresponding to and connected to the N+ doped region and the P base region, the gate electrode is arranged corresponding to the N+ doped region, the P base region and the N-type drift region between the adjacent P base regions, and the gate electrode is connected to the N-type drift region and the source structure through a gate oxide layer; an _{AlxGa1 -xN} layer is arranged between the gate oxide layer and the N-type drift region, the _{AlxGa1 -xN} layer corresponds to and connects the N-type drift region, and 0＜x≤1. The semiconductor device provided by the present invention has improved accumulation layer resistance and high working efficiency.

Description

Semiconductor device

Technical Field

The present invention relates to a semiconductor device.

Background technique

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is widely used in various fields due to its advantages of fast switching speed and low power consumption. However, MOSFET has the disadvantages of low current density and large on-resistance.

Summary of the invention

In view of the problems existing in the background technology, an embodiment of the present invention provides a semiconductor device to improve current density and reduce on-resistance.

In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device, which includes a first electrode layer, a substrate layer, an N-type drift region, a source structure and a second electrode layer which are stacked in sequence; the source structure includes independent N+ doping regions, and a P base region arranged around each N+ doping region, and adjacent P base regions are spaced apart from each other; the second electrode layer includes a source electrode and a gate electrode, the source electrode is arranged corresponding to and connected to the N+ doping region and the P base region, the gate electrode is arranged corresponding to the N+ doping region, the P base region and the N-type drift region between adjacent P base regions, and the gate electrode is connected to the N-type drift region and the source structure through a gate oxide layer; an _{AlxGa1 -xN} layer is arranged between the gate oxide layer and the N-type drift region, the _{AlxGa1 -xN} layer corresponds to and connects the N-type drift region, 0＜x≤1.

According to one aspect of the embodiment of the present invention, the thickness of the _{AlxGa1 -xN} layer is 5nm-500nm.

According to one aspect of the embodiment of the present invention, the thickness of the _{AlxGa1 -xN} layer is 10 nm to 100 nm.

According to one aspect of the embodiment of the present invention, the thickness of the _{AlxGa1 -xN} layer is 10 nm to 50 nm.

According to one aspect of an embodiment of the present invention, in the _{AlxGa1 -xN} layer, 0.1≤x≤0.5.

According to one aspect of an embodiment of the present invention, adjacent P-base regions are separated by an N-type drift region, and the _{AlxGa1 -xN} layer corresponds to and is disposed on the surface of the N-type drift region between adjacent P-base regions.

According to one aspect of an embodiment of the present invention, a surface of the _{AlxGa1 -xN} layer facing the N-type drift region is flush with a surface of the gate oxide layer facing the N-type drift region.

According to one aspect of an embodiment of the present invention, the length of the _{AlxGa1 -xN} layer is equal to or less than the distance between adjacent P-base regions.

According to one aspect of the embodiments of the present invention, the semiconductor device is a planar metal oxide semiconductor field effect transistor MOSFET or an insulated gate bipolar transistor (IGBT).

According to one aspect of an embodiment of the present invention, adjacent P base regions are separated by a trench, and the interface between the P base region and the N-type drift region is higher than the bottom surface of the trench; the gate electrode, the gate oxide layer and the _{AlxGa1 -xN} layer are arranged in the trench; the gate electrode and the source electrode are isolated by an insulating oxide layer.

According to one aspect of the embodiments of the present invention, the _{AlxGa1 -xN} layer is disposed on the wall surface of the trench below the interface.

According to one aspect of the embodiments of the present invention, the semiconductor device is a trench metal oxide semiconductor field effect transistor MOSFET or an insulated gate bipolar transistor IGBT.

In the semiconductor device provided by the embodiment of the present invention, when in the on state, an accumulation layer is formed between the gate oxide layer and the N-type drift region, and electrons can pass through the source structure and reach the N-type drift region through the accumulation layer. By arranging an _{AlxGa1 -xN} layer between the gate oxide layer and the N-type drift region, and making the _{AlxGa1 -xN} layer correspond to and connect to the N-type drift region, the current density of the accumulation layer can be significantly increased, the on-resistance can be reduced, and the working efficiency of the semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are not drawn according to the true scale.

FIG. 1 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention.

FIG. 2 is a schematic diagram of the structure of a planar MOSFET provided by an embodiment of the present invention.

FIG. 3 is a schematic diagram of the on-resistance of the planar MOSFET in FIG. 2 .

FIG. 4 is a schematic diagram of the structure of a planar IGBT provided by an embodiment of the present invention.

FIG. 5 is a schematic diagram of the structure of a trench MOSFET provided by an embodiment of the present invention.

FIG6 is a schematic diagram of the structure of a trench IGBT provided by another embodiment of the present invention.

Description of labels:

110. a first electrode layer;

120, substrate layer; 121, N+ type substrate layer; 122, N+ type buffer layer; 123, P+ type collector layer;

130, N-type drift region; 131, accumulation layer;

140. Source structure; 141. P base region; 142. N+ doped region;

150, second electrode layer; 151, source electrode; 152, gate electrode; 153, gate oxide layer; 154, _{AlxGa1 -xN} layer; 155, insulating oxide layer.

Detailed ways

The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish an entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, in this article, the meaning of "multiple" is more than two, and "above" and "below" include the number.

FIG. 1 schematically shows a semiconductor device provided by an embodiment of the present invention. Referring to FIG. 1 , a semiconductor device provided by an embodiment of the present invention includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150 which are sequentially stacked; the source structure 140 includes mutually independent N+ doping regions 142 and a P base region 141 which is arranged around each N+ doping region 142, and adjacent P base regions 141 are spaced apart from each other; the second electrode layer 150 includes a source electrode 151 and a gate electrode 152, the source electrode 151 is arranged corresponding to and connected to the N+ doping region 142 and the P base region 141, the gate electrode 152 is arranged corresponding to the N+ doping region 142, the P base region 141 and the N-type drift region 130 between the adjacent P base region 141, and the gate electrode 152 is connected to the N-type drift region 130 and the source structure 140 through a gate oxide layer 153; an _{AlxGa1 -xO2} is arranged between the gate oxide layer 153 and the N-type drift region 130 N layer 154 , 0＜x≤1, Al _x Ga _1-x N layer 154 corresponds to and is connected to the N-type drift region 130 , and the gate oxide layer 153 is disposed to cover the Al _x Ga _1-x N layer 154 .

In the semiconductor device provided by the embodiment of the present invention, when in the on state, an accumulation layer 131 is formed between the gate oxide layer 153 and the N-type drift region 130, and electrons can pass through the source structure 140 and reach the N-type drift region 130 through the accumulation layer 131. By arranging an _{AlxGa1 -xN} layer 154 between the gate oxide layer 153 and the N-type drift region 130, and making the _{AlxGa1 -xN} layer 154 correspond to and connect to the N-type drift region 130, the _{AlxGa1 -xN} layer 154 will generate a high concentration of two-dimensional electron gas (2DEG), thereby significantly improving the current density of the accumulation layer 131, reducing the on-resistance of the semiconductor device, and improving the working efficiency of the semiconductor device.

Furthermore, the thickness of the _{AlxGa1 -xN} layer 154 can be determined according to specific specifications of the semiconductor device through theoretical calculation using simulation software such as SENTAURUS or SILVACO, so as to achieve the purpose of optimally improving the resistance of the accumulation layer.

In some embodiments, the upper limit of the thickness of the _{AlxGa1 -xN} layer 154 may be 30 nm, 50 nm, 70 nm, 100 nm, 120 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm; the lower limit of the thickness of the _{AlxGa1 -xN} layer 154 may be 5 nm, 8 nm, 10 nm, 15 nm, 20 nm, 30 nm, 50 nm, 80 nm, 100 nm, 130 nm, 180 nm, 200 nm. The thickness of the _{AlxGa1 -xN} layer 154 may be any combination of the upper limit or the lower limit.

Optionally, the thickness of the _{AlxGa1 -xN} layer 154 is 5 nm to 500 nm.

Optionally, the thickness of the _{AlxGa1 -xN} layer 154 is 10 nm to 100 nm.

Optionally, the thickness of the _{AlxGa1 -xN} layer 154 is 10 nm to 50 nm.

Optionally, in the _{AlxGa1 -xN} layer 154, 0.1≤x≤0.5.

Optionally, the material of the N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.

The _{AlxGa1 -xN} layer 154 may be formed by deposition or other processes after the P-base region 141 and the N+ doping region 142 are formed.

In some embodiments, adjacent P-base regions 141 are separated by an N-type drift region 130 , and the Al _x Ga _1-x N layer 154 corresponds to and is disposed on the surface of the N-type drift region 130 between adjacent P-base regions 141 .

Furthermore, a surface of the Al _x Ga _1-x N layer 154 facing the N-type drift region 130 is flush with a surface of the gate oxide layer 153 facing the N-type drift region 130 .

Furthermore, the length of the _{AlxGa1 -xN} layer 154 may be equal to or less than the distance L between adjacent P base regions 141. For example, the length of the _{AlxGa1 -xN} layer 154 is equal to the distance L between adjacent P base regions 141, which can better improve the current density of the accumulation layer 131 and reduce the on-resistance of the semiconductor device.

The semiconductor device may be a planar MOSFET. As an example, please refer to FIG. 2 , the planar MOSFET includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150 which are stacked in sequence; the source structure 140 includes mutually independent N+ doping regions 142, and a P base region 141 which is arranged around each N+ doping region 142, and adjacent P base regions 141 are spaced apart by the N-type drift region 130; the second electrode layer 150 The invention comprises a source electrode 151 and a gate electrode 152. The source electrode 151 is arranged corresponding to and connected to the N+ doping region 142 and the P base region 141. The gate electrode 152 is arranged corresponding to the N+ doping region 142, the P base region 141 and the N-type drift region 130 between the adjacent P base regions 141. The gate electrode 152 is connected to the N-type drift region 130 and the source structure 140 through a gate oxide layer 153. An _{AlxGa1 -xN} layer 154 is arranged between the gate oxide layer 153 and the N-type drift region 130. The _{AlxGa1 -xN} layer 154 corresponds to and is connected to the N-type drift region 130. The gate oxide layer 153 covers the _{AlxGa1 -xN} layer 154.

The first electrode layer 110 is a drain electrode.

The substrate layer 120 is an N+ type substrate layer 121. Optionally, the material of the N+ type substrate layer 121 is Si, SiC, GaAs, GaN or other semiconductor materials.

Optionally, the material of the N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.

As shown in Fig. 3, the on-resistance of the planar MOSFET includes source contact resistance _RCS , source resistance _RN+ , channel resistance _RCH , accumulation layer resistance _RA , JFET region resistance _RJFET , drift region resistance _RD , substrate resistance _RSUB , and drain contact resistance _RCD . Since the planar MOSFET is provided with _{AlxGa1 -xN} layer 154 between gate oxide layer 153 and N-type drift region 130, _{AlxGa1 -xN} layer 154 will generate high-concentration two-dimensional electron gas, significantly increase the current density of accumulation layer 131, and significantly reduce the accumulation layer resistance _RA , thereby reducing the on-resistance of the semiconductor device and improving the working efficiency of the semiconductor device.

In order to more clearly show the beneficial effect of the _{AlxGa1 -xN} layer 154, a conventional planar MOSFET without the _{AlxGa1 -xN} layer 154 between the gate oxide layer 153 and the N-type drift region 130 and a planar MOSFET with the _{AlxGa1 -xN} layer 154 between the gate oxide layer 153 and the N-type drift region 130 are provided for comparison, and other features of the conventional planar MOSFET and the planar MOSFET of the embodiment of the present invention are the same. Among them, the cell pitch width W of the conventional planar MOSFET and the planar MOSFET of the embodiment of the present invention is 20μm, the distance L between adjacent P base regions 141 is 6μm, and the thickness of the _{AlxGa1 -xN} layer 154 in the planar MOSFET of the embodiment of the present invention is 30nm, and x=0.3.

For a conventional planar MOSFET, the resistance _RA of the accumulation layer is 0.66mΩ·cm ² at a rated voltage of 50V, accounting for 29.5% of its on-resistance, second only to the channel resistance RC _H . According to the formula _RA =ρ×L=L/(q×μ _n ×n), the number of electrons in the accumulation layer of the conventional planar MOSFET can be obtained as n=L/(q×μ _n × _RA ). The distance between adjacent P base regions 141 is L=6μm, the charge is q=1.6×10 ^-19 C, the resistance _RA of the accumulation layer is 0.66mΩ·cm ² , and the electron mobility μ _n =200cm ² /(V·s) of the accumulation layer is substituted into the formula to obtain the number of electrons in the accumulation layer n=2.84×10 ¹⁶ cm ^-3 .

In the planar MOSFET of the embodiment of the present invention, since an _{AlxGa1 -xN} layer 154 is disposed between the gate oxide layer 153 and the N-type drift region 130, the two-dimensional electron gas generated by the _{AlxGa1 -xN} layer 154 is as high as 5× ^{1019cm -3} , which significantly increases the current density of the accumulation layer 131, and significantly reduces the accumulation layer resistance _RA to only about 6.6× ^10-4mΩ · ^cm2 , which is reduced by 3 orders of magnitude and is basically negligible compared with other components of the on-resistance. Therefore, the on-resistance of the semiconductor device is significantly reduced, and the working efficiency of the semiconductor device is improved.

The semiconductor device may be a planar IGBT. As an example, please refer to FIG. 4 , the planar IGBT includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150 which are stacked in sequence; the source structure 140 includes mutually independent N+ doping regions 142, and a P base region 141 which is arranged around each N+ doping region 142, and adjacent P base regions 141 are spaced apart by the N-type drift region 130; the second electrode layer 150 includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150 ... a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150; the source structure 140 includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150; the source structure 140 includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150; the source structure 140 includes a first electrode layer 110, a substrate layer 12 The source electrode 151 and the gate electrode 152 are provided. The source electrode 151 is provided corresponding to and connected to the N+ doped region 142 and the P base region 141. The gate electrode 152 is provided corresponding to the N+ doped region 142, the P base region 141 and the N-type drift region 130 between the adjacent P base regions 141. The gate electrode 152 is connected to the N-type drift region 130 and the source structure 140 through a gate oxide layer 153. An _{AlxGa1 -xN} layer 154 is provided between the gate oxide layer 153 and the N-type drift region 130. The _{AlxGa1 -xN} layer 154 corresponds to and is connected to the N-type drift region 130. The gate oxide layer 153 covers the _{AlxGa1 -xN} layer 154.

The first electrode layer 110 is a collector.

The substrate layer 120 includes an N+ type buffer layer 122 and a P+ type collector layer 123 which are stacked, wherein the N+ type buffer layer 122 is adjacent to the N− type drift region 130 , and the P+ type collector layer 123 is adjacent to the first electrode layer 110 .

Optionally, the material of the N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.

In some embodiments, adjacent P-base regions 141 are separated by trenches, and the interface between the P-base region 141 and the N-type drift region 130 is higher than the bottom surface of the trenches; the gate electrode 152 , the gate oxide layer 153 and the Al _x Ga _1-x N layer 154 are disposed in the trenches; and the gate electrode 152 and the source electrode 151 are isolated by an insulating oxide layer 154 .

Furthermore, the _{AlxGa1 -xN} layer 154 is disposed on the wall of the trench below the interface between the P-base region 141 and the N-type drift region 130. That is, the _{AlxGa1 -xN} layer 154 is located below the interface between the P-base region 141 and the N-type drift region 130, thereby achieving the effect of improving the resistance _RA of the accumulation layer.

Optionally, the _{AlxGa1 -xN} layer 154 is disposed on the bottom wall surface of the trench and a portion of the side wall surface connected to the bottom wall surface, and the top surface of the _{AlxGa1 -xN} layer 154 is flush with the interface between the P base region 141 and the N-type drift region 130. In other embodiments, the top surface of the _{AlxGa1 -xN} layer 154 may also be lower than the interface between the P base region 141 and the N-type drift region 130. Both can play a good effect of improving the accumulation layer resistance _RA .

It can be understood that the _{AlxGa1 -xN layer 154 can also be disposed on a portion of the wall surface of the trench below the interface between the P-base region 141 and the N-type drift region 130, for example, the AlxGa1-xN} layer 154 can be disposed on the side wall surface of the trench below the interface between the P-base region 141 and the N-type drift region 130, the _{AlxGa1 -xN} layer 154 can be disposed on the bottom wall surface of the trench, or the _{AlxGa1 - xN} layer 154 can be disposed on the side wall surface and a portion of the bottom wall surface of the trench below the interface between the P _- base region 141 and the N-type drift region 130, all of which can have the effect of improving the accumulation layer resistance _RA .

Further, when the _{AlxGa1 -xN} layer 154 is disposed on the sidewall surface of the trench, the surface of the _{AlxGa1 -xN} layer 154 facing the N-type drift region 130 is flush with the surface of the gate oxide layer 153 facing the source structure 140 .

The semiconductor device may be a trench MOSFET. As an example, please refer to FIG. 5 , the trench MOSFET includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150 which are stacked in sequence; the source structure 140 includes mutually independent N+ doping regions 142, and a P base region 141 arranged around each N+ doping region 142, adjacent P base regions 141 are spaced by trenches, and the interface between the P base region 141 and the N-type drift region 130 is higher than the bottom of the trench. The second electrode layer 150 includes a source electrode 151 and a gate electrode 152, the gate electrode 152 is arranged in the groove, and the gate electrode 152 is connected to the N-type drift region 130 and the source structure 140 through a gate oxide layer 153; the notch of the groove is covered with an insulating oxide layer 155, the source electrode 151 is arranged to cover the insulating oxide layer 155, and the source electrode 151 is arranged corresponding to and connected to the N+ doped region 142 and the P base region 141; an _{AlxGa1 -xN} layer 154 is arranged between the gate oxide layer 153 and the N-type drift region 130, the _{AlxGa1 -xN} layer 154 corresponds to and connects the N-type drift region 130, and the gate oxide layer 153 covers the _{AlxGa1 -xN} layer 154.

The first electrode layer 110 is a drain electrode.

The substrate layer 120 is an N+ type substrate layer 121. Optionally, the material of the N+ type substrate layer 121 is Si, SiC, GaAs, GaN or other semiconductor materials.

Optionally, the material of the N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.

The semiconductor device may be a trench IGBT. As an example, please refer to FIG. 6 , the trench IGBT includes a first electrode layer 110, a substrate layer 120, an N-type drift region 130, a source structure 140 and a second electrode layer 150 which are stacked in sequence; the source structure 140 includes mutually independent N+ doping regions 142, and a P base region 141 arranged around each N+ doping region 142, adjacent P base regions 141 are separated by trenches, and the interface between the P base region 141 and the N-type drift region 130 is higher than the bottom surface of the trench The second electrode layer 150 includes a source electrode 151 and a gate electrode 152. The gate electrode 152 is arranged in the groove, and the gate electrode 152 is connected to the N-type drift region 130 and the source structure 140 through a gate oxide layer 153. The notch of the groove is covered with an insulating oxide layer 155. The source electrode 151 is arranged to cover the insulating oxide layer 155, and the source electrode 151 is arranged to correspond to and connect the N+ doped region 142 and the P base region 141. An _{AlxGa1 -xN} layer 154 is arranged between the gate oxide layer 153 and the N-type drift region 130. The _{AlxGa1 -xN} layer 154 corresponds to and connects the N-type drift region 130, and the gate oxide layer 153 covers the _{AlxGa1 -xN} layer 154.

The first electrode layer 110 is a collector.

The substrate layer 120 includes an N+ type buffer layer 122 and a P+ type collector layer 123 which are stacked, wherein the N+ type buffer layer 122 is adjacent to the N− type drift region 130 , and the P+ type collector layer 123 is adjacent to the first electrode layer 110 .

Optionally, the material of the N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.

The above is only a specific implementation of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system described above can refer to the corresponding connection structure in the aforementioned system embodiment, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.

Claims (9)

1. The semiconductor device is characterized by comprising a first electrode layer, a substrate layer, an N-type drift region, a source electrode structure and a second electrode layer which are sequentially stacked; the source electrode structure comprises N+ doped regions independent of each other and P base regions arranged around each N+ doped region, and the adjacent P base regions are spaced from each other; the second electrode layer comprises a source electrode and a gate electrode, the source electrode is arranged corresponding to and connected with the N+ doping region and the P base region, the gate electrode is arranged corresponding to the N+ doping region, the P base region and an N-type drift region between adjacent P base regions, and the gate electrode is connected with the N-type drift region and the source electrode structure through a gate oxide layer;

An Al _xGa_1-x N layer is arranged between the gate oxide layer and the N-type drift region, the Al _xGa_1-x N layer corresponds to and is connected with the N-type drift region, x is more than 0 and less than or equal to 1, so that high-concentration two-dimensional electron gas is generated, and the length of the Al _xGa_1-x N layer is equal to or less than the distance between the adjacent P base regions.

2. The semiconductor device according to claim 1, wherein a thickness of the Al _xGa_1-x N layer is 5 nm to 500 nm;

Or the thickness of the Al _xGa_1-x N layer is 10 nm-100 nm;

Or the thickness of the Al _xGa_1-x N layer is 10 nm-50 nm.

3. The semiconductor device according to claim 1, wherein 0.1.ltoreq.x.ltoreq.0.5 in the Al _xGa_1-x N layer.

4. A semiconductor device according to any one of claims 1-3, wherein adjacent P base regions are separated by the N-type drift region, and the Al _xGa_1-x N layer corresponds to and is disposed on the surface of the N-type drift region between adjacent P base regions.

5. The semiconductor device of claim 4, wherein a surface of the Al _xGa_1-x N layer facing the N-type drift region is flush with a surface of the gate oxide layer facing the N-type drift region.

6. The semiconductor device according to claim 4, wherein the semiconductor device is a planar metal oxide semiconductor field effect transistor MOSFET or an insulated gate bipolar transistor IGBT.

7. A semiconductor device according to any of claims 1-3, wherein adjacent P base regions are separated by a trench, the interface between the P base region and the N-type drift region being higher than the bottom surface of the trench;

The gate electrode, the gate oxide layer and the Al _xGa_1-x N layer are arranged in the groove;

the gate electrode and the source electrode are isolated by an insulating oxide layer.

8. The semiconductor device of claim 7, wherein the Al _xGa_1-x N layer is disposed on a wall of the trench below the interface.

9. The semiconductor device of claim 7, wherein the semiconductor device is a trench metal oxide semiconductor field effect transistor, MOSFET, or an insulated gate bipolar transistor, IGBT.