CN118762737B - A programmable fuse control circuit with isolation function - Google Patents
A programmable fuse control circuit with isolation function Download PDFInfo
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- CN118762737B CN118762737B CN202411240561.9A CN202411240561A CN118762737B CN 118762737 B CN118762737 B CN 118762737B CN 202411240561 A CN202411240561 A CN 202411240561A CN 118762737 B CN118762737 B CN 118762737B
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- fuse
- discharge tube
- control circuit
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
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- Semiconductor Integrated Circuits (AREA)
Abstract
一种带隔离功能的熔丝可编程控制电路，设置有电源隔离控制电路单元、熔丝电路单元以及地线隔离控制电路单元；电源隔离控制电路单元和地线隔离控制电路单元分别与熔丝电路单元连接。该带隔离功能的熔丝可编程控制电路在使用时通过电源隔离控制电路单元对电源隔离控制电路单元中编程电源的隔离和地线隔离控制电路单元对电源隔离控制电路单元中编程地线的隔离，避免芯片在上电过程中或使用过程中受电源毛刺干扰被异常熔断，提高熔丝编程的可靠性。
A fuse programmable control circuit with an isolation function is provided with a power isolation control circuit unit, a fuse circuit unit and a ground isolation control circuit unit; the power isolation control circuit unit and the ground isolation control circuit unit are respectively connected to the fuse circuit unit. When in use, the fuse programmable control circuit with an isolation function isolates the programming power in the power isolation control circuit unit by the power isolation control circuit unit and isolates the programming ground in the power isolation control circuit unit by the ground isolation control circuit unit, thereby preventing the chip from being abnormally fused due to power burr interference during power-on or use, and improving the reliability of fuse programming.
Description
Technical Field
The invention relates to the technical field of programmable control circuits of fuses in integrated circuit designs, in particular to a programmable control circuit of a fuse with an isolation function.
Background
The fuse programming circuit is that a large voltage is applied across the fuse, and when a current flows, electron migration occurs to increase the resistance or generate joule heat to break the fuse. When the fuse is used for data storage, the resistance value of the fuse is maintained or changed, and the read data is based on the fact that the resistance value of the fuse is converted into a voltage value and is compared with a built-in reference voltage, so that whether the state of the fuse is blown or unblown is judged. In the prior art, when a chip is powered on in the circuit operation process, a fuse circuit is wrongly burned, the programming voltage is changed rapidly, the fuse circuit is wrongly burned, and the fuse circuit is damaged by ESD static electricity.
Therefore, it is necessary to provide a fuse programmable control circuit with isolation function to overcome the deficiencies of the prior art.
Disclosure of Invention
The invention aims to provide a fuse programmable control circuit with an isolation function, which can prevent a chip from being abnormally blown by power supply burr interference in the power-on process or the use process by increasing the isolation of a programming power supply and the isolation of a programming ground wire and improve the reliability of fuse programming.
The above object of the present invention is achieved by the following means. A programmable fuse control circuit with isolation function is provided, which comprises a power isolation control circuit unit, a fuse circuit unit and a ground isolation control circuit unit, wherein the power isolation control circuit unit and the ground isolation control circuit unit are respectively connected with the fuse circuit unit.
Preferably, the power isolation control circuit unit is provided with a PS control signal, an inverter INV1, a chip U1, a pull-down resistor R1, a pull-up tube PMOS1, a power supply control tube PMOS2, a discharge tube NOMS1 and a discharge tube NMOS2, wherein the output end of the PS control signal is connected with the input end of the inverter INV1, the ground wire of the inverter INV1 is grounded GND, the power supply end of the inverter INV1 is connected with the ground wire isolation control circuit unit, the power supply end of the inverter INV1 is connected with a power supply VDD, the output end of the inverter INV1 is respectively connected with the 1 pin of the chip U1 and the grid electrode of the discharge tube NMOS2, the 2 pin of the chip U1 is respectively connected with the source electrode of the pull-up tube PMOS1, the source electrode of the power supply control tube PMOS2, the ground wire isolation control circuit unit and the fuse circuit unit, and the 2 pin of the chip U1 is connected with a power supply VDDQ;
The 3 pins of the chip U1 are respectively connected with the drain electrode of the pull-up tube PMOS1, the gate electrode of the power supply control tube PMOS2, and the gate electrode of the discharge tube NMOS1, the 4 pins of the chip U1 are grounded GND, the source electrode of the pull-up tube PMOS1 is connected with one end of the pull-down resistor R1, the other end of the pull-down resistor R1 is grounded GND, the source electrode of the discharge tube NMOS2 is grounded GND, and the drain electrode of the discharge tube NMOS2 is respectively connected with the drain electrode of the discharge tube NOMS1, the drain electrode of the power supply control tube PMOS2, and the fuse circuit unit, and the drain electrode of the discharge tube NMOS2 is connected with the power supply VQR.
Preferably, the fuse circuit unit is provided with a BL bit line, a WL word line, a power supply control tube PMOS5, a power supply control tube PMOS6, a discharge tube NMOS7, a resistor R3 and a fuse, wherein the source electrode of the power supply control tube PMOS5 is respectively connected with the drain electrode of the power supply control tube PMOS5, the pin 2 of the chip U1 and the ground wire isolation control circuit unit, the grid electrode of the power supply control tube PMOS5 is respectively connected with one end of the resistor R3 and the grid electrode of the discharge tube NMOS7, the power supply control tube PMOS5 is connected with a power supply VDDQ,
The other end of the resistor R3 is connected with the source electrode of the discharge tube NMOS7, the other end of the resistor R3 is connected with the ground wire GND, the drain electrode of the discharge tube NMOS7 is respectively connected with the grid electrode and the WL word line of the discharge tube NMOS6, the source electrode of the discharge tube NMOS6 is connected with the ground wire GND1, the drain electrode of the discharge tube NMOS6 is connected with one end of a fuse, the other end of the fuse is connected with the drain electrode of the power supply control tube PMOS6, the grid electrode of the power supply control tube PMOS6 is connected with the BL bit line, the source electrode of the power supply control tube PMOS6 is connected with the drain electrode of the discharge tube NMOS2, and the source electrode of the power supply control tube PMOS6 is connected with the power supply VQR.
Preferably, the ground isolation control circuit unit is provided with a power supply control tube PMOS3, a power supply control tube PMOS4, a discharge tube NMOS3, a discharge tube NMOS4, a discharge tube NMOS5 and a resistor R2, wherein the source electrode of the power supply control tube PMOS4 is respectively connected with the drain electrode of the power supply control tube PMOS4 and the pin 2 of the chip U1, the source electrode of the power supply control tube PMOS4 is connected with a power supply VDDQ,
The grid electrode of the power supply control tube PMOS4 is respectively connected with one end of a resistor R2 and the grid electrode of the discharge tube NMOS5, the other end of the resistor R2 is respectively connected with the source electrode of the discharge tube NMOS5 and the source electrode of the power supply control tube NMOS4, the other end of the resistor R2 is connected with a ground wire GND, the source electrode of the power supply control tube NMOS3 is connected with the drain electrode of the power supply control tube NMOS3 and the source electrode of the power supply control tube PMOS3, the source electrode of the power supply control tube PMOS3 is connected with the power supply end of the inverter INV1, the drain electrode of the power supply control tube PMOS3 is respectively connected with the drain electrode of the discharge tube NMOS5 and the grid electrode of the discharge tube NMOS4, and the drain electrode of the discharge tube NMOS4 is connected with the ground wire GND1.
Wherein, 3 pins of the chip U1 are set as an output end Q.
Wherein, the 1 pin of the chip U1 is set as the input end D.
Wherein, the chip U1 is set as LEVEL SHIFT level converter.
The fuse programmable control circuit with the isolation function is provided with a power isolation control circuit unit, a fuse circuit unit and a ground wire isolation control circuit unit, wherein the power isolation control circuit unit and the ground wire isolation control circuit unit are respectively connected with the fuse circuit unit. When the fuse programmable control circuit with the isolation function is used, the isolation of a programming power supply in the power supply isolation control circuit unit and the isolation of a programming ground wire in the power supply isolation control circuit unit are realized through the power supply isolation control circuit unit, so that the chip is prevented from being abnormally blown by the interference of power supply burrs in the power-on process or the use process, and the reliability of fuse programming is improved.
Drawings
The invention is further illustrated by the accompanying drawings, which are not to be construed as limiting the invention in any way.
Fig. 1 is a schematic diagram of a module connection structure of an embodiment 1 of a fuse programmable control circuit with isolation function according to the present invention.
Fig. 2 is a circuit diagram of a power isolation control circuit unit of embodiment 1 of a fuse programmable control circuit with isolation function according to the present invention.
Fig. 3 is a circuit diagram of a ground isolation control circuit unit of embodiment 1 of a fuse programmable control circuit with isolation function according to the present invention.
Fig. 4 is a circuit diagram of a fuse circuit unit of embodiment 1 of a fuse programmable control circuit with isolation function according to the present invention.
Reference numerals illustrate:
a power isolation control circuit unit 100, a fuse circuit unit 200, and a ground isolation control circuit unit 300.
Detailed Description
The invention will be further described with reference to the following examples.
Example 1
As shown in fig. 1, a fuse programmable control circuit with isolation function is provided with a power isolation control circuit unit 100, a fuse circuit unit 200 and a ground isolation control circuit unit 300, wherein the power isolation control circuit unit 100 and the ground isolation control circuit unit 300 are respectively connected with the fuse circuit unit 200. In use, the power supply isolation control circuit unit 100 effects isolation of the fuse programming power supply of the fuse circuit unit 200, and the ground isolation control circuit unit 300 effects isolation of the programming ground.
Specifically, as shown in fig. 2, the power isolation control circuit unit 100 is provided with a PS control signal, an inverter INV1, a chip U1, a pull-down resistor R1, a pull-up transistor PMOS1, a power control transistor PMOS2, a discharge transistor NOMS1 and a discharge transistor NMOS2, wherein an output end of the PS control signal is connected to an input end of the inverter INV1, a ground line of the inverter INV1 is grounded GND, a power supply end of the inverter INV1 is connected to the ground line isolation control circuit unit 300, a power supply end of the inverter INV1 is connected to a power supply VDD, an output end of the inverter INV1 is connected to a pin 1 of the chip U1 and a gate of the discharge transistor NMOS2, a pin 2 of the chip U1 is connected to a source of the pull-up transistor PMOS1, a source of the power control transistor PMOS2, the ground line isolation control circuit unit 300 and the fuse circuit unit 200, and a pin 2 of the chip U1 is connected to a power supply VDDQ;
The 3 pin of the chip U1 is connected to the drain of the pull-up transistor PMOS1, the gate of the power supply control transistor PMOS2, and the gate of the discharge transistor NMOS1, the 4 pin of the chip U1 is grounded GND, the source of the pull-up transistor PMOS1 is connected to one end of the pull-down resistor R1, the other end of the pull-down resistor R1 is grounded GND, the source of the discharge transistor NMOS2 is grounded GND, and the drain of the discharge transistor NMOS2 is connected to the drain of the discharge transistor NOMS1, the drain of the power supply control transistor PMOS2, and the fuse circuit unit 200, respectively, and the drain of the discharge transistor NMOS2 is connected to the power supply VQR. Wherein, the chip U1 is set as LEVEL SHIFT level converter, the 3 pin of the chip U1 is set as the output terminal Q, and the 1 pin of the chip U1 is set as the input terminal D.
When the fuse is used, the power supply control tube PMOS2 separates the VDDQ from the fuse programming power supply VQR, and the switch state of the PMOS2 tube is controlled by a PS control signal in the power-on process of the VDD, so that the VDDQ is blocked from entering the fuse in the power-on process of the VDD.
In the power isolation control circuit unit 100, when the power up at VDD is completed and VDDQ is in the power up process, PS is set to a low level, and is output to a high level through the inverter INV1, and the power control tube PMOS2 is turned off through the level conversion module, so as to prevent the VDDQ program voltage from entering the fuse inside, whereas when PS is set to a high level, the power control tube PMOS2 is turned on, and the VDDQ program voltage enters the fuse inside. If VDD is not powered up or is not stable, PS does not act, and VDDQ is powered up, then PMOS2 is controlled to be in an off state through a pull-up tube PMOS1 tube and a resistor R1, so that VDDQ enters the fuse, that is, VQR is in a floating state. The discharge tube NMOS1 tube discharges VQR when VDDQ is present, and the discharge tube NMOS2 tube discharges VQR when VDDQ is in a floating state.
Specifically, as shown in fig. 4, the fuse circuit unit 200 is provided with a BL bit line, a WL word line, a power supply control tube PMOS5, a power supply control tube PMOS6, a discharge tube NMOS7, a resistor R3, and a fuse, wherein a source of the power supply control tube PMOS5 is connected to a drain of the power supply control tube PMOS5, a pin 2 of the chip U1, and the ground isolation control circuit unit 300, a gate of the power supply control tube PMOS5 is connected to one end of the resistor R3 and a gate of the discharge tube NMOS7, the power supply control tube PMOS5 is connected to a power supply VDDQ,
The other end of the resistor R3 is connected with the source electrode of the discharge tube NMOS7, the other end of the resistor R3 is connected with the ground wire GND, the drain electrode of the discharge tube NMOS7 is respectively connected with the grid electrode and the WL word line of the discharge tube NMOS6, the source electrode of the discharge tube NMOS6 is connected with the ground wire GND1, the drain electrode of the discharge tube NMOS6 is connected with one end of a fuse, the other end of the fuse is connected with the drain electrode of the power supply control tube PMOS6, the grid electrode of the power supply control tube PMOS6 is connected with the BL bit line, the source electrode of the power supply control tube PMOS6 is connected with the drain electrode of the discharge tube NMOS2, and the source electrode of the power supply control tube PMOS6 is connected with the power supply VQR. The connection method of the power supply control tube is equivalent to MOS capacitance, when the program voltage has the working conditions of voltage fluctuation, burr interference or ESD, the gate voltage of the discharge tube NMOS7 at one end of the capacitance also rises rapidly, the discharge tube NMOS7 is opened, the gate voltage of the discharge tube NMOS6 is pulled down, the discharge tube NMOS6 is turned off, and the current path from the fuse to the ground is blocked.
Specifically, as shown in fig. 3, the ground isolation control circuit unit 300 is provided with a power supply control tube PMOS3, a power supply control tube PMOS4, a discharge tube NMOS3, a discharge tube NMOS4, a discharge tube NMOS5, and a resistor R2, wherein the source of the power supply control tube PMOS4 is connected to the drain of the power supply control tube PMOS4 and the pin 2 of the chip U1, respectively, the source of the power supply control tube PMOS4 is connected to the power supply VDDQ,
The grid electrode of the power supply control tube PMOS4 is respectively connected with one end of a resistor R2 and the grid electrode of the discharge tube NMOS5, the other end of the resistor R2 is respectively connected with the source electrode of the discharge tube NMOS5 and the source electrode of the power supply control tube NMOS4, the other end of the resistor R2 is connected with a ground wire GND, the source electrode of the power supply control tube NMOS3 is connected with the drain electrode of the power supply control tube NMOS3 and the source electrode of the power supply control tube PMOS3, the source electrode of the power supply control tube PMOS3 is connected with the power supply end of the inverter INV1, the drain electrode of the power supply control tube PMOS3 is respectively connected with the drain electrode of the discharge tube NMOS5 and the grid electrode of the discharge tube NMOS4, and the drain electrode of the discharge tube NMOS4 is connected with the ground wire GND1. The discharge tube NMOS4 separates the external ground GND from the fuse ground GND1, and when the program voltage VDDQ changes rapidly, the fuse ground GND1 is disconnected by controlling the discharge tube NMOS 4. When VDDQ changes rapidly, the voltage of the grid electrode (point B) of the discharge tube NMOS5 at one end of the MOS capacitor also rises rapidly, the discharge tube NMOS5 is opened, the point C voltage is pulled down, the power supply control tube PMOS4 is turned off, and the isolation of the fuse ground GND1 and the external ground GND is realized.
In fig. 3 of the present technology, the connection of the power supply control tube PMOS4 is equivalent to a MOS capacitor, and when the VDDQ programming voltage changes rapidly, the voltage of the gate (point B) of the discharge tube NMOS5 at one end of the power supply control tube PMOS4, which is relatively equivalent to the capacitor, also rises rapidly, the discharge tube NMOS5 is turned on, the point C voltage pulls down, the discharge tube NMOS4 is turned off, the isolation between the fuse ground GND1 and the external ground GND is achieved, and the fuse is prevented from being burned by mistake due to the large current flowing through the fuse. When VDDQ is stable, the power supply control tube PMOS4 serving as a capacitor blocks VDDQ from being connected with point B, the pull-down resistor R2 pulls down the voltage of point B to ground, the discharge tube NMOS5 is turned off, the path from point C to ground is disconnected, the discharge tube NMOS3 adopting the diode connection method pulls down the gate voltage of the power supply control tube PMOS3 to ground, the pipe of the power supply control tube PMOS3 is turned on, the voltage of point C is lifted up to open the discharge tube NMOS4, so that the ground lines GND1 and GND are turned on, and the path from the power supply to GND through the fuse is normal when programming and reading operations are performed.
In fig. 4, the connection of the power supply control tube PMOS5 is equivalent to a MOS capacitor, and when the program voltage VDDQ has voltage fluctuation, glitch, ESD, or other working conditions, the gate voltage (point D) of the discharge tube NMOS7 at one end equivalent to the capacitor power supply control tube PMOS5 also rises rapidly, the discharge tube NMOS7 is turned on, the gate voltage of the discharge tube NMOS6 is pulled down, the discharge tube NMOS6 is turned off, and the current path from the fuse to ground is blocked. When VDDQ is in steady state, resistor R3 pulls the D point voltage low turning off NMOS 7. The WL word line is active high and when the WL word line is high, the discharge tube NMOS6 is in an open state. The BL bit line is active low, and when BL bit line is low, power control transistor PMOS6 is turned on, and internal programming voltage VQR flows through Fuse fuses for programming or reading.
The fuse programmable control circuit with the isolation function is provided with a power isolation control circuit unit, a fuse circuit unit and a ground wire isolation control circuit unit, wherein the power isolation control circuit unit and the ground wire isolation control circuit unit are respectively connected with the fuse circuit unit, and the fuse programmable control circuit with the isolation function controls the switching state of a power control tube PMOS2 by adding a PS control signal, so that VDDQ is blocked from entering the fuse in the VDD power-up process, and the fuse is wrongly burned in the chip power-up process. Meanwhile, when VDDQ changes rapidly, the discharge tube NMOS4 is controlled to disconnect the fuse wire, so that the fuse wire is prevented from being wrongly burned due to too rapid change of the programming power supply VDDQ, and a protection circuit is added on the WL word line, and when the programming voltage has the working conditions of voltage fluctuation, burr interference or ESD, and the like, the fuse wire current loop is turned off, so that the fuse wire is prevented from being wrongly burned. And in subsequent functional expansion, can be easily grasped by a designer and applied to other integrated circuit designs.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411240561.9A CN118762737B (en) | 2024-09-05 | 2024-09-05 | A programmable fuse control circuit with isolation function |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411240561.9A CN118762737B (en) | 2024-09-05 | 2024-09-05 | A programmable fuse control circuit with isolation function |
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| CN118762737A CN118762737A (en) | 2024-10-11 |
| CN118762737B true CN118762737B (en) | 2025-02-11 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734761A (en) * | 2004-08-04 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Fuse circuit and electric fuse circuit with electrostatic discharge protection |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100267492B1 (en) * | 1998-06-11 | 2000-11-01 | 김영환 | Repair circuit with anti-fuse programming in redundency cell and manufacturing method thereof |
| US20110134707A1 (en) * | 2007-11-02 | 2011-06-09 | Saeng Hwan Kim | Block isolation control circuit |
| CN102427076B (en) * | 2011-11-22 | 2013-06-26 | 中国电子科技集团公司第五十八研究所 | Gate oxide breakdown antifuse configuration unit structure applied to FPGA |
| CN103730163B (en) * | 2013-12-27 | 2017-02-15 | 深圳市国微电子有限公司 | Programmable storage system |
| US10163916B2 (en) * | 2015-12-16 | 2018-12-25 | NEO Semiconductor, Inc. | Compact anti-fuse memory cell using CMOS process |
| CN105575436B (en) * | 2016-02-23 | 2023-06-23 | 中国科学院半导体研究所 | Programmable control polycrystalline fuse circuit and integrated circuit including the circuit |
| CN114171096A (en) * | 2021-12-03 | 2022-03-11 | 无锡中微亿芯有限公司 | Reading time controllable anti-fuse memory reading circuit |
| CN115019864A (en) * | 2022-05-30 | 2022-09-06 | 上海华力集成电路制造有限公司 | Blown fuse programming unit, programming circuit, control circuit and array |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1734761A (en) * | 2004-08-04 | 2006-02-15 | 台湾积体电路制造股份有限公司 | Fuse circuit and electric fuse circuit with electrostatic discharge protection |
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