CN111881638B - Programmable circuit, programming method thereof and reading method thereof - Google Patents
Programmable circuit, programming method thereof and reading method thereof Download PDFInfo
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- CN111881638B CN111881638B CN202010760424.3A CN202010760424A CN111881638B CN 111881638 B CN111881638 B CN 111881638B CN 202010760424 A CN202010760424 A CN 202010760424A CN 111881638 B CN111881638 B CN 111881638B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/343—Logical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention provides a programmable circuit, a programming method and a reading method thereof, wherein the programmable circuit comprises: the first selecting unit, the second selecting unit, the first programming unit, the second programming unit, the first control unit and the second control unit. The first selection unit, the first programming unit and the first control unit are connected in series; the first end of the second programming unit is connected with the first programming unit and the first control unit; the second end of the second programming unit is connected with the second selecting unit and the second control unit. The first selection unit, the first programming unit, and the second control unit form a path when the first programming unit is programmed. The second selection unit, the second programming unit, and the first control unit form a path when the second programming unit is programmed. According to the invention, by arranging the two programming units and forming the two programming paths, the function of twice programming is realized, and the performance of the device is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a programmable circuit, a programming method and a reading method thereof.
Background
Common one-time programmable memory (One Time Programable, OTP) structures include two broad classes, antifuse (Anti-ELECTRICALLY PROGRAMMABLE FUSE, anti-Efuse) and electrical fuse (ELECTRICALLY PROGRAMMABLE FUSE, efuse). The antifuse is programmed by breaking an ONO (Oxide-Nitride-Oxide) insulating layer between a polysilicon layer and an n+ diffusion layer such that the resistance value between the two layers changes, resulting in a change in the equivalent logic value. The electric fuse is programmed by blowing the fuse according to the Electromigration (EM) characteristic, so as to change the resistance value at two ends of the fuse. Both OTPs adopt standard CMOS technology, the cell area is small, the total cost is reduced, the safety is good, and especially, the internal interconnection structure of the OTP and the cell has the natural radiation-proof capability and is relatively not influenced by electromagnetic radiation, thus the OTP has special attractive force for aerospace, military, nuclear industry and other applications, but the defects of the OTP structure are obvious: the memory can be programmed only once, so that the field use conditions of users and the production test capability of products are greatly limited, and the redundancy is poor.
Therefore, in order to solve the above-mentioned problems, a re-programmable circuit is required to realize the secondary programming, and enhance the device performance.
Disclosure of Invention
The invention aims to provide a programmable circuit, a programming method and a reading method thereof, so as to solve the problem of how to realize the secondary programming of an anti-fuse circuit.
In order to solve the above technical problems, the present invention provides a programmable circuit, comprising: the device comprises a first selection unit, a second selection unit, a first programming unit, a second programming unit, a first control unit and a second control unit;
the first selection unit, the first programming unit and the first control unit are sequentially connected in series; the first end of the second programming unit is connected with the first programming unit and the first control unit; the second end of the second programming unit is connected with the second selection unit and the second control unit;
the first selecting unit, the first programming unit, and the second control unit form a path when programming the first programming unit;
The second selecting unit, the second programming unit, and the first control unit form a path when the second programming unit is programmed.
Optionally, in the programmable circuit, the first programming unit is an antifuse transistor, and the second programming unit is an electric fuse; the first selection unit, the second selection unit, the first control unit and the second control unit are all MOS tubes.
Optionally, in the programmable circuit, a source of the first selection unit is connected to a gate of the first programming unit.
Optionally, in the programmable circuit, a source of the first programming unit is connected to a drain of the first control unit.
Optionally, in the programmable circuit, a first end of the second programming unit is connected to a source of the first programming unit and a drain of the first control unit; the second end of the second programming unit is connected with the source electrode of the second selecting unit and the drain electrode of the second control unit.
Optionally, in the programmable circuit, a source of the first control unit and a source of the second control unit are grounded.
Optionally, in the programmable circuit, the programmable circuit further includes an output comparing unit, and the output comparing unit is connected to the drain of the first selecting unit and the gate of the first programming unit; the output comparison unit is used for providing reference current and comparing the reference current with the current value flowing through the first programming unit so as to convert the reference current into logic value output.
Optionally, in the programmable circuit, the output comparing unit includes a comparator, a reference resistor, and a comparing transistor; wherein,
The first end of the comparator is connected with the drain electrode of the first selection unit and the grid electrode of the first programming unit;
The second end of the comparator is connected with the reference resistor and the comparison transistor in series; the drain electrode of the comparison transistor is connected with the reference resistor, the source electrode of the comparison transistor is grounded, and the grid electrode of the comparison transistor is connected with a reference power supply;
The third terminal of the comparator is an output port.
Based on the same inventive concept, the invention also provides a programming method of the programmable circuit, comprising the following steps: first programming and second programming; wherein,
In the first programming, the first selection unit and the second control unit are turned on, the second selection unit and the first control unit are turned off, so that the first programming unit is changed from a high resistance state to a low resistance state, and the second programming unit is kept in the low resistance state, and then the first selection unit, the first programming unit, the second programming unit and the second control unit form a passage;
In the second programming, after the first programming is executed, the first programming unit keeps a low resistance state, the second selecting unit and the first control unit are conducted, the first selecting unit and the second control unit are disconnected, and then a passage is formed among the second selecting unit, the second programming unit and the first control unit, so that the second programming unit is changed from the low resistance state to the high resistance state.
Based on the same inventive concept, the invention also provides a method for reading a programmable circuit, comprising the following steps: turning on the second control unit, and turning off the first selection unit, the second selection unit and the first control unit so that the first programming unit, the second programming unit and the second control unit form a passage; and acquiring a current value in the path, and converting the current value into a logic value and outputting the logic value.
In summary, the present invention provides a programmable circuit, a programming method and a reading method thereof, wherein the programmable circuit includes: the first selecting unit, the second selecting unit, the first programming unit, the second programming unit, the first control unit and the second control unit. The first selection unit, the first programming unit and the first control unit are connected in series; the first end of the second programming unit is connected with the first programming unit and the first control unit; the second end of the second programming unit is connected with the second selecting unit and the second control unit. The first selecting unit, the first programming unit, and the second control unit form a path when the first programming unit is programmed. The second selecting unit, the second programming unit, and the first control unit form a path when the second programming unit is programmed. According to the invention, by arranging the two programming units and forming the two programming paths, the function of twice programming is realized, and the performance of the device is improved.
Drawings
FIG. 1 is an antifuse circuit diagram of an embodiment of the present invention;
FIG. 2 is a programmable circuit diagram of an embodiment of the present invention;
FIG. 3 is a schematic diagram of an output comparing unit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a first programming-time programmable circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a second programming-time programmable circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a programmable circuit read according to an embodiment of the invention;
Wherein, the reference numerals illustrate:
a 10-antifuse transistor; 101-a first selection unit; 102-a second selection unit; 200-a first programming unit; 300-a second programming unit; 401-a first control unit; 402-a second control unit; 500-output comparison unit.
Detailed Description
Referring to fig. 1, a conventional antifuse circuit is generally an antifuse transistor 10 connected to an NMOS transistor. The source of the antifuse transistor 10 is connected to the drain of an NMOS transistor, the source of which is grounded. When the gate of the anti-fuse transistor 10 is connected to a high level, the gate of the NMOS transistor is also connected to a high level, so that the anti-fuse transistor 10 is turned on, the anti-fuse transistor 10 is turned from a high resistance state to a low resistance state, and the NMOS transistor is turned on, the anti-fuse circuit is turned from the high resistance state to the low resistance state, so that one-time programming is realized, but the anti-fuse transistor 10 can only perform one-time programming, so that the conventional anti-fuse circuit cannot realize secondary programming, and has lower expansibility of devices and higher cost.
Therefore, in order to solve the technical problem, the invention provides a novel programmable circuit to realize the secondary programming function of the circuit, improve the device performance and enhance the expansibility of the circuit.
The following describes a programmable circuit, a programming method and a reading method thereof in further detail with reference to the drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
In order to solve the above technical problems, the present embodiment provides a programmable circuit. Referring to fig. 2, the programmable circuit includes: the first selecting unit 101, the second selecting unit 102, the first programming unit 200, the second programming unit 300, the first control unit 401, and the second control unit 402.
The first selection unit 101, the first programming unit 200, and the first control unit 401 are sequentially connected in series. A first end of the second programming unit 300 is connected to the first programming unit 200 and the first control unit 401; a second terminal of the second programming unit 300 is connected to the second selection unit 102 and the second control unit 402.
When programming the first programming unit 200, the first selecting unit 101, the first programming unit 200, and the second control unit 402 form a path;
When programming the second programming unit 300, the second selecting unit 102, the second programming unit 300, and the first control unit 402 form a path.
Specifically, in the present embodiment, the first programming unit 200 is an antifuse transistor, and the second programming unit 300 is an electric fuse. When the anti-fuse transistor is turned on, the anti-fuse transistor changes from a high resistance state to a low resistance state; when the electric fuse is turned on, the electric fuse changes from a low resistance state to a high resistance state. Further, the first selecting unit 101, the second selecting unit 102, the first control unit 401, and the second control unit 402 are all MOS transistors. In one embodiment, the first selecting unit 101 is a PMOS transistor, the second selecting unit 102 is a PMOS transistor, the first controlling unit 401 is an NMOS transistor, and the second controlling unit 402 is an NMOS transistor.
With continued reference to fig. 2, the source of the first selection unit 101 is connected to the gate of the first programming unit 200. The source of the first programming unit 200 is connected to the drain of the first control unit 401. The first terminal of the second programming unit 300 is connected to the source of the first programming unit 200 and the drain of the first control unit 401. A second terminal of the second programming unit 300 is connected to the source of the second selecting unit 102 and the drain of the second control unit 402. The source of the first control unit 401 and the source of the second control unit 402 are both grounded.
In addition, the programmable circuit further includes an output comparing unit 500, and the output comparing unit 500 is connected to the drain of the first selecting unit 101 and the gate of the first programming unit 200; the output comparing unit 500 is used for providing a reference current and comparing with the current value flowing through the first programming unit 200 to convert into a logic value output.
Specifically, referring to fig. 3, the output comparing unit 500 includes a comparator 501, a reference resistor 502, and a comparing transistor 503. Optionally, the comparison transistor 503 is an NMOS transistor. Wherein, the first end a of the comparator 501 is connected to the drain of the first selection unit 101 and the gate of the first programming unit 200. The second terminal b of the comparator 501 is connected in series with the reference resistor 502 and the comparison transistor 503. Specifically, the drain of the comparison transistor 503 is connected to the reference resistor 502, the source of the comparison transistor 503 is grounded, and the gate of the comparison transistor 503 is connected to a reference power supply. The third terminal c of the comparator 503 is an output port.
The present embodiment is implemented by switching in the existing antifuse circuit the second programming unit 300, the second selecting unit 102, and the second control unit 402. Wherein the electric fuse in the second programming unit 300 and the antifuse transistor in the first programming unit 200 are all one-time programmable devices. When the antifuse transistor is turned on, the antifuse transistor changes from a high-resistance state to a low-resistance state; when the electric fuse is turned on, the electric fuse changes from a low resistance state to a high resistance state. The programmable circuit provided by the embodiment can realize the second programming through the electric fuse after the programming of the anti-fuse transistor is completed by adding the electric fuse.
Based on the same inventive concept, the present embodiment further provides a programming method of a programmable circuit, including: first programming and second programming. Wherein,
Referring to fig. 4 (the broken line is shown to be open), in the first programming, the first selecting unit 101, the first programming unit 200, the second programming unit 300 and the second control unit 402 are formed into a path by turning on the first selecting unit 101 and the second control unit 402 and turning off the second selecting unit 102 and the first control unit 401 to change the first programming unit 200 from the high resistance state to the low resistance state and the second programming unit 300 is kept in the low resistance state.
Specifically, in this embodiment, the antifuse transistor is in a high-resistance state, which may be defined as a logic value "1", before the first programming unit 200 is programmed. The drain electrode of the first selection unit 101 is connected to a high level, and the gate electrode of the first selection unit 101 is connected to a low level, so that the first selection unit 101 is turned on. The drain and gate of the second selection unit 102 are both connected to a high level, so that the second selection unit 102 is turned off. The gate of the first control unit 401 is connected to a low level to turn off the first control unit 401. And the gate of the second control unit 402 is connected to the high level, so that the second control unit 402 is turned on. Thus, the first selection unit 101, the first programming unit 200, the second programming unit 300, and the second control unit 402 form a path such that the antifuse transistor is turned on, and the antifuse transistor changes from a high resistance state to a low resistance state, which may be defined as a logic value "0", while the second programming unit maintains the low resistance state, i.e., the electric fuse is not turned off. Whereby the programmable circuit is programmed from a logic value "1" to a logic value "0" after a first programming.
Further, in this embodiment, the "high level" is the operating voltage, and the "low level" is the ground (0V). Alternatively, for example: the operating voltage was 0.9V in the 28nm process plateau and 1.2V in the 50LP process plateau.
Referring to fig. 5 (the broken line is shown to be open), in the second programming, after the first programming is performed, the first programming unit 200 maintains a low resistance state, the second selecting unit 102 and the first control unit 401 are turned on, and the first selecting unit 101 and the second control unit 402 are turned off, so that the second selecting unit 102, the second programming unit 300 and the first control unit 401 form a path to change the second programming unit 300 from the low resistance state to the high resistance state.
Specifically, in this embodiment, after the first programming is performed, the antifuse transistor is in a low-resistance state, and a high level is connected to the drain and the gate of the first selection unit 101, so as to disconnect the first selection unit 101. The gate of the second selection unit 102 is connected to a low level, and the drain is connected to a high level, so as to conduct the second selection unit 102. The gate of the first control unit 401 is connected to a high level to turn on the first control unit 401. And a low level is switched on at the gate of the second selection unit 402 to switch off the second selection unit 402. The second selecting unit 102, the second programming unit 300, and the first control unit 401 form a path through which current flows so that the electric fuse is blown. The second programming unit changes from a low resistance state to a high resistance state. Further, after the second programming, the programmable circuit changes from the low resistance state to the high resistance state, and then is programmed from the logic value "0" to the logic value "1".
Based on the same inventive concept, this embodiment also provides a method for reading a programmable circuit, please refer to fig. 6 (the dashed line in the drawing shows that the circuit is open), including: the second control unit 402 is turned on, and the first selection unit 101, the second selection unit 102, and the first control unit 402 are turned off, so that the first programming unit 200, the second programming unit 300, and the second control unit 402 form a path. The comparison amplifying unit 500 obtains a current value in the path, the current value corresponds to a resistance state condition in the programmable circuit, and the current value can be converted into a logic value through comparison and output.
Specifically, in this embodiment, the gates and drains of the first selection unit 101 and the second selection unit 102 are both connected to the high level, so that the first selection unit 101 and the second selection unit 102 are disconnected. The gate of the first control unit 401 is connected to a low level to turn off the first control unit 401. The gate of the second control unit 402 is connected to the high level, so that the second control unit 402 is turned on. The first programming unit 200, the second programming unit 300, and the second control unit 402 are made to form a path in a programmable circuit. The output comparing unit obtains a current value through the first programming unit 200 and converts the current value into a logic value output. Further, when the programmable circuit is in a high resistance state, a logic value of "1" is output, and when the programmable circuit is in a low resistance state, the logic value of "0" is output.
In summary, the present embodiment provides a programmable circuit, a programming method and a reading method thereof, which can form two programming paths by setting two programming units, so as to realize the function of twice programming and improve the performance of the device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (4)
1. A programmable circuit, the programmable circuit comprising: the device comprises a first selection unit, a second selection unit, a first programming unit, a second programming unit, a first control unit and a second control unit;
the first selection unit, the first programming unit and the first control unit are sequentially connected in series; the first end of the second programming unit is connected with the first programming unit and the first control unit; the second end of the second programming unit is connected with the second selection unit and the second control unit;
the first selecting unit, the first programming unit, and the second control unit form a path when programming the first programming unit;
The second selecting unit, the second programming unit, and the first control unit form a path when programming the second programming unit;
Wherein the first programming unit is an antifuse transistor and the second programming unit is an electrical fuse; the first selection unit, the second selection unit, the first control unit and the second control unit are all MOS tubes; the source electrode of the first selection unit is connected with the grid electrode of the first programming unit; the source electrode of the first programming unit is connected with the drain electrode of the first control unit; the first end of the second programming unit is connected with the source electrode of the first programming unit and the drain electrode of the first control unit; the second end of the second programming unit is connected with the source electrode of the second selecting unit and the drain electrode of the second control unit; the source electrode of the first control unit and the source electrode of the second control unit are grounded; the programmable circuit further comprises an output comparison unit, wherein the output comparison unit is connected with the drain electrode of the first selection unit and the grid electrode of the first programming unit; the output comparison unit is used for providing reference current and comparing the reference current with the current value flowing through the first programming unit so as to convert the reference current into logic value output.
2. The programmable circuit of claim 1, wherein the output comparison unit comprises a comparator, a reference resistor, and a comparison transistor; wherein,
The first end of the comparator is connected with the drain electrode of the first selection unit and the grid electrode of the first programming unit;
The second end of the comparator is connected with the reference resistor and the comparison transistor in series; the drain electrode of the comparison transistor is connected with the reference resistor, the source electrode of the comparison transistor is grounded, and the grid electrode of the comparison transistor is connected with a reference power supply;
The third terminal of the comparator is an output port.
3. A method of programming a programmable circuit using the programmable circuit of any one of claims 1-2, the method of programming a programmable circuit comprising: first programming and second programming; wherein,
In the first programming, the first selection unit and the second control unit are turned on, the second selection unit and the first control unit are turned off, so that the first programming unit is changed from a high resistance state to a low resistance state, and the second programming unit is kept in the low resistance state, and then the first selection unit, the first programming unit, the second programming unit and the second control unit form a passage;
In the second programming, after the first programming is executed, the first programming unit keeps a low resistance state, the second selecting unit and the first control unit are conducted, the first selecting unit and the second control unit are disconnected, and then a passage is formed among the second selecting unit, the second programming unit and the first control unit, so that the second programming unit is changed from the low resistance state to the high resistance state.
4. A method of reading a programmable circuit using the programmable circuit according to any one of claims 1 to 2, the method of reading a programmable circuit comprising: turning on the second control unit, and turning off the first selection unit, the second selection unit and the first control unit so that the first programming unit, the second programming unit and the second control unit form a passage; and acquiring a current value in the path, and converting the current value into a logic value and outputting the logic value.
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| CN101361139A (en) * | 2005-08-05 | 2009-02-04 | 飞思卡尔半导体公司 | One time programmable memory and method of operation |
| CN103247336A (en) * | 2012-02-06 | 2013-08-14 | 美格纳半导体有限公司 | Nonvolatile memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3923982B2 (en) * | 2005-01-12 | 2007-06-06 | 株式会社東芝 | Semiconductor integrated circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101361139A (en) * | 2005-08-05 | 2009-02-04 | 飞思卡尔半导体公司 | One time programmable memory and method of operation |
| CN103247336A (en) * | 2012-02-06 | 2013-08-14 | 美格纳半导体有限公司 | Nonvolatile memory device |
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| 基于标准制作工艺的一次性可编程存储的研究;赵立明;刘利峰;陈力颖;毕胜兰;;电子技术(12);全文 * |
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