CN118738116A - A digitally etched recessed gate enhanced GaN HEMT device and its preparation method - Google Patents

Abstract

The invention discloses a digitally etched groove gate enhanced GaN HEMT device and a preparation method thereof. The device comprises a substrate layer, a III-N composite buffer layer, a GaN channel layer and a III-N barrier layer which are sequentially stacked from bottom to top; a source electrode, a drain electrode and a groove extending from the surface to the inside of the III-N barrier layer are provided on the III-N barrier layer, and a gate electrode is covered in the groove; the GaN channel layer and the III-N barrier layer form a heterojunction, and a two-dimensional electron gas channel is formed at the heterojunction interface formed by the GaN channel layer and the III-N barrier layer and on a side close to the GaN channel layer; the source electrode and the drain electrode both form ohmic contacts with the two-dimensional electron gas channel, and the gate electrode forms a Schottky contact with the two-dimensional electron gas channel; the invention adopts a groove gate structure to increase the contact area between the gate and the channel, and enhance the control ability of the gate on the communication of the two-dimensional electron gas; a groove structure with good surface flatness is successfully prepared by adopting a digital etching process, so as to achieve effective regulation of the etching depth, avoid etching damage, and finally improve the stability of the device.

Description

A digitally etched recessed gate enhanced GaN HEMT device and a method for manufacturing the same

Technical Field

The present invention belongs to the technical field of semiconductor devices, and in particular relates to a digitally etched recessed gate enhanced GaN HEMT device and a preparation method thereof.

Background Art

The third-generation semiconductor material gallium nitride (GaN) and its group III nitride (III-N) materials have the advantages of wide band gap and high electron saturation velocity. The group III nitride semiconductor heterojunction has strong spontaneous polarization and piezoelectric polarization effects, thus having the advantages of high electron concentration and high mobility. It is widely used in the field of radio frequency devices and power electronic devices.

Since the concentration of two-dimensional electron gas (2DEG) at the GaN heterojunction interface is very high and is formed when the heterojunction structure is formed, the gate Schottky barrier of the device cannot completely deplete the 2DEG under the gate, so the GaN HEMT device is a normally-on device (depletion-type device). Although the depletion-type HEMT device has a simple process and is easy to manufacture, the depletion-type HEMT device requires a negative voltage drive module to be added in the RF circuit design, which increases the circuit power consumption. During the startup process of the switching power supply application, there may be overcharging or even loss of power control, resulting in the circuit being unable to work. Therefore, considering the device reliability, design cost and energy consumption, in actual circuit applications, we require the transistor to be in a normally-off state, that is, an enhancement-type device.

At present, the main technical solutions for realizing enhanced GaN-based HEMT devices are as follows: p-GaN cap layer technology, grooved gate technology, fluorine ion implantation technology in the region below the gate, and cascade technology. Among them, the grooved gate technology reduces the distance between the gate and the channel and increases the contact area between the gate and the channel. This design enhances the gate's control over the two-dimensional electron gas channel, improves the electron injection efficiency, reduces the gate charge and output capacitance, thereby speeding up the switching speed and reducing the switching loss. However, the dry etching process used cannot accurately control the etching depth, and etching damage occurs, which reduces the stability of the device.

Summary of the invention

In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a digitally etched recessed gate enhanced GaN HEMT device and a preparation method thereof. By adopting a digital etching process, a recessed gate enhanced GaN HEMT device with accurate and stable depth and no etching damage can be obtained, thereby greatly improving the stability of the device.

In order to achieve the above object, the technical solution adopted by the present invention is as follows:

A digitally etched recessed gate enhanced GaN HEMT device, the device comprises, from bottom to top, a substrate layer 1, a III-N composite buffer layer 2, a GaN channel layer 3, and a III-N barrier layer 4 which are sequentially stacked; the substrate layer 1 and the III-N composite buffer layer 2 are horizontally aligned, the GaN channel layer 3 and the III-N barrier layer 4 are horizontally aligned, and the III-N composite buffer layer 2 and the GaN channel layer 3 are arranged in a stepped structure; a source electrode 5 and a drain electrode 7 are arranged at both ends of the surface of the III-N barrier layer 4, a recess extending from the surface to the inside is arranged in the middle of the III-N barrier layer 4, and a gate electrode 6 is covered in the recess; the GaN channel layer 3 and the III-N barrier layer 4 form a heterojunction, and a two-dimensional electron gas channel is formed at the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and on a side close to the GaN channel layer 3; the source electrode 5 and the drain electrode 7 both form ohmic contacts with the two-dimensional electron gas channel, and the gate electrode 6 forms a Schottky contact with the two-dimensional electron gas channel.

The substrate layer 1 is made of Si, SiC, sapphire or diamond, and has a thickness of 70-2000 μm;

The III-N composite buffer layer 2 includes three layers, which are a nucleation layer, a transition layer and a buffer layer from bottom to top. The material of the nucleation layer is AlN or GaN with a thickness of 50-300nm. The material of the transition layer is AlGaN with a gradient Al component with a thickness of 200-1000nm, and the Al component gradient changes from 1 to 0.1. The material of the buffer layer is GaN or AIGaN with a thickness of 100-5000nm. The nucleation layer, transition layer and buffer layer are unintentionally doped.

The GaN channel layer 3 is made of GaN with a thickness of 50-500 nm;

The III-N barrier layer 4 is made of AlGaN, InAlN, or AlN, has a thickness of 5-30 nm, and is unintentionally doped;

The structures of the source electrode 5 and the drain electrode 7 are Ti/Al and other metals, or Ta/Al and other metals, or TIN/AI and other metals from bottom to top, and the thicknesses are 20/120/40/50 nm respectively;

The structure of the gate electrode 6 is Ni and other metals, or Ti and other metals, or TiN and other metals, or TaN and other metals from bottom to top, with thicknesses of 50/300 nm respectively; the depth of the groove is 5-20 nm.

The surface and the inside of the groove of the III-N barrier layer 4 are covered with a gate dielectric layer 8 .

The gate dielectric layer 8 is made of one or a combination of SiN, AlN, Al ₂ O ₃ , HfO ₂ , and ZrO ₂ ; and has a thickness of 1-30 nm.

A method for preparing the digitally etched recessed gate enhanced GaN HEMT device as described above comprises the following steps:

Step 1: At a high temperature of 900-1100° C., hydrogen is introduced into the reaction chamber to clean the pollutants on the surface of the substrate layer 1;

Step 2: using a metal organic chemical vapor deposition (MOCVD) process, a III-N composite buffer layer 2, a GaN channel layer 3, and a III-N barrier layer 4 are sequentially grown on the substrate layer 1 cleaned in step 1;

Step 3: etching the III-N barrier layer 4 and the two ends of the GaN channel layer 3 formed in step 2 from top to bottom, so that the etched part and the unetched part form a step, so that adjacent devices are electrically isolated;

Step 4: A source electrode 5 and a drain electrode 7 are prepared at both ends of the top of the III-N barrier layer 4 by vacuum evaporation or magnetron sputtering, and thermal annealing is performed in a _N2 atmosphere at 750-900°C for 20-90s; the source electrode 5 and the drain electrode 7 are simultaneously in ohmic contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas channel generated near one side of the GaN channel layer 3;

Step 5: using a plasma enhanced chemical vapor deposition (PECVD) process to deposit a dielectric layer on the surface of the III-N barrier layer 4 that does not cover the source electrode 5 and the drain electrode 7; using a photolithography process to etch the middle area of the dielectric layer to remove the dielectric layer in the area;

Step 6: Using the dielectric layer that has not been etched in step 5 as a mask, digitally etching the area of the III-N barrier layer 4 that is not protected by the mask to form a groove;

Step 7: Etch away the remaining dielectric layer on the surface of the III-N barrier layer 4 using an ion etcher (RIE);

Step 8: A gate electrode 6 is prepared in the middle groove of the III-N barrier layer 4 by a vacuum evaporation process. The gate electrode 6 forms a Schottky contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas channel generated on one side of the GaN channel layer 3, thereby obtaining a digitally etched groove gate enhanced GaN HEMT device.

The structure obtained from step 1 to step 3 is ultrasonically cleaned in acetone for 10-20 minutes, with the ultrasonic power set at 1-3KW, and then placed in a water bath with a cleaning and stripping solution for heating for 10-15 minutes. Finally, it is cleaned with deionized water and blown dry with nitrogen; the cleaning and stripping solution is N-methylpyrrolidone (NMP); and the water bath heating temperature is 70-85°C.

In step 5, the material of the dielectric layer is SiN or SiO ₂ , and the deposition thickness is 20-50 nm.

The specific process of step 6 is as follows:

S1: using an atomic layer deposition device (ALD) to perform saturation oxidation on the surface of the III-N barrier layer 4 in an environment of water vapor (H ₂ O), oxygen (O ₂ ), or ozone (O ₃ ), to obtain a III-N barrier layer 4 containing oxide on the surface;

S2: using a buffered oxide etchant (BOE), a tetramethylammonium hydroxide (TMAH) solution or a hydrofluoric acid (HF) solution to chemically wet etch the oxide on the surface of the III-N barrier layer 4;

S3: Repeat steps S1 and S2 until a groove with a depth of 5-20 nm is obtained.

The buffered oxide etchant (BOE) comprises an aqueous ammonium fluoride solution with a mass concentration of 30-40% and an aqueous hydrofluoric acid solution with a mass concentration of 5-10%, wherein the volume ratio of the ammonium fluoride solution to the hydrofluoric acid solution is (6-10):1; the mass concentration of the hydrofluoric acid (HF) solution is 40-50%, and the mass concentration of the tetramethylammonium hydroxide (TMAH) solution is 20-30%.

A gate dielectric layer 8 is formed by depositing a gate dielectric on the surface of the III-N barrier layer 4 and in the groove by plasma enhanced chemical vapor deposition (PEALD) or atomic layer deposition (ALD).

Compared with the prior art, the beneficial effects of the present invention are:

1. In conventional dry etching technology, it is difficult to control the physical bombardment collision of electrons and the resulting plasma chemical reaction, resulting in the inability to effectively control the surface flatness of the etched material, etching damage, and the etching depth cannot be accurately controlled due to equipment problems. The present invention uses a digital etching process to first oxidize the barrier layer under the action of oxygen plasma, and then wet-etch the oxidized III-N barrier layer to obtain a groove structure with good surface flatness. Because the oxidation mechanism is at the atomic level, the etching depth can be effectively controlled, thereby improving the stability of the device.

2. The present invention provides grooves extending from the surface to the inside on the III-N barrier layer and the GaN channel layer, and the grooves are covered with gate electrodes. This groove gate structure can reduce the distance between the gate and the channel, increase the contact area between the gate and the channel, and thus enhance the gate's control over the communication of the two-dimensional electron gas, improve the electron injection efficiency, reduce the gate charge and output capacitance, speed up the switching speed and reduce the switching loss.

3. The present invention deposits gate dielectrics on the surfaces of the III-N barrier layer on both sides of the groove, thereby effectively suppressing gate leakage, increasing the breakdown voltage, and reducing the probability of electron tunneling in the two-dimensional electron gas channel.

4. The present invention removes surface contaminants after electrical isolation treatment by ultrasonically cleaning the structure obtained in steps 1 to 3, thereby avoiding the phenomenon that the source electrode and the drain electrode prepared subsequently cannot be in close contact due to the presence of contaminants and thus fall off.

To sum up, compared with the prior art, the present invention reduces the distance between the gate and the channel and increases the contact area between the gate and the channel by adopting a groove gate structure, thereby enhancing the gate's control ability over the communication of the two-dimensional electron gas; a groove structure with good surface flatness is successfully obtained by adopting a digital etching process, which realizes effective regulation of the etching depth, avoids etching damage, and improves the stability of the device; the preparation method of the present invention is simple and relatively controllable, compatible with the original process, and can significantly improve the performance of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a front view of a digitally etched recessed gate enhanced GaN HEMT device provided by the present invention.

FIG. 2 is a front view of a digitally etched recessed gate enhanced GaN HEMT device with a gate dielectric layer provided by the present invention.

In the figure: 1-substrate layer; 2-III-N composite buffer layer; 3-GaN channel layer; 4-III-N barrier layer; 5-source electrode; 6-gate electrode; 7-drain electrode, 8-gate dielectric layer.

DETAILED DESCRIPTION

The present invention is further described in detail below with reference to the accompanying drawings and examples, but the embodiments of the present invention are not limited thereto.

As shown in FIG1 , a digitally etched groove gate enhanced GaN HEMT device includes, from bottom to top, a substrate layer 1, a III-N composite buffer layer 2, a GaN channel layer 3, and a III-N barrier layer 4 which are sequentially stacked, wherein the substrate layer 1 and the III-N composite buffer layer 2 are horizontally aligned, the GaN channel layer 3 and the III-N barrier layer 4 are horizontally aligned, and the III-N composite buffer layer 2 and the GaN channel layer 3 are arranged in a stepped structure; a source electrode 5 and a drain electrode 7 are arranged at both ends of the top of the III-N barrier layer 4, and the III-N barrier layer 4 is provided with a plurality of electrodes. A groove extending from its surface to the inside is arranged in the middle, and the groove is covered with a gate electrode 6; the GaN channel layer 3 and the III-N barrier layer 4 form a heterojunction, and due to the surface state and polarization effect of the III-N barrier layer 4, a two-dimensional electron gas channel is formed at the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and on the side close to the GaN channel layer 3; the source electrode 5 and the drain electrode 7 both form ohmic contact with the two-dimensional electron gas channel; the gate electrode 6 forms a Schottky contact with the two-dimensional electron gas channel.

The substrate layer 1 is made of Si, SiC, sapphire or diamond, with a thickness of 70-2000 μm; the III-N composite buffer layer 2 includes three layers, namely, a nucleation layer, a transition layer and a buffer layer from bottom to top, the nucleation layer is made of AlN or GaN, with a thickness of 50-300 nm, the transition layer is made of AlGaN with a gradient Al component, with a thickness of 200-1000 nm, and the Al component gradient changes from 1 to 0.1, the buffer layer is made of GaN or AIGaN, with a thickness of 100-5000 nm; the nucleation layer, transition layer and buffer layer are unintentionally doped; the GaN channel layer 3 is GaN with a thickness of 50-500nm, the material of the III-N barrier layer 4 is AlGaN, InAlN, or AlN with a thickness of 5-30nm, which is unintentionally doped; the structures of the source electrode 5 and the drain electrode 7 are Ti/A1 and other metals, or Ta/A1 and other metals, or TIN/AI and other metals from bottom to top, with thicknesses of 20/120/40/50nm, respectively, and the structures of the gate electrode 6 are Ni and other metals, or Ti and other metals, or TiN and other metals, or TaN and other metals from bottom to top, with thicknesses of 50/300nm, respectively; the depth of the groove is 5-20nm.

As shown in FIG2 , the surface of the III-N barrier layer 4 is covered with a gate dielectric layer 8 located on both sides of the groove. The material of the gate dielectric layer 8 is one or a combination of SiN, AlN, Al ₂ O ₃ , HfO ₂ , and ZrO ₂ ; the thickness is 1-30 nm.

A method for preparing a digitally etched recessed gate enhanced GaN HEMT device comprises the following steps:

Step 1: At a high temperature of 900-1100° C., hydrogen is introduced into the reaction chamber to clean the pollutants on the surface of the substrate layer 1;

Step 2: using a metal organic chemical vapor deposition (MOCVD) process, a III-N composite buffer layer 2, a GaN channel layer 3, and a III-N barrier layer 4 are sequentially grown on the substrate layer 1 cleaned in step 1;

Step 3: etching the two ends of the III-N barrier layer 4 and the GaN channel layer 3 formed in step 2 from top to bottom, so that the etched part and the unetched part form a step, so that adjacent devices are electrically isolated; the upper step surface of the step is the surface of the unetched part, and the lower step surface of the step is the surface of the etched part;

Step 4: The structure obtained from step 1 to step 3 is ultrasonically cleaned in acetone (MOS grade) for 10-20 minutes, with the ultrasonic power set at 1-3KW, and then placed in a cleaning stripping solution for water bath heating for 10-15 minutes, and finally cleaned with deionized water and dried with nitrogen; the cleaning stripping solution is N-methylpyrrolidone (NMP); the water bath heating temperature is 70-85°C;

Step 5: Prepare a source electrode 5 and a drain electrode 7 at both ends of the top of the III-N barrier layer 4 cleaned in step 4 by vacuum evaporation or magnetron sputtering, and perform thermal annealing for 20-90s in a _N2 atmosphere at 750-900°C; the source electrode 5 and the drain electrode 7 both simultaneously form an ohmic contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas channel generated on one side of the GaN channel layer 3;

Step 6: using plasma enhanced chemical vapor deposition (PECVD) to deposit a dielectric layer on the surface of the III-N barrier layer 4 that does not cover the source electrode 5 and the drain electrode 7; using an ion etcher (RIE) to etch the middle area of the dielectric layer to remove the dielectric layer in this area; the dielectric layer is made of SiN or SiO ₂ and has a deposition thickness of 20-50 nm;

Step 7: Using the dielectric layer that has not been etched in step 5 as a mask, digitally etching the area of the III-N barrier layer 4 that is not protected by the mask to form a groove;

The specific process of step 7 is as follows:

S1: using an atomic layer deposition device (ALD) to perform saturated oxidation on the surface of the III-N barrier layer 4 in an environment of water vapor (H ₂ O), oxygen (O ₂ ), or ozone (O ₃ ), to obtain a III-N barrier layer 4 containing oxide on the surface;

S2: Use a buffered oxide etchant (BOE), a tetramethylammonium hydroxide (TMAH) solution or a hydrofluoric acid (HF) solution to chemically wet etch the oxide on the surface of the III-N barrier layer 4; the buffered oxide etchant (BOE) includes an aqueous ammonium fluoride solution with a mass concentration of 30-40% and an aqueous hydrofluoric acid solution with a mass concentration of 5-10%, and the volume ratio of the ammonium fluoride solution to the hydrofluoric acid solution is (6-10):1; the mass concentration of the hydrofluoric acid (HF) solution is 40-50%, and the mass concentration of the tetramethylammonium hydroxide (TMAH) solution is 20-30%.

S3: repeating step S1 and step S2 until a groove with a depth of 5-20 nm is obtained, and the obtained groove has high flatness and small surface roughness;

Step 8: Etch away the remaining dielectric layer on the surface of the III-N barrier layer 4 using an ion etcher (RIE);

Step 9: A gate electrode 6 is prepared in the middle groove of the III-N barrier layer 4 by a vacuum evaporation process. The gate electrode 6 forms a Schottky contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas channel generated on one side of the GaN channel layer 3, thereby obtaining a digitally etched groove gate enhanced GaN HEMT device.

The present invention also includes a step 8A between step 8 and step 9, step 8A: using plasma enhanced chemical vapor deposition (PEALD) or atomic layer deposition (ALD) process to deposit gate dielectrics on the surface and in the grooves of the III-N barrier layer 4 to form a gate dielectric layer 8; the material of the gate dielectric is one or more combinations of SiN, AlN, Al ₂ O ₃ , HfO ₂ , ZrO ₂ ; the thickness is 1-30nm.

Example 1

A digitally etched groove gate enhanced gallium nitride HEMT device, wherein the substrate layer 1 is made of Si with a thickness of 200 μm; the III-N composite buffer layer 2 includes three layers, which are a nucleation layer, a transition layer and a buffer layer from bottom to top, the nucleation layer is made of AlN with a thickness of 150 nm, the transition layer is made of AlGaN with a gradient Al component with a thickness of 700 nm, and the Al component gradient changes from 1 to 0.1, and the buffer layer is made of GaN with a thickness of 300 nm; the nucleation layer, The transition layer and the buffer layer are unintentionally doped; the material of the GaN channel layer 3 is GaN with a thickness of 300nm, and the material of the III-N barrier layer 4 is AlGaN with a thickness of 20nm, which is unintentionally doped; the structures of the source electrode 5 and the drain electrode 7 are Ti/A1/Ni/Au from bottom to top, with thicknesses of 20/120/40/50nm, and the structures of the gate electrode 6 are TiN/Au from bottom to top, with thicknesses of 50/300nm; the depth of the groove is 10nm.

A method for preparing a digitally etched recessed gate enhanced GaN HEMT device comprises the following steps:

Step 1: At a high temperature of 1000° C., hydrogen is introduced into the reaction chamber to clean the pollutants on the surface of the substrate layer 1;

Step 2: Using a metal organic chemical vapor deposition (MOCVD) process, a III-N composite buffer layer 2, a GaN channel layer 3, and a III-N barrier layer 4 are sequentially grown on a clean substrate layer 1; that is, a 150 nm thick AlN nucleation layer is first grown on the substrate at a low temperature of 500°C, and then the temperature is raised to 1000°C, a transition layer is grown on the nucleation layer, and a gradient AlGaN with a thickness of 700 nm, the Al component gradually changes from 1 to 0.1, and then a GaN buffer layer with a thickness of 300 nm is grown on the transition layer; then, the temperature is maintained at 1000°C, a GaN channel layer 3 with a thickness of 300 nm is grown on the buffer layer, and an AlGaN barrier layer 4 with a thickness of 20 nm is epitaxially grown on the channel layer 3, and the Al component is 0.15;

Step 3: etching the two ends of the III-N barrier layer 4 and the GaN channel layer 3 formed in step 2 from top to bottom, so that the etched part and the unetched part form a step, separating different devices so that adjacent devices are electrically isolated; the upper step surface of the step is the surface of the unetched part, and the lower step surface of the step is the surface of the etched part;

Step 4: The structure obtained from step 1 to step 3 is ultrasonically cleaned in acetone (MOS grade) for 10 minutes, the ultrasonic power is set at 1KW, and then placed in a cleaning stripping solution for water bath heating for 15 minutes, and finally cleaned with deionized water and blown dry with nitrogen; the cleaning stripping solution is N-methylpyrrolidone (NMP); the water bath heating temperature is 80°C;

Step 5: A source electrode 5 and a drain electrode 7 are respectively prepared at both ends of the top of the III-N barrier layer 4 cleaned in step 4 by vacuum evaporation or magnetron sputtering, and thermal annealing is performed in an _N2 atmosphere at 850°C for 30s; the source electrode 5 and the drain electrode 7 both simultaneously form an ohmic contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas generated on one side of the GaN channel layer 3;

Step 6: using a plasma enhanced chemical vapor deposition (PECVD) process to deposit SiN on the surface of the III-N barrier layer 4 to form a dielectric layer with a deposition thickness of 30 nm; using an ion etcher (RIE) to etch the middle region of the dielectric layer to remove the SiN in the region;

Step 7: Using the dielectric layer that has not been etched in step 6 as a mask, an atomic layer deposition device (ALD) is used to perform saturation oxidation on the area of the III-N barrier layer 4 that is not protected by the mask in an oxygen (O ₂ ) environment, and then a tetramethylammonium hydroxide (TMAH) solution with a mass concentration of 25% is used to perform chemical wet etching on the oxidized III-N barrier layer 4, and the saturation oxidation and wet etching operations are repeated until a groove with a depth of 10 nm is obtained;

Step 8: Use an ion etcher (RIE) to etch away the remaining SiN on the surface of the III-N barrier layer 4;

Step 9: A gate electrode 6 is prepared in the middle groove of the III-N barrier layer 4 by vacuum evaporation or magnetron sputtering. The gate electrode 6 forms a Schottky contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas channel generated on one side of the GaN channel layer 3, and finally a groove gate enhanced GaN HEMT device is obtained.

Example 2

On the basis of Example 1, in this embodiment, between Step 8 and Step 9, Step 8A is provided:

Step 8A: Al ₂ O ₃ is deposited on the surface of the III-N barrier layer 4 and in the groove by an atomic layer deposition (ALD) process to form a gate dielectric layer 8 with a thickness of 10 nm.

Example 3

A digitally etched groove gate enhanced gallium nitride HEMT device, wherein the substrate layer 1 is made of SiC with a thickness of 500 μm; the III-N composite buffer layer 2 includes three layers, which are a nucleation layer, a transition layer and a buffer layer from bottom to top, the nucleation layer is made of GaN with a thickness of 250 nm, the transition layer is made of AlGaN with a gradient Al component with a thickness of 1000 nm, and the Al component gradient changes from 1 to 0.1; the buffer layer is made of GaN with a thickness of 200 nm; the nucleation layer is made of GaN with a thickness of 250 nm, and ... GaN with a thickness of 250 nm. The layer, transition layer and buffer layer are unintentionally doped; the material of the GaN channel layer 3 is GaN with a thickness of 50nm, and the material of the III-N barrier layer 4 is InAlN with a thickness of 30nm, which is unintentionally doped; the structures of the source electrode 5 and the drain electrode 7 are Ti/A1/Ni/Au from bottom to top, with thicknesses of 20/120/40/50nm, respectively, and the structures of the gate electrode 6 are Ni/Au from bottom to top, with thicknesses of 50/300nm, respectively; the depth of the groove is 20nm.

A method for preparing a digitally etched recessed gate enhanced GaN HEMT device comprises the following steps:

Step 1: At a high temperature of 1000° C., hydrogen is introduced into the reaction chamber to clean the pollutants on the surface of the substrate layer 1;

Step 2: Using a metal organic chemical vapor deposition (MOCVD) process, a III-N composite buffer layer 2, a GaN channel layer 3, and a III-N barrier layer 4 are sequentially grown on a clean substrate layer 1; that is, a GaN nucleation layer with a thickness of 250 nm is first grown on the substrate at a low temperature of 500°C, and then the temperature is raised to 1000°C, and a transition layer with a thickness of 1000 nm of gradient AlGaN is grown on the nucleation layer, and the Al component gradually changes from 1 to 0.1, and then a GaN buffer layer with a thickness of 200 nm is grown on the transition layer; then, the temperature is maintained at 1000°C, and a GaN channel layer 3 with a thickness of 50 nm is grown on the buffer layer, and an InAlN barrier layer 4 with a thickness of 30 nm is epitaxially grown on the channel layer 3, and the Al component is 0.15;

Step 3: etching the two ends of the III-N barrier layer 4 and the GaN channel layer 3 formed in step 2 from top to bottom, so that the etched part and the unetched part form a step, so that adjacent devices are electrically isolated; the upper step surface of the step is the surface of the unetched part, and the lower step surface of the step is the surface of the etched part;

Step 4: The structure obtained from step 1 to step 3 is ultrasonically cleaned in acetone (MOS grade) for 10 minutes, the ultrasonic power is set at 2KW, and then placed in a cleaning stripping solution for water bath heating for 15 minutes, and finally cleaned with deionized water and blown dry with nitrogen; the cleaning stripping solution is N-methylpyrrolidone (NMP); the water bath heating temperature is 80°C;

Step 5: A source electrode 5 and a drain electrode 7 are respectively prepared at both ends of the top of the III-N barrier layer 4 cleaned in step 4 by vacuum evaporation or magnetron sputtering, and thermal annealing is performed in a _N2 atmosphere at 875°C for 30 seconds; the source electrode 5 and the drain electrode 7 both simultaneously form an ohmic contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas generated on one side of the GaN channel layer 3;

Step 6: Deposit SiO ₂ on the surface of the III-N barrier layer 4 by plasma enhanced chemical vapor deposition (PECVD) to form a dielectric layer with a deposition thickness of 50 nm; use an ion etcher (RIE) to etch the middle region of the dielectric layer to remove the SiO ₂ in the region;

Step 7: Using the dielectric layer deposited in step 6 as a mask, using an atomic layer deposition device (ALD), saturation oxidation is performed on the III-N barrier layer 4 without mask protection in a water vapor (H ₂ O) environment, and then a hydrofluoric acid (HF) solution with a mass concentration of 49% is used to chemically wet etch the oxidized III-N barrier layer 4, and the saturation oxidation and wet etching operations are repeated until a groove with a depth of 20 nm is obtained;

Step 8: Use an ion etcher (RIE) to etch away the remaining SiO ₂ on the surface of the III-N barrier layer 4;

Step 9: A gate electrode 6 is prepared in the middle groove of the III-N barrier layer 4 by vacuum evaporation or magnetron sputtering. The gate electrode 6 forms a Schottky contact with the heterojunction interface formed by the GaN channel layer 3 and the III-N barrier layer 4 and the two-dimensional electron gas channel generated on one side of the GaN channel layer 3, and finally a groove gate enhanced GaN HEMT device is obtained.

The above contents are further detailed descriptions of the invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims (10)

1. The utility model provides a digit etching recess bars enhancement mode gaN HEMT device which characterized in that: the device comprises a substrate layer (1), a III-N composite buffer layer (2), a GaN channel layer (3) and a III-N barrier layer (4) which are sequentially overlapped from bottom to top; the substrate layer (1) and the III-N composite buffer layer (2) are horizontally aligned, the GaN channel layer (3) and the III-N barrier layer (4) are horizontally aligned, and the III-N composite buffer layer (2) and the GaN channel layer (3) are arranged in a step structure; an active electrode (5) and a drain electrode (7) are arranged at two ends of the surface of the III-N barrier layer (4), a groove extending inwards from the surface of the III-N barrier layer (4) is arranged in the middle of the III-N barrier layer, and a gate electrode (6) is covered in the groove; the GaN channel layer (3) and the III-N barrier layer (4) form a heterojunction, a heterojunction interface formed by the GaN channel layer (3) and the III-N barrier layer (4) forms a two-dimensional electron gas channel at one side close to the GaN channel layer (3); the source electrode (5) and the drain electrode (7) form ohmic contact with the two-dimensional electron gas channel, and the gate electrode (6) forms Schottky contact with the two-dimensional electron gas channel.

2. The digitally etched recessed gate enhanced GaN HEMT device of claim 1, wherein: the substrate layer (1) is made of Si, siC, sapphire or Diamond (Diamond) and has the thickness of 70-2000 mu m;

The III-N composite buffer layer (2) comprises three layers, namely a nucleation layer, a transition layer and a buffer layer from bottom to top, wherein the nucleation layer is made of AlN or GaN, the thickness is 50-300nm, the transition layer is made of AlGaN with gradually changed Al components, the thickness is 200-1000nm, the Al components are gradually changed from 1 to 0.1, the buffer layer is made of GaN or AIGaN, and the thickness is 100-5000nm; the nucleation layer, the transition layer and the buffer layer are unintentionally doped;

the GaN channel layer (3) is made of GaN, and the thickness of the GaN channel layer is 50-500nm;

The III-N barrier layer (4) is made of AlGaN, inAlN or AlN, has the thickness of 5-30nm and is unintentionally doped;

the structures of the source electrode (5) and the drain electrode (7) are Ti/A1 and other metals, ta/A1 and other metals, or TIN/AI and other metals in sequence from bottom to top, and the thicknesses are 20/120/40/50nm in sequence;

The structure of the gate electrode (6) is sequentially Ni and other metals, or Ti and other metals, or TiN and other metals, or TaN and other metals from bottom to top, and the thickness is sequentially 50/300nm; the depth of the groove is 5-20nm.

3. The digitally etched recessed gate enhanced GaN HEMT device of claim 1, wherein: and a gate dielectric layer (8) is covered on the surface of the III-N barrier layer (4) and in the groove.

4. The digitally etched recessed gate enhanced GaN HEMT device of claim 3, wherein: the gate dielectric layer (8) is made of one or more of SiN, alN and Al ₂O₃,HfO₂,ZrO₂; the thickness is 1-30nm.

5. The method for manufacturing the digitally etched recessed gate enhanced GaN HEMT device of any one of claims 1-4, comprising the steps of:

step 1: introducing hydrogen into the reaction chamber at a high temperature of 900-1100 ℃ to clean pollutants on the surface of the substrate layer (1);

Step 2: a Metal Organic Chemical Vapor Deposition (MOCVD) process is adopted, and a III-N composite buffer layer (2), a GaN channel layer (3) and a III-N barrier layer (4) are sequentially grown on the substrate layer (1) cleaned in the step 1;

Step 3: etching the two ends of the III-N barrier layer (4) and the GaN channel layer (3) formed in the step (2) from top to bottom, so that the etched part and the unetched part form steps, and electric isolation is formed between adjacent devices;

Step 4: vacuum evaporation or magnetron sputtering technology is adopted at the two ends of the top of the III-N barrier layer (4) to respectively prepare a source electrode (5) and a drain electrode (7), and thermal annealing is carried out for 20-90s in an N ₂ atmosphere at 750-900 ℃; the source electrode (5) and the drain electrode (7) form ohmic contact with a heterojunction interface formed by the GaN channel layer (3) and the III-N barrier layer (4) at the same time and a two-dimensional electron gas channel formed on one side close to the GaN channel layer (3);

step 5: depositing a dielectric layer on the surface of the III-N barrier layer (4) which is not covered by the source electrode (5) and the drain electrode (7) by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process; etching the middle area of the dielectric layer by adopting a photoetching process, and removing the dielectric layer in the area;

Step 6: taking the dielectric layer which is not etched in the step 5 as a mask, and carrying out digital etching on the area of the III-N barrier layer (4) which is not protected by the mask to manufacture a groove;

Step 7: etching the residual dielectric layer on the surface of the III-N barrier layer (4) by using an ion etching machine (RIE);

Step 8: and preparing a gate electrode (6) in the middle groove of the III-N barrier layer (4) by adopting a vacuum evaporation process, wherein the gate electrode (6) forms a Schottky contact with a heterojunction interface formed by the GaN channel layer (3) and the III-N barrier layer (4) and a two-dimensional electron gas channel generated on one side close to the GaN channel layer (3), so as to obtain the digital etched groove gate enhanced GaN HEMT device.

6. The digitally etched recessed gate enhanced GaN HEMT device of claim 5, wherein: carrying out ultrasonic cleaning on the structure obtained in the step 1-step 3 in acetone for 10-20min, wherein the ultrasonic power is 1-3KW, then placing the structure into a cleaning stripping liquid water bath for heating for 10-15min, and finally cleaning the structure with deionized water and drying the structure with nitrogen; the cleaning stripping liquid is N-methyl pyrrolidone (NMP); the heating temperature of the water bath is 70-85 ℃.

7. The digitally etched recessed gate enhanced GaN HEMT device of claim 5, wherein: and in the step 5, the dielectric layer is made of SiN or SiO ₂, and the deposition thickness is 20-50nm.

8. The digitally etched recessed gate enhanced GaN HEMT device of claim 5, wherein the specific process of step 6 is as follows:

S1: performing saturated oxidation on the surface of the III-N barrier layer (4) in the environment of water vapor (H ₂ O), oxygen (O ₂) or ozone (O ₃) by using atomic layer-by-layer deposition equipment (ALD) to obtain the III-N barrier layer (4) with oxide on the surface;

S2: performing chemical wet etching on the oxide on the surface of the III-N barrier layer (4) by using a buffer oxide etching solution (BOE), a tetramethyl ammonium hydroxide (TMAH) solution or a hydrofluoric acid (HF) solution;

S3: and repeating the step S1 and the step S2 until grooves with the depth of 5-20nm are obtained.

9. The digitally etched recessed gate enhanced GaN HEMT device of claim 8, wherein: the buffer oxide etching solution (BOE) comprises 30-40% of fluorinated ammonia water solution and 5-10% of hydrofluoric acid water solution, wherein the volume ratio of the fluorinated ammonia solution to the hydrofluoric acid solution is (6-10): 1, a step of; the mass concentration of the hydrofluoric acid (HF) solution is 40-50%, and the mass concentration of the tetramethyl ammonium hydroxide (TMAH) solution is 20-30%.

10. The digitally etched recessed gate enhanced GaN HEMT device of claim 8, wherein: and depositing gate dielectric on the surface of the III-N barrier layer (4) and in the grooves by adopting plasma enhanced chemical vapor deposition (PEALD) or atomic layer-by-layer deposition (ALD) to form a gate dielectric layer (8).