CN118734761A - Useless logical deletion method, device, storage medium, computer equipment and program product - Google Patents

Abstract

The application relates to the technical field of integrated circuits, and provides a useless logic deleting method, a device, a storage medium, computer equipment and a program product, wherein the useless logic deleting method comprises the following steps: determining a wire net connected with input pins of a top layer module and a wire net without driving from wire nets of an integrated circuit design, and marking the wire nets as reference wire nets; for each reference net, the following preset operations are performed: determining a reference wire net as a target wire net under the condition that the reference wire net meets the preset condition, taking each wire net in other wire nets as a new reference wire net respectively under the condition that the reference wire net is connected with other wire nets along the signal propagation direction, continuously executing preset operation, determining the reference wire net as the target wire net under the condition that the target wire net exists in the other wire nets, and determining an instance of the connection of the reference wire net along the signal propagation direction as a target instance; and deleting the wire nets other than the target wire net and the examples other than the target example. The method can quickly remove useless logic.

Description

Useless logical deletion method, device, storage medium, computer equipment and program product

Technical Field

The present application generally relates to the field of integrated circuit technology, and more specifically, to a useless logical deletion method, apparatus, storage medium, computer equipment and program product.

Background Art

In integrated circuit design, there are usually a lot of useless logics in the register transfer level that have no effect on the output signal. These useless logics are usually manifested as all output pins of the instance not being connected to any wire net, which not only affects the accuracy of power consumption calculations, but also increases area usage.

To solve this problem, there is a method for deleting redundant logic elements in the related art. This method starts from the output signal of the top layer, searches for the signal source in the reverse direction of signal propagation, builds a table of driving signal sources, and deletes useless instances by looking up the table. However, as the complexity of integrated circuit design increases, this method still needs to check and clean up all wire nets after deleting useless instances by looking up the table, and in a multi-level design, the speed of reversely searching for signal sources is too slow.

Summary of the invention

The present application provides a useless logic deletion method, apparatus, storage medium, computer equipment and program product, which are used to at least solve the problem of how to quickly remove useless logic in integrated circuit design.

According to one aspect of the present application, a useless logic deletion method is provided, the useless logic deletion method comprising: determining, from the wire nets of the integrated circuit design, the wire nets connected to the input pins of the top-level module and the wire nets without drivers, and recording them as reference wire nets; for each reference wire net, performing the following preset operations: if the reference wire net meets the preset conditions, determining the reference wire net as a target wire net, wherein the preset conditions include being connected to the output pins of the top-level module, and if the reference wire net is connected to other wire nets along the signal propagation direction, taking each wire net in the other wire nets as a new reference wire net, and continuing to perform the preset operations to determine whether there is a target wire net in the other wire nets, and if it is determined that there is a target wire net in the other wire nets, determining the reference wire net as a target wire net, and determining the instance connected to the reference wire net along the signal propagation direction as a target instance; deleting the wire nets other than the target wire net and the instances other than the target instance in the integrated circuit design as useless logic to obtain an updated integrated circuit design.

According to another aspect of the present application, a useless logic deletion device is provided, the useless logic deletion device comprising: a preparation unit, configured to determine, from the wire nets of the integrated circuit design, the wire nets connected to the input pins of the top-level module and the wire nets without drivers, recorded as reference wire nets; an execution unit, configured to perform the following preset operations for each reference wire net: if the reference wire net meets a preset condition, determine the reference wire net as a target wire net, wherein the preset condition includes being connected to the output pin of the top-level module, and if the reference wire net is connected to other wire nets along the signal propagation direction, use each wire net in the other wire nets as a new reference wire net, and continue to perform the preset operations to determine whether there is a target wire net in the other wire nets, and if it is determined that there is a target wire net in the other wire nets, determine the reference wire net as a target wire net, and determine the instance connected to the reference wire net along the signal propagation direction as a target instance; a deletion unit, configured to delete the wire nets other than the target wire net and the instances other than the target instance in the integrated circuit design as useless logic to obtain an updated integrated circuit design.

According to another aspect of the present application, a computer-readable storage medium is provided. When instructions in the computer-readable storage medium are executed by at least one processor, the at least one processor is prompted to execute the useless logical deletion method as described above.

According to another aspect of the present application, a computer device is provided, comprising: at least one processor; and at least one memory storing computer executable instructions, wherein when the computer executable instructions are executed by the at least one processor, the at least one processor is prompted to execute the useless logical deletion method as described above.

According to another aspect of the present application, a computer program product is provided, comprising computer instructions. When the computer instructions are executed by at least one processor, the at least one processor is prompted to execute the useless logical deletion method as described above.

According to the useless logic deletion method, device, storage medium, computer equipment and program product of the exemplary embodiment of the present application, by adopting the depth first search (DFS) method, starting from the reference line network as the initial source of useless logic, along the signal propagation direction, traversing the line network and instance of the integrated circuit design, obtaining the target line network that meets the preset conditions and the line network that can be connected to the target line network along the signal propagation direction, all these line networks are used as the target line network, and the instance connected to the target line network along the signal propagation direction is determined as the target instance, and finally the line network and instance other than the target line network and the target instance are deleted as useless logic, and all useless logic can be removed without multiple driver detection (Multiple Driver Detection refers to the identification and processing of multiple signal sources driving the same network in integrated circuit design), which effectively improves the efficiency of deleting useless logic. In addition, this operation of forward searching for useless logic along the signal propagation direction can be done together with constant propagation simplification, which helps to improve processing efficiency.

Other aspects and/or advantages of the general inventive concept of the present application will be set forth in part in the following description, and some will be clear from the description or may be learned through practice of the general inventive concept of the present application.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the present application will become clear and easier to understand from the following description of the embodiments in conjunction with the accompanying drawings.

FIG. 1 is a flow chart showing a useless logical deletion method according to an exemplary embodiment of the present application.

FIG. 2 is a topology diagram showing an integrated circuit design according to a specific embodiment of the present application.

FIG. 3 is a block diagram showing a useless logical deletion apparatus according to an exemplary embodiment of the present application.

FIG. 4 is a block diagram showing a computer device according to an exemplary embodiment of the present application.

DETAILED DESCRIPTION

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the present invention as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, one of ordinary skill in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. In addition, descriptions of well-known functions and structures are omitted for clarity and brevity.

It should be noted that the phrase "at least one of the items" in this application includes three types of parallel situations: "any one of the items", "a combination of any number of the items", and "all of the items". For example, "including at least one of A and B" includes the following three parallel situations: (1) including A; (2) including B; (3) including A and B. Another example is "executing at least one of step 1 and step 2" which means the following three parallel situations: (1) executing step 1; (2) executing step 2; (3) executing step 1 and step 2.

With the advancement of manufacturing technology and design technology, the design method of electronic systems has undergone profound changes. From computer-aided design (CAD), computer-aided engineering (CAE) to electronic design automation (EDA), the degree of design automation is getting higher and higher, and the complexity of design is getting stronger and stronger. Integrated circuit (IC) EDA refers to the design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of ultra-large-scale integrated circuit chips. At present, EDA technology has become a powerful tool for modern electronic design. Without the support of EDA technology, it is unimaginable to complete the design and manufacture of ultra-large-scale integrated circuits. Integrated circuit designers need to use EDA tools to design complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve the success rate of tape-out and save tape-out costs.

Integrated circuit design usually consists of several modules. Modules are the basic building blocks of hierarchical design. Their practical meaning is to represent the logical entities on the hardware circuit. In hierarchical design, modules are layered. High-level modules implement complex functions by calling instances of low-level modules. Modules will set pins toward low-level instances and/or pins toward high-level modules. Pins are used to connect nets, so that high-level modules and low-level instances can be connected through nets. A top module is required to connect the modules to complete the entire system. The top module defines the primary input and primary output of the design.

In integrated circuit design, the register transfer level (RTL) usually contains a lot of useless logic that has no effect on the output signal. This useless logic is usually manifested as all the output pins of the instance not being connected to any net. The reason is that in order to reuse modules, designers will instantiate a large number of modules, resulting in redundancy of some signals, which will not only affect the accuracy of power consumption calculations, but also increase the use of area. Therefore, after reading the RTL design file, the relevant EDA tools may detect the useless logic in the design and then remove it.

There is a method for deleting redundant logic elements in the related art. This method starts from the output signal of the top layer, searches for the signal source in the reverse direction of signal propagation, builds a table of driving signal sources, and deletes useless instances by looking up the table. However, as the complexity of integrated circuit design increases, this method still needs to check and clean up all wire nets after deleting useless instances by looking up the table, and in a multi-level design, the speed of reversely searching for signal sources is too slow.

The following describes in detail a useless logical deletion method, apparatus, storage medium, computer device, and program product according to exemplary embodiments of the present application with reference to FIGS. 1 to 4 .

Fig. 1 is a flow chart showing a useless logical deletion method according to an exemplary embodiment of the present application. The useless logical deletion method according to an exemplary embodiment of the present application can be implemented in a computer device with sufficient computing power.

1 , in step S101 , a net connected to an input pin of a top-level module and a net without a driver are determined from among the nets of the integrated circuit design and recorded as reference nets.

Floating Net refers to a signal line that is not connected to any active driving source in the integrated circuit design. The nets connected to the input pins of the top-level module and the undriven nets are the initial sources of useless logic. By using these nets as reference nets and exploring the non-deletable useful logic from front to back along the signal propagation direction, the overall calculation process can be simplified and the calculation efficiency can be improved.

In step S102 , a preset operation is performed for each reference net to determine a target net and a target instance in the integrated circuit design.

The preset operation specifically includes: when the reference line network meets the preset conditions, the reference line network is determined as the target line network, wherein the preset conditions include being connected to the output pin of the top-level module, and such a line network must be a useful line network and needs to be retained; if the reference line network does not meet the preset conditions, then when the reference line network is connected to other line networks along the signal propagation direction (i.e., the direction from input to output), each line network in the other line networks is used as a new reference line network, and the preset operation is continued to be performed to determine whether there is a target line network in other line networks, and when it is determined that there is a target line network in other line networks, the reference line network is determined as the target line network, and the instance connected to the reference line network along the signal propagation direction is determined as the target instance.

Specifically, the preset operation is to first determine whether the current reference network N1 meets the preset conditions, such as whether the current reference network N1 is connected to the output pin of the top-level module. If it does, it is determined that the reference network N1 is a non-deletable target network. If it does not meet the conditions, it is temporarily impossible to determine whether the reference network N1 is the target network, and it is also necessary to determine whether the reference network N1 is connected to other networks along the signal propagation direction. If no other networks are connected, it is determined that the reference network N1 is not the target network; if other networks are connected, continue to explore other networks N1-i, where i=1,2,…,I, I is the number of other networks connected to the reference network N1 along the signal propagation direction, and use other networks one by one as new reference networks, and perform the same preset operation to make a judgment. After further exploration, if it is determined that there is a target network in other network N1-i, then the reference network N1 is also determined to be the target network, and the instance connected to the reference network N1 along the signal propagation direction is determined as the target instance that cannot be deleted; if it is determined that none of the other network N1-i is the target network, then the reference network N1 is also determined not to be the target network. At this point, the preset operation for the reference network N1 is completed, and the preset operation can continue to be performed for the reference network N2, and so on, until the preset operation for all reference networks is completed.

It can be understood that in the process of continuing to explore other network N1-i connected to the reference network N1, if other network N1-i is connected to other network N1-i-j along the signal propagation direction, where j=1,2,…,J, J is the number of other network connected to the reference network N1-i along the signal propagation direction, then it is necessary to take other network N1-i-j as new reference network one by one and continue to explore according to the same rules.

It should be understood that in the process of step-by-step exploration, multiple network lines connected in sequence along the signal propagation direction can form a path. If the network line at the end of the path is the target network line, then all reference network lines on the path can be determined as the target network line, and all instances can be determined as target instances.

It should also be understood that even if the reference line network N1 is determined to be the target line network, if it is found that the reference line network N1 is connected to other line networks along the signal propagation direction, the preset operation can also be performed on the other line networks. For example, the reference line network is a branch line network, and one branch is connected to the output pin of the top module. At this time, since the output pin of the top module will not be connected to other line networks along the signal propagation direction, the branch of the reference line network will not be connected to other line networks along the signal propagation direction, but another branch of the reference line network may be connected to other line networks along the signal propagation direction. In other words, the two situations that the reference line network meets the preset conditions and the reference line network is connected to other line networks along the signal propagation direction can exist at the same time.

In step S103, nets other than the target net and instances other than the target instance in the integrated circuit design are deleted as useless logic to obtain an updated integrated circuit design.

Based on the judgment result of step S102, this step retains the target net and the target instance, and deletes other nets and instances as useless logic.

Optionally, step S103 includes: traversing the nets and instances in the integrated circuit design layer by layer from top to bottom, and performing the following operations: when the traversed net is not the target net, deleting the traversed net as useless logic; when the traversed instance is not the target instance, deleting the traversed instance as useless logic; when the traversed instance is the target instance and is a hierarchical instance, continuing to traverse the nets and lower instances in the current hierarchical instance downward. By performing the traversal from top to bottom, it is possible to directly delete clear useless logic without deleting the instances and nets inside the useless hierarchical instance one by one, which helps to improve the deletion efficiency. In addition, for the hierarchical target instance, although it should not be deleted directly as a target instance, there may still be non-target instances and non-target nets in its lower instance. By continuing to traverse downward, only the target instance and target net of its lower layer can be retained, ensuring the full deletion of useless logic. As an example, you can first traverse the nets in the top-level module, delete the non-target nets, and then traverse all lower-level instances of the top-level module and delete the non-target instances. For the target instance in the lower-level instance, if it is a leaf instance, it is directly retained without any further processing. If it is a hierarchical instance, continue to traverse the nets and instances in the hierarchical target instance, delete the non-target nets and non-target instances, and continue to explore the hierarchical target instance.

According to the useless logic deletion method of the exemplary embodiment of the present application, by adopting a depth-first search method, starting from the reference line network as the initial source of useless logic, along the signal propagation direction, traversing the line network and instance of the integrated circuit design, obtaining the target line network that meets the preset conditions and the line network that can be connected to the target line network along the signal propagation direction, all these line networks are used as target line networks, and the instance connected to the target line network along the signal propagation direction is determined as the target instance, and finally the line network and instance other than the target line network and the target instance are deleted as useless logic, which can remove all useless logic without multi-drive detection, effectively improving the efficiency of deleting useless logic. In addition, this operation of forward searching for useless logic along the signal propagation direction can be done together with constant propagation simplification (a technology in optimizing integrated circuit design, which reduces the complexity of the circuit by identifying and replacing known constant values in the circuit. For example, if a signal always remains at 1 or 0, then the related operations and logic in the circuit can be simplified or omitted, thereby improving the efficiency of the circuit), which helps to improve processing efficiency.

Next, the useless logical deletion method according to the exemplary embodiment of the present application is further introduced.

Regarding how to implement the judgment in the preset operation, optionally, in the preset operation, when the reference net is connected to other nets along the signal propagation direction, the step of using each of the other nets as a new reference net includes: when the reference net is directly connected to other nets along the signal propagation direction, using each of the other directly connected nets as a new reference net; when the reference net is directly connected to the input pin of the leaf instance along the signal propagation direction, using each output net of the leaf instance as a new reference net, wherein the output net of the leaf instance is other nets indirectly connected to the reference net along the signal propagation direction. For the case where the reference net is directly connected to the input pin of the leaf instance, although the leaf instance is not a net, since there are no other nets inside the leaf instance, if the leaf instance has an output net, whether there is useful logic that cannot be deleted in the output net of the leaf instance will directly determine whether the reference net is useful logic that cannot be deleted. Based on this, by treating the output net of the leaf instance as other nets connected to the reference net along the direction of signal propagation as a new reference net, it is possible to reliably confirm useless logic and ensure the efficiency of useless logic deletion. It should be understood that based on the structure of the integrated circuit design, in the case where the reference net is directly connected to other nets along the direction of signal propagation, the reference net will be directly connected to the hierarchical instance. Specifically, if the reference net is connected to the input net of the hierarchical instance, the input net serves as a new reference net; if the reference net is the output net of the hierarchical instance, the reference net (i.e., the output net of the hierarchical instance) is connected to the upper net of the current hierarchical instance, and the upper net is used as a new reference net.

It should be understood that just as the two situations described above that the reference line network meets the preset conditions and the reference line network is connected to other line networks along the signal propagation direction can exist at the same time, the reference line network can also be directly or indirectly connected to other line networks along the signal propagation direction.

Further optionally, in the preset operation, the judgment can be specifically implemented based on the pins. At this time, the preset operation also includes: obtaining all the pins connected to the reference line network along the signal propagation direction, recorded as reference pins; accordingly, in the preset operation, when the reference line network meets the preset conditions, the step of determining the reference line network as the target line network includes: when the reference pin includes the output pin of the top-level module, determining the reference line network as the target line network; in the preset operation, when the reference line network is directly connected to other line networks along the signal propagation direction, the step of using each line network in the other directly connected line networks as a new reference line network includes: when the reference pin includes the pin of the hierarchical instance, each line network connected on the other side of the reference pin is used as a new reference line network; in the preset operation, when the reference line network is directly connected to the input pin of the leaf instance along the signal propagation direction, the step of using each output line network of the leaf instance as a new reference line network includes: when the reference pin includes the input pin of the leaf instance, each output line network of the leaf instance is used as a new reference line network. By taking the pins as the object of judgment when executing the preset operation, it is possible to combine the type of module instance to which the pin belongs (i.e., top-level module, hierarchical instance, or leaf instance) and the type of the pin itself (i.e., input pin or output pin) to achieve reliable preset condition judgment and exploration of new reference network cables, which helps to simplify the amount of calculation.

Considering that the wire nets in the integrated circuit design may have complex connection relationships, the same reference wire net may be repeatedly encountered during the process of probing based on different paths, and then the preset operation may be repeatedly performed on the reference wire net.

To this end, in some embodiments, optionally, step S102 includes: for each reference line net, if it is determined that the preset operation has been performed on the reference line net, no longer perform the preset operation on the reference line net; if it is determined that the preset operation has not been performed on the reference line net, perform the preset operation on the reference line net. By limiting the preset operation to be performed only once on the same reference line net, it is possible to reduce repeated calculations, control the amount of calculations, and reduce the waste of computing resources. It should be understood that in the case where the preset operation has been performed on the reference line net, if it is necessary to determine whether the reference line net is the target line net, the current latest execution result can be directly used, that is, if it is currently determined that the reference line net is the target line net, then the reference line net is considered to be the target line net, otherwise it is considered that the reference line net is not the target line net. Subsequent modifications can be made based on the updated execution results.

Further optionally, in the case where it is determined that the preset operation has been performed on the reference line network, the step of no longer performing the preset operation on the reference line network specifically includes: in the case where it is determined that the reference line network has a processed flag, no longer performing the preset operation on the reference line network; in the case where it is determined that the preset operation has not been performed on the reference line network, the step of performing the preset operation on the reference line network specifically includes: in the case where it is determined that the reference line network does not have a processed flag, adding a processed flag to the reference line network, and performing the preset operation on the reference line network. By configuring the processed flag, the reference line network on which the preset operation has been performed can be conveniently marked, and the amount of calculation can be reliably controlled.

In other embodiments, optionally, if the judgment in the preset operation is implemented based on the pins, then after the step of obtaining all the pins connected to the reference line network along the signal propagation direction and recording them as reference pins, the preset operation may also include: when the reference pin has a processed flag, no longer executing other steps in the preset operation for the reference pin; when the reference pin does not have a processed flag, adding a processed flag to the reference pin, and continuing to execute other steps in the preset operation for the reference pin. By configuring the processed flag before executing the judgment and probing for the reference pin, the reference pin can be conveniently marked. For the embodiments that implement the preset operation based on the pins, it can also substantially prevent the repeated execution of the preset operation, which helps to control the amount of calculation and reduce the waste of computing resources.

It should be understood that there is no execution contradiction between the above two embodiments. Therefore, in order to solve the problem of repeatedly executing the preset operation, you can choose to adopt any of the above embodiments, or you can adopt both embodiments at the same time. This application does not limit this.

For any of the above two embodiments of adding processed flags, optionally, after step S102 and before step S103, the useless logic deletion method according to the exemplary embodiment of the present application further includes: removing all processed flags, and executing step S101 and step S102 again. After completing step S102 once (i.e., executing the preset operation for all reference network), removing all processed flags and re-executing step S101 and step S102, it is possible to check for leaks and fill gaps based on the target network and target instance that have been determined, ensure that all useless logic is found, and ensure the reliable deletion of useless logic. At the same time, in the case of useless loop logic, performing two calculations on the entire integrated circuit design can ensure that all useless loop logic is also found without the need for additional loop detection, which helps to fully simplify the detection process of useless logic and reduce the consumption of computing resources.

In order to realize the marking of the target network and the target instance, optionally, the preset operation further includes: adding a non-deletable flag to the target network and the target instance. The target network and the target instance are determined in the process of executing the preset operation. By adding the non-deletable flag to them, the marking of the target network and the target instance can be realized as the target network and the target instance are determined in the process of executing the preset operation, which is convenient for operation and has high reliability. Accordingly, when the deletion is performed in step S103, the network and the instance without the non-deletable flag can be specifically deleted.

Further optionally, the preset operation also includes: adding a deletable flag to the nets other than the target net and the instances other than the target instance in the integrated circuit design. Compared with the situation where only a non-deletable flag is added and it is necessary to determine whether each net and instance has a non-deletable flag when executing step S103, by configuring clear deletable flags and non-deletable flags for the nets and instances in the integrated circuit design, the operation logic can be optimized, so that the deletion in step S103 is more targeted, and the calculation speed and efficiency are improved. Accordingly, when deleting in step S103, the nets and instances with deletable flags can be specifically deleted.

Further optionally, before step S102, the useless logic deletion method according to the exemplary embodiment of the present application further includes: adding a deletable flag to each wire net and each instance in the integrated circuit design; accordingly, the above-mentioned step of adding an indelible flag to the target wire net and the target instance includes: when the reference wire net is determined as the target wire net, the deletable flag of the reference wire net is modified to an indelible flag; when an instance is determined as the target instance, the deletable flag of the instance is modified to an indelible flag. By setting the deletable flag for all wire nets and instances by default, and then in the process of performing the preset operation for each reference wire net, the deletable flag of the determined target wire net and target instance is modified to an indelible flag, the modification of the deletion flag can be made more targeted, which helps to save the amount of calculation. On the contrary, if the indelible flag is set by default, and then in the process of performing the preset operation, the indelible flags of other wire nets and instances other than the target wire net and the target instance are modified to deletable flags, the amount of calculation will be very large due to the lack of targeting.

In particular, some EDA tools support setting unchangeable logic, in which case the designer can set any instance, pin or net as unchangeable. At this time, these unchangeable logics and the logic related thereto should also be undeletable. Based on this, optionally, the preset conditions also include at least one of the following: the reference net is an unchangeable net, the pins connected to the reference net along the signal propagation direction are unchangeable pins, and the instance where the pins connected to the reference net along the signal propagation direction are located is an unchangeable instance. By configuring the above preset conditions, it is possible to determine an undeletable target net based on unchangeable nets, pins and instances, thereby ensuring compatibility with the setting function of unchangeable logic and improving the reliability of the useless logic deletion method.

Further optionally, before step S102, the useless logic deletion method according to the exemplary embodiment of the present application also includes: in the case where there is an unchangeable instance in the integrated circuit design, traverse the instance in the integrated circuit design layer by layer from top to bottom, and set all lower instances and lower network of the unchangeable hierarchical instance to be unchangeable. By traversing all instances in the entire integrated circuit design once, the "unchangeable" setting of the hierarchical instance is passed from top to bottom to all lower instances and lower network of the hierarchical instance in the process, and when the user only sets the key instance to "unchangeable", the "unchangeable" setting can be automatically passed to cover the lower logic, which can not only simplify the user's setting operation, but also ensure that the logic that cannot be deleted is retained, thereby improving the processing efficiency of the integrated circuit design. It should be understood that the prerequisite for performing the traversal setting operation is that there is an unchangeable instance in the integrated circuit design, which means that if the user has not set an unchangeable instance, there is no need to perform the traversal setting operation, which can reduce unnecessary calculations.

In general, the useless logic deletion method according to the exemplary embodiment of the present application aims to quickly remove all useless logic based on marking. On the one hand, useless logic can be quickly removed through one-time marking and traversal respectively. On the other hand, all useless loop logic can be removed without loop detection and multi-drive detection.

In this exemplary embodiment, all nets and instances have a deletable flag by default. First, the nets connected to the input pins of the top-level module and the undriven nets are used as the initial reference nets. Starting from these reference nets, the entire integrated circuit design is traversed in a depth-first search manner to find non-deletable instances and nets, and their deletable flags are modified to non-deletable flags, and then all nets and instances with deletable flags are removed. The specific steps are as follows.

In the first step, a deletable flag is added to each net and each instance in the integrated circuit design.

The second step is to start with the reference line net and traverse the integrated circuit design to mark the logic that cannot be deleted. Specifically, start searching from the reference line net and perform the following operations for each reference line net.

1) Determine whether the current line network has a processed flag. If the current line network has a processed flag, directly return the annotation of the current line network (including the deletable flag and the non-deletable flag), and continue to process the next reference line network; otherwise, add a processed flag to the current line network, and continue to execute step 2) to perform the preset operation and perform forward traversal from input to output along the signal propagation direction.

2) Get all pins connected to the current net along the direction of signal propagation, and perform the following operations for each pin.

a) Perform the following operations according to the connection status of the pins.

i) If the pin is the output pin of the top-level module, change the deletable flag of the current network to a non-deletable flag.

ii) If the pin is the input pin of the leaf instance, obtain all the output nets of the leaf instance (i.e., the nets connected to the output pins, which serve as new reference nets), and traverse the pins of each output net according to step 2) to obtain the label of each output net. If any output net has a non-deletable flag, modify the deletable flags of the current net and the leaf instance to non-deletable flags.

iii) If the pin is an input pin of a hierarchical instance, obtain the lower-level net connected to the pin (as a new reference net), and execute step 2) for the lower-level net. Traverse the pins of the lower-level net to obtain the annotation of the lower-level net. If the lower-level net has a non-deletable flag, modify the deletable flags of the current net and the hierarchical instance to non-deletable flags.

iv) If the pin is an output pin of a hierarchical instance, obtain the upper-layer net connected to the pin (as a new reference net), and process the upper-layer net according to step 2), traverse the pins of the upper-layer net to obtain the annotation of the upper-layer net, and if the upper-layer net has a non-deletable flag, change the deletable flag of the current net to a non-deletable flag.

v) In other cases, skip directly.

b) Optionally, before executing step a), it is also possible to first determine whether the pin has a processed flag. If the pin has a processed flag, directly return the annotation of the wire net or instance connected to the pin and continue to process the next pin; otherwise, add a processed flag to the pin and continue to execute step a).

By nestedly executing step 2) in the above operation, if the last pin found is the output pin of the top-level module, the deletable flags of the instances and nets on the entire path from the initial reference net to the last pin can be modified to non-deletable flags.

The third step is to traverse all the nets and instances in the integrated circuit design from top to bottom and delete all the nets and instances with deletable marks.

Specifically, the network is traversed, and if the network has a deletable flag, the network is directly deleted. All lower-level instances of the top-level module are also obtained. If the instance has a deletable flag, the instance is directly deleted. Otherwise, it is determined whether the instance is a hierarchical instance. If so, the instances and network of the lower layers of the instance are obtained for determination.

After executing steps 1 to 3 once, you can also clear all processed flags and re-execute steps 2 to 3 to ensure that all useless logic can be completely and accurately deleted.

By following the steps above, you can quickly and easily annotate the nets and instances throughout your design, and quickly remove all unused logic without the need for loop detection.

When actually executing the first and second steps, you can first obtain the wire nets connected to the input pins of the top-level module and the undriven wire nets, and put them into the reference wire net set startNets.

Then execute the traversal function TravNet(net), traverse each net in the reference net set startNets, first determine whether the current net has the processed flag done, if it has, return the label of the net, if not, first add the processed flag done to the current net, and set the delete flag saveFlag = false, then get all the pins of the current net along the signal propagation direction, and put them into the pin set pins. Next, traverse each pin in the pin set pins: if the instance where the pin is located is a leaf instance, get the output net of the leaf instance and put it into the output net set outNets, then traverse each net in the output net set outNets, if it is determined that any of the output nets has an undeletable flag, set the delete flag saveFlag = true, and change the deletable flag of the leaf instance to an undeletable flag. If the instance where the pin is located is a hierarchical instance, if the net connected to the other side of the pin has an undeletable flag, set the delete flag saveFlag = true, and change the deletable flag of the hierarchical instance to an undeletable flag. If the pin is the output pin of the top-level module, set the deletion flag saveFlag = true. Finally, mark the current network according to the saveFlag value. If saveFlag is true, mark the current network as non-deletable. If saveFlag is false, mark the current network as deletable, and return the saveFlag value as the function value of TravNet(net).

In particular, if the EDA tool supports settings that cannot be changed, you also need to handle the relationship between the unchangeable nets and instances. The following are common rules.

1) If the upper instance cannot be changed, its lower instances and nets cannot be changed; the upper instance cannot be removed.

2) If the pin cannot be changed, the net it is connected to and the instance it is in cannot be removed.

3) If a network is immutable, its parent instance cannot be removed.

To this end, first, all instances of the entire integrated circuit design are traversed from top to bottom. If the hierarchical instance is unchangeable, the nets and instances at the lower level are traversed and set to be unchangeable.

Then, starting from the nets connected to the input pins of the top-level module and the nets without drivers, the entire integrated circuit design is traversed in depth first for annotation. Traverse the nets, and if the net has been processed, return the net annotation, otherwise the net is marked as processed; if the current net is an unchangeable net, which is equivalent to satisfying the condition that the reference net in the preset condition is an unchangeable net, then directly modify the net's deletable flag to an undeletable flag, otherwise traverse all the pins connected to the net along the signal propagation direction, and perform the following operations for each pin.

1) If the pin or the instance where the pin is located is unchangeable, it is equivalent to satisfying either of the two conditions that the pin connected to the reference line net along the signal propagation direction in the preset condition is an unchangeable pin, or the instance where the pin is located is an unchangeable instance, then the deletable flag of the instance and the current line net is changed to an undeletable flag.

2) If the pin is the output pin of the top-level module, change the deletable flag of the current network to a non-deletable flag.

3) If the pin is the input pin of the leaf instance, obtain the output network of the leaf instance (as the new reference network) and traverse the pins connected to the output network along the signal propagation direction; if the pin of any output network is unchangeable, or any output network has an undeletable flag, modify the deletable flag of the leaf instance and the current network to an undeletable flag.

4) If the pin is an input pin of a hierarchical instance, obtain the underlying net (as a new reference net) and traverse its pins; if the underlying net is non-deletable, change the deletable flag of the hierarchical instance and the current net to a non-deletable flag.

5) If the pin is an output pin of a hierarchical instance, obtain the upper-layer net (as a new reference net) and traverse its pins; if the upper-layer net has a non-deletable flag, change the deletable flag of the hierarchical instance and the current net to a non-deletable flag.

6) In other cases, just skip it.

Finally, the entire integrated circuit design is traversed from top to bottom, deleting the wire nets and instances with deletable marks.

1) Traverse the wire network. If the wire network has a removable flag, delete the wire network directly.

2) Get all lower-level instances of the top-level module. If the instance has a deletable flag, delete the instance directly. Otherwise, determine whether the instance is a hierarchical instance. If so, get the lower-level instances and wire networks of the instance for segmentation determination.

During actual execution, there are three differences from the implementation example that does not involve the unchangeable setting, and the rest of the operations are the same. First, before traversing each pin in the pin set pins, first determine whether the current net is unchangeable. If so, set saveFlag to true. Second, when traversing each pin in the pin set pins, add a branch situation: if it is determined that the pin is unchangeable or the instance where the pin is located is unchangeable, set the deletion flag saveFlag = true, and modify the deletable flag of the instance where the pin is located to an undeletable flag. Third, when traversing each pin in the pin set pins, if the instance where the pin is located is a leaf instance, then when traversing each net in the output net set outNets, if it is determined that any of the output nets has an unchangeable flag, or the pins of any output net are unchangeable, set the deletion flag saveFlag = true, and modify the deletable flag of the leaf instance to an undeletable flag.

Next, two specific embodiments of the present application are introduced.

In the first specific embodiment, the integrated circuit design is shown in FIG2 , TOP is the top-level module, and the input pins s1, i1, i2, ck1, i4, i5, ck2 of TOP are connected to the nets n0, n1, n2, n4, n6, n7, n9 under TOP along the signal propagation direction, respectively. There are also nets n3, n8, n10, n11, n12, n13, n14 under TOP, and net n14 is connected to the output pin o of TOP. L1, L2, L3, L4 are leaf instances in the top-level module TOP, and these leaf instances all have input pins A, B and output pin O. H1 and H2 are hierarchical instances. H1/p0, H1/p1, H1/p2 are input pins of H1, H1/p3, H1/p4 are output pins of H1, and H1/L1, H1/L2 are leaf instances in H1. H2/p1 and H2/p2 are input pins of H2, H2/p3 and H2/p4 are output pins of H2, and H2/L1 and H2/L2 are leaf instances in H2. H1/L1 and H2/L1 both have input pins S, I0, I1 and output pin O, and H1/L2 and H2/L2 both have input pins D, > and output pins Q, , H1 and H2 both have nets n0, n1, n2, n3, n4, and n5. Except for the difference that net H1/n0 is a driven net and net H2/n0 is a non-driven net, the connection methods of other nets and leaf instances with the same name in H1 and H2 are the same. The following takes nets n1, n2, and H2/n0 as examples to illustrate the traversal and annotation process from front to back.

(1) The process of processing n1 is as follows.

① For the first processing, set n1 to done (processed); get the pin associated with net n1 as L1/A, which is the input pin of leaf instance L1; get the net n3 connected to the output pin L1/O of L1; iterate n3 (step ②). Since the return value of step ② is false, mark net n1 as deletable.

② For the first processing, set n3 to done; obtain the pin H1/p1 associated with n3. H1/p1 is the input pin of the hierarchical instance H1, and obtain its lower-level net H1/n1; iteratively process H1/n1 (step ③). Since the return value of step ③ is false, mark the instance H1 and net n3 as deletable, and return false to step ①.

③In the first processing, set H1/n1 to done; obtain the pin H1/L1/I1 associated with H1/n1, which is the input pin of the leaf instance H1/L1, and obtain the net H1/n3 connected to the output pin H1/L1/O of H1/L1; iteratively process H1/n3 (step ④). Since the return value of step ④ is false, mark the instance H1/L1 and the net H1/n1 as deletable, and return false to step ②.

④ For the first processing, set H1/n3 to done; obtain the pin H1/L2/D associated with H1/n3, which is the input pin of the leaf instance H1/L2; iteratively process the net H1/n2 connected to the output pin H1/L2/Q (step ⑤) and the output pin H1/L2/ The connected net H1/n5 (step ⑦) returns false, so the instance H1/L2 and net H1/n3 are marked as deletable, and false is returned to step ③.

⑤In the first processing, set H1/n2 to done; obtain the associated pins H1/L1/I0 and H1/p3, process pins H1/L1/I0 (step a) and H1/p3 (step b). Since the return values of both are false, mark the instances H1/L2, H1 and net H1/n2 as deletable, and return false to step ④.

a) H1/L1/I0 is the input pin of the leaf instance H1/L1. Get the output pin H1/L1/O. Its associated net H1/n3 has been marked as done. Return its current marked false to step ⑤.

b) H1/p3 is the output pin of the hierarchical instance H1. Get its upper-layer net n10 and iterate n10 (step ⑥). Since the return value of step ⑥ is false, return false to step ⑤.

⑥ First processing, set n10 to done; get the associated pin L3/A, which is the input pin of the leaf instance L3. Since L3 has no output net, mark the instance L3 and net n10 as deletable, and return false to step b).

⑦ For the first processing, set H1/n5 to done; obtain the associated pin H1/p4, which is the output pin of the hierarchical instance H1, obtain the upper-level net n11, and iterate n11 (step ⑧). Since the return value of step ⑧ is false, mark the instance H1 and net H1/n5 as deletable, and return false to step ④.

⑧In the first processing, set n11 to done; obtain the associated pin L3/B, which is the input pin of the leaf instance L3. Since L3 has no output net, mark the instance L3 and net n11 as deletable, and return false to step ⑦.

(2) The process of processing n2 is as follows.

During the first processing, n2 is set to done; the pin associated with net n2 is obtained as L1/B, which is the input pin of leaf instance L1. Its output net n3 has been marked as done and is deletable, so instance L1 is deletable and net n2 is deletable.

(3) The process of treating H2/n0 is as follows.

① For the first processing, set H2/n0 to done; obtain the associated pin H2/L1/S, which is the input pin of the leaf instance H2/L1, obtain the net H2/n3 connected to the output pin H2/L1/O of H2/L1, and iteratively process the net H2/n3 (step ②). Since the return value of step ② is true, the instance H2/L1 and the net H2/n0 are marked as non-deletable.

②In the first processing, set H2/n3 to done; get the associated pin H2/L2/D, which is the input pin of the leaf instance H2/L2, and iteratively process the output nets H2/n2 (step ③) and H2/n5 (step ⑥). Since the return values of both are true, mark the instance H2/L2 and the net H2/n3 as non-deletable, and return true to step ①.

③ For the first processing, set H2/n2 to done; obtain the associated pins H2/L1/I0 and H2/p3; process pins H2/L1/I0 (step a) and H2/p3 (step b). Since the return value of step b) is true, mark instance H2 and net H2/n2 as non-deletable, and return true to step ②.

a) H2/L1/I0 is the input pin of leaf instance H2/L1. Get the net H2/n3 connected to output pin H2/L1/O, which has been marked as done. Return the current mark false of H2/n3 to step ③.

b) H2/p3 is the output pin of the hierarchical instance H2. Its upper layer net n12 is iteratively processed (step ④). Since the return value of step ④ is true, true is returned to step ③.

④ For the first processing, set n12 to done; obtain the associated pin L4/A, which is the input pin of the leaf instance L4, and iterate the output net n14 (step ⑤). Since the return value of step ⑤ is true, set the instance L4 and net n12 to be non-deletable, and return true to step b).

⑤For the first processing, set n14 to done; get the associated pin o, where o is the output pin of the top-level module TOP, set n14 to be non-deletable, and return true to step ④.

⑥In the first processing, set H2/n5 to done; obtain the associated pin H2/p4, which is the output pin of the hierarchical instance H2, obtain the upper-level net n13, and iteratively process n13 (step ⑦). Since the return value of step ⑦ is true, set the net H2/n5 and instance H2 to be non-deletable, and return true to step ②.

⑦ For the first processing, set n13 to done; get the associated pin L4/B, which is the input pin of the leaf instance L4. Since the output net n14 has been marked as done and n14 is not deletable, set n13 to not deletable and return true to step ⑥.

(4) Mark the results.

After all iterations are completed, the nets are labeled as: n0, n1, n2, n3, n4, n10, n11 and H1/n Can be deleted; n6, n7, n8, n9, n12, n13, n14 and H2/n Cannot be deleted.

Instances are marked as follows: L1, L3, H1, H1/L1, H1/L2 are deletable; L2, L4, H2, H2/L1, H2/L2 are non-deletable.

(5) Remove useless logic.

Traverse the entire integrated circuit design from top to bottom: traverse the top-level nets and delete all deletable nets, namely n0, n1, n2, n3, n4, n10 and n11; traverse the instances and delete instances L1, L3, H1. H2 is a non-deletable hierarchical instance. Traverse the nets of H2 and there are no deletable nets. Traverse the instances of H2 and there are no deletable instances.

The integrated circuit design of the second specific embodiment is still as shown in FIG. 2 , but the leaf instance H1 / L2 is set to be unchangeable, and the process of processing the top-level input network n1 is as follows.

① For the first processing, set n1 to done; get the pin associated with net n1 as L1/A, which is the input pin of leaf instance L1; get the net n3 connected to the output pin L1/O of L1; iterate n3 (step ②). Since the return value of step ② is true, mark net n1 as non-deletable.

②In the first processing, set n3 to done; obtain the pin H1/p1 associated with n3. H1/p1 is the input pin of the hierarchical instance H1, and obtain its lower-level net H1/n1; iteratively process H1/n1 (step ③). Since the return value of step ③ is true, the instance H1 and net n3 are marked as non-deletable, and true is returned to step ①.

③In the first processing, set H1/n1 to done; obtain the pin H1/L1/I1 associated with H1/n1, which is the input pin of the leaf instance H1/L1, and obtain the output net H1/n3 of H1/L1; iteratively process H1/n3 (step ④). Since the return value of step ④ is true, mark the instance H1/L1 and net H1/n1 as non-deletable, and return true to step ②.

④In the first processing, set H1/n3 to done; obtain the pin H1/L2/D associated with H1/n3. Since the instance H1/L2 is not changeable, set the instance H1/L2 and the net H1/n3 to be non-deletable; at the same time, since H1/L2/D is the input pin of the leaf instance H1/L2, iteratively process the output nets H1/n2 (step ⑤) and H1/n5 (step ⑦). Since the return value of step ⑤ is true, mark the instance H1/L2 and the net H1/n3 as non-deletable, and return true to step ③.

⑤For the first processing, set H1/n2 to done; obtain the associated pins H1/L1/I0 and H1/p3, process the associated pins H1/L1/I0 (step a) and H1/p3 (step b). Since the return value of step a) is true, set the line net H1/n2 to non-deletable and return true to step ④.

a) H1/L1/I0 is the input pin of the leaf instance H1/L1. Get the output pin H1/L1/O. Its associated net H1/n3 has been marked as done. Return the current mark true to step ⑤.

b) H1/p3 is the output pin of the hierarchical instance H1. Get its upper-layer net n10 and iterate n10 (step ⑥). Since the return value of step ⑥ is false, return false to step ⑤.

⑥ First processing, set n10 to done; get the associated pin L3/A, which is the input pin of the leaf instance L3. Since L3 has no output net, mark the instance L3 and net n10 as deletable, and return false to step b).

⑦In the first processing, set H1/n5 to done; obtain the associated pin H1/p4, which is the output pin of the hierarchical instance H1, obtain the upper-level net n11, and iteratively process n11 (step ⑧). Since the return value of step ⑧ is false, the instance H1 and the net H1/n5 are marked as deletable (the instance H1 will be modified to non-deletable in step ②), and return false to step ④.

⑧In the first processing, set n11 to done; obtain the associated pin L3/B, which is the input pin of the leaf instance L3. Since L3 has no output net, mark the instance L3 and net n11 as deletable, and return false to step ⑦.

The process of processing n2 is as follows: for the first processing, set n2 to done; obtain the pin associated with net n2 as L1/B, which is the input pin of leaf instance L1, and its output net n3 has been marked as done and cannot be deleted, then instance L1 cannot be deleted, and net n2 cannot be deleted.

The process of treating H2/n0 is the same as that in the first specific embodiment.

After all iterations are completed, the nets are marked as follows: n0, n4, n10, n11 and H1/n5 are deletable; n1, n2, n3, n6, n7, n8, n9, n12, n13, n14, H1/n0, H1/n1, H1/n2, H1/n3, H1/n4 and H2/n Cannot be deleted.

The instances are marked as follows: L1 and L3 are deletable; L2, L4, H1, H1/L1, H1/L2, H2, H2/L1, and H2/L2 are non-deletable.

(5) Remove useless logic.

Traverse the entire integrated circuit design from top to bottom: traverse the top-level nets and delete all deletable nets, namely n0, n4, n10, n11 and H1/n5; traverse the instances and delete instances L1 and L3. H1 and H2 are non-deletable hierarchical instances. Traverse the nets of H1 and delete the deletable nets, namely H1/n5. Traverse the instances of H1 and there are no deletable instances. Traverse the nets of H2 and there are no deletable nets. Traverse the instances of H2 and there are no deletable instances.

FIG. 3 is a block diagram showing a useless logical deletion apparatus according to an exemplary embodiment of the present application.

3 , the useless logical deletion device 300 includes a preparation unit 301 , an execution unit 302 , and a deletion unit 303 .

The preparation unit 301 may determine the nets connected to the input pins of the top-level module and the undriven nets from the nets designed for the integrated circuit, and record them as reference nets.

The execution unit 302 can perform the following preset operations for each reference line network: when the reference line network meets the preset conditions, the reference line network is determined as the target line network, wherein the preset conditions include being connected to the output pin of the top-level module; when the reference line network is connected to other line networks along the signal propagation direction, each line network in the other line networks is used as a new reference line network, and the preset operations are continued to be performed to determine whether there is a target line network in other line networks; when it is determined that there is a target line network in other line networks, the reference line network is determined as the target line network, and the instance to which the reference line network is connected along the signal propagation direction is determined as the target instance.

The deletion unit 303 may delete the nets other than the target net and the instances other than the target instance in the integrated circuit design as useless logic to obtain an updated integrated circuit design.

Optionally, the step executed by the execution unit 302 of taking each of the other nets as a new reference net when the reference net is connected to other nets along the signal propagation direction includes: when the reference net is directly connected to other nets along the signal propagation direction, taking each of the other directly connected nets as a new reference net; when the reference net is directly connected to the input pin of a leaf instance along the signal propagation direction, taking each output net of the leaf instance as a new reference net, wherein the output net of the leaf instance is other nets indirectly connected to the reference net along the signal propagation direction.

Optionally, the preset operation performed by the execution unit 302 also includes: obtaining all pins connected to the reference line network along the signal propagation direction, recorded as reference pins; the step executed by the execution unit 302 to determine the reference line network as the target line network when the reference line network meets the preset conditions includes: when the reference pin includes the output pin of the top-level module, the reference line network is determined as the target line network; the step executed by the execution unit 302 to use each line network in the other directly connected line networks as a new reference line network when the reference line network is directly connected to other line networks along the signal propagation direction includes: when the reference pin includes the pin of the hierarchical instance, each line network connected on the other side of the reference pin is used as a new reference line network; the step executed by the execution unit 302 to use each output line network of the leaf instance as a new reference line network when the reference line network is directly connected to the input pin of the leaf instance along the signal propagation direction includes: when the reference pin includes the input pin of the leaf instance, each output line network of the leaf instance is used as a new reference line network.

Optionally, after the step of obtaining all pins connected to the reference line network along the signal propagation direction and recording them as reference pins, the preset operation performed by the execution unit 302 also includes: when the reference pin has a processed flag, no longer executing other steps in the preset operation for the reference pin; when the reference pin does not have a processed flag, adding a processed flag to the reference pin, and continuing to execute other steps in the preset operation for the reference pin.

Optionally, the execution unit 302 may further: for each reference line net, if it is determined that the preset operation has been performed on the reference line net, no longer perform the preset operation on the reference line net; if it is determined that the preset operation has not been performed on the reference line net, perform the preset operation on the reference line net.

Optionally, the step of not executing the preset operation on the reference line network when it is determined that the preset operation has been executed on the reference line network, executed by the execution unit 302, includes: when it is determined that the reference line network has a processed flag, not executing the preset operation on the reference line network; optionally, the step of executing the preset operation on the reference line network when it is determined that the preset operation has not been executed on the reference line network, executed by the execution unit 302, includes: when it is determined that the reference line network does not have a processed flag, adding a processed flag to the reference line network, and executing the preset operation on the reference line network.

Optionally, the useless logical deletion device 300 further includes a removal unit (not shown in the figure), which can remove all processed marks and enable the preparation unit 301 and the execution unit 302 to run again.

Optionally, the preset operation performed by the execution unit 302 further includes: adding a non-deletable flag to the target net and the target instance.

Optionally, the useless logic deletion device 300 also includes an adding unit (not shown in the figure), which can add a deletable flag for each line net and each instance in the integrated circuit design; the step of adding a non-deletable flag for the target line net and the target instance performed by the execution unit 302 includes: when the reference line net is determined as the target line net, the deletable flag of the reference line net is modified to an non-deletable flag; when an instance is determined as the target instance, the deletable flag of the instance is modified to an non-deletable flag.

Optionally, the preset conditions also include at least one of the following: the reference line network is an unchangeable line network, the pins connected to the reference line network along the signal propagation direction are unchangeable pins, and the instance where the pins connected to the reference line network along the signal propagation direction are located is an unchangeable instance.

Optionally, the useless logical deletion device 300 also includes a traversal unit (not shown in the figure), which can traverse the instances in the integrated circuit design from top to bottom layer by layer when there are unchangeable instances in the integrated circuit design, and set all lower-level instances and lower-level wire networks of the unchangeable hierarchical instances to be unchangeable.

Optionally, the deletion unit 303 can also: traverse the wire nets and instances in the integrated circuit design layer by layer from top to bottom, and perform the following operations: when the traversed wire net is not the target wire net, delete the traversed wire net as useless logic; when the traversed instance is not the target instance, delete the traversed instance as useless logic; when the traversed instance is the target instance and it is a hierarchical instance, continue to traverse downward the wire nets and lower-level instances in the current hierarchical instance.

Regarding the device in the above embodiment, the specific manner in which each unit performs the operation has been described in detail in the embodiment of the method, and will not be elaborated here.

Fig. 4 is a block diagram of a computer device according to an exemplary embodiment of the present application. As shown in Fig. 4, the computer device 400 includes at least one processor 401 and at least one memory 402 storing computer executable instructions. Here, when the computer executable instructions are executed by the processor 401, the processor 401 is prompted to execute the useless logical deletion method as described in the above exemplary embodiment.

As an example, the computer device 400 is not necessarily a single device, but may be any collection of devices or circuits that can execute the above instructions (or instruction sets) individually or in combination. The computer device 400 may also be part of an integrated control system or system manager, or may be configured as a server that is interconnected with a local or remote (e.g., via wireless transmission) interface.

In computer device 400, processor 401 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor 401 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

The processor 401 may execute instructions or codes stored in the memory 402, wherein the memory 402 may also store data. Instructions and data may also be sent and received over a network via a network interface device, wherein the network interface device may employ any known transmission protocol.

The memory 402 may be integrated with the processor 401, for example, by placing RAM or flash memory within an integrated circuit design microprocessor or the like. In addition, the memory 402 may include a separate device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The memory 402 and the processor 401 may be operationally coupled, or may communicate with each other, such as through an I/O port, a network connection, etc., so that the processor 401 can read files stored in the memory 402.

In addition, the computer device 400 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.) All components of the computer device 400 may be connected to each other via a bus and/or a network.

In an exemplary embodiment, a computer-readable storage medium may also be provided. When the instructions in the computer-readable storage medium are executed by the processor, the processor is enabled to execute the useless logical deletion method as described in the above exemplary embodiment. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: a read-only memory (ROM), a random access memory (RAM), a random access programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a non-volatile memory, a CD-ROM, a CD-R, a CD+R, a CD-RW, a CD+RW, a DVD-ROM, a DVD-R, a DVD+R, a DVD-RW, a DVD+RW, a DVD-RAM, a BD-ROM, a BD-R, a BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device is configured to store computer programs and any associated data, data files and data structures in a non-transitory manner and provide the computer programs and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the above-mentioned computer-readable storage medium can be run in an environment deployed in a computer device such as a client, a host, an agent device, a server, etc. In addition, in one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system, so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

In an exemplary embodiment, a computer program product may also be provided, comprising computer instructions. When the computer instructions are executed by a processor, the processor is prompted to execute the useless logical deletion method as described in the above exemplary embodiment.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

In addition, it should be noted that although several examples of each step are described above with reference to specific drawings, it should be understood that the implementation methods of the present application are not limited to the combinations given in the examples, and the steps appearing in different drawings may be combined, which are not exhaustively listed here.

It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the claims.

Claims (16)

1. A useless logical deletion method, characterized in that the useless logical deletion method comprises: From the wire nets of the integrated circuit design, determine the wire nets connected to the input pins of the top-level module and the wire nets without drivers, and record them as reference wire nets; For each guide grid, perform the following preset operations: In the case where the reference line net meets a preset condition, the reference line net is determined as a target line net, wherein the preset condition includes being connected to an output pin of a top-level module, In the case where the reference line net is connected to other line nets along the signal propagation direction, each line net in the other line nets is used as a new reference line net, and the preset operation is continued to be performed to determine whether there is a target line net in the other line nets, and in the case where it is determined that there is a target line net in the other line nets, the reference line net is determined as the target line net, and the instance connected to the reference line net along the signal propagation direction is determined as the target instance; Nets other than the target net and instances other than the target instance in the integrated circuit design are deleted as useless logic to obtain an updated integrated circuit design. 2. The useless logic deletion method according to claim 1, characterized in that, when the reference line network is connected to other line networks along the signal propagation direction, each line network in the other line networks is used as a new reference line network, comprising: In the case where the reference line net is directly connected to other line nets along the signal propagation direction, each line net in the other directly connected line nets is used as a new reference line net; When the reference line network is directly connected to the input pin of the leaf instance along the signal propagation direction, each output line network of the leaf instance is used as the new reference line network, wherein the output line network of the leaf instance is other line network indirectly connected to the reference line network along the signal propagation direction. 3. The useless logical deletion method according to claim 2, characterized in that: The preset operation also includes: Obtain all pins connected to the reference line network along the signal propagation direction, and record them as reference pins; The step of determining the reference line network as a target line network when the reference line network meets a preset condition includes: In a case where the reference pin includes an output pin of a top-level module, determining the reference line net as the target line net; When the reference line net is directly connected to other line nets along the signal propagation direction, each line net in the other directly connected line nets is used as a new reference line net, including: In the case where the reference pin includes a pin of a hierarchical instance, each of the wire nets connected to the other side of the reference pin is used as the new reference wire net; In the case where the reference line net is directly connected to the input pin of the leaf instance along the signal propagation direction, each output line net of the leaf instance is used as the new reference line net, comprising: In the case where the reference pin includes an input pin of a leaf instance, each output net of the leaf instance is used as the new reference net. 4. The useless logic deletion method according to claim 3, characterized in that after the step of obtaining all pins connected to the reference line network along the signal propagation direction and recording them as reference pins, the preset operation further comprises: In the case where the reference pin has a processed flag, no other steps in the preset operation are performed for the reference pin; In the case that the reference pin does not have the processed flag, the processed flag is added to the reference pin, and other steps in the preset operation are continued to be performed for the reference pin. 5. The useless logical deletion method according to claim 1, characterized in that the following preset operations are performed for each reference line network, including: For each reference line network, if it is determined that the preset operation has been performed on the reference line network, no longer performing the preset operation on the reference line network; In a case where it is determined that the preset operation has not been performed on the reference line network, the preset operation is performed on the reference line network. 6. The useless logical deletion method according to claim 5, characterized in that: The step of not performing the preset operation on the reference line network when it is determined that the preset operation has been performed on the reference line network includes: When it is determined that the reference line network has a processed flag, no longer performing the preset operation on the reference line network; In a case where it is determined that the preset operation has not been performed on the reference line network, performing the preset operation on the reference line network includes: When it is determined that the reference line network does not have the processed flag, the processed flag is added to the reference line network, and the preset operation is performed on the reference line network. 7. The method for deleting useless logic according to claim 4 or 6, characterized in that after the step of performing the following preset operation on each reference net and before the step of deleting nets other than the target net and instances other than the target instance in the integrated circuit design as useless logic to obtain an updated integrated circuit design, the method for deleting useless logic further comprises: Remove all the processed flags, and re-execute the step of determining the wire nets connected to the input pins of the top-level module and the undriven wire nets from the wire nets designed by the integrated circuit, and record them as reference wire nets, and the step of performing the following preset operations for each reference wire net. 8. The useless logical deletion method according to any one of claims 1 to 6, wherein the preset operation further comprises: An undeletable flag is added to the target net and the target instance. 9. The useless logical deletion method according to claim 8, characterized in that: Before the step of performing the following preset operation for each reference line network, the useless logic deletion method further includes: Adding a deletable flag to each net and each instance in the integrated circuit design; The adding a non-deletable flag to the target network and the target instance includes: In the case where the reference line net is determined as the target line net, modifying the deletable flag of the reference line net to the non-deletable flag; When an instance is determined as a target instance, the deletable flag of the instance is modified to the non-deletable flag. 10. The useless logical deletion method as described in any one of claims 1 to 6 is characterized in that the preset conditions also include at least one of the following: the reference line network is an unchangeable line network, the pins connected to the reference line network along the signal propagation direction are unchangeable pins, and the instance where the pins connected to the reference line network along the signal propagation direction are located is an unchangeable instance. 11. The useless logic deletion method according to claim 10, characterized in that before the step of performing the following preset operation for each reference line network, the useless logic deletion method further comprises: In the case where there are unchangeable instances in the integrated circuit design, the instances in the integrated circuit design are traversed layer by layer from top to bottom, and all lower instances and lower network layers of the unchangeable hierarchical instances are set to be unchangeable. 12. The method for deleting useless logic according to any one of claims 1 to 6, wherein the deleting nets other than the target net and instances other than the target instance in the integrated circuit design as useless logic to obtain an updated integrated circuit design comprises: Traverse the nets and instances in the integrated circuit design layer by layer from top to bottom and perform the following operations: When the traversed wire net is not the target wire net, the traversed wire net is deleted as useless logic; When the traversed instance is not the target instance, the traversed instance is deleted as useless logic; When the traversed instance is the target instance and a hierarchical instance, the line nets and lower layer instances in the current hierarchical instance are continuously traversed downward. 13. A useless logical deletion device, characterized in that the useless logical deletion device comprises: The preparation unit is configured to determine, from the wire nets designed by the integrated circuit, the wire nets to which the input pins of the top-level module are connected and the wire nets without drivers, which are recorded as reference wire nets; The execution unit is configured to perform the following preset operations for each reference line network: In the case where the reference line net meets a preset condition, the reference line net is determined as a target line net, wherein the preset condition includes being connected to an output pin of a top-level module, In the case where the reference line net is connected to other line nets along the signal propagation direction, each line net in the other line nets is used as a new reference line net, and the preset operation is continued to be performed to determine whether there is a target line net in the other line nets, and in the case where it is determined that there is a target line net in the other line nets, the reference line net is determined as the target line net, and the instance connected to the reference line net along the signal propagation direction is determined as the target instance; The deleting unit is configured to delete the nets other than the target net and the instances other than the target instance in the integrated circuit design as useless logic to obtain an updated integrated circuit design. 14. A computer-readable storage medium, characterized in that when the instructions in the computer-readable storage medium are executed by at least one processor, the at least one processor is prompted to execute the useless logical deletion method according to any one of claims 1 to 12. 15. A computer device, comprising: at least one processor; at least one memory storing computer executable instructions, Wherein, when the computer executable instructions are executed by the at least one processor, the at least one processor is prompted to execute the useless logical deletion method according to any one of claims 1 to 12. 16. A computer program product, comprising computer instructions, characterized in that when the computer instructions are executed by at least one processor, the at least one processor is prompted to execute the useless logical deletion method according to any one of claims 1 to 12.