CN118731909B - A pulse laser radar device based on FPGA - Google Patents
A pulse laser radar device based on FPGA Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/481—Constructional features, e.g. arrangements of optical elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02A—TECHNOLOGIES FOR ADAPTATION TO CLIMATE CHANGE
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Abstract
本发明公开了一种基于FPGA的脉冲激光雷达装置，涉及激光测距技术领域，该装置包括FPGA芯片，FPGA芯片内部署有激光发射器和激光收发模块，激光收发模块连接有光学镜头与APD模块，光学镜头与APD模块连接有光收发一体芯片，光收发一体芯片与FPGA芯片连接，光收发一体芯片还连接有反射信号优化电路。本发明减少了由于噪声影响的误差，更精确定位了反射信号，从而使获得的飞行时间更加精确；使用FPGA芯片进行控制和处理，大大简化系统结构，减小系统体积，而且降低了制造成本，并提升测量效率。
The present invention discloses a pulse laser radar device based on FPGA, which relates to the field of laser ranging technology. The device includes an FPGA chip, a laser transmitter and a laser transceiver module are deployed in the FPGA chip, the laser transceiver module is connected to an optical lens and an APD module, the optical lens and the APD module are connected to an optical transceiver integrated chip, the optical transceiver integrated chip is connected to the FPGA chip, and the optical transceiver integrated chip is also connected to a reflection signal optimization circuit. The present invention reduces the error caused by noise, more accurately locates the reflection signal, so that the obtained flight time is more accurate; the FPGA chip is used for control and processing, which greatly simplifies the system structure, reduces the system volume, reduces the manufacturing cost, and improves the measurement efficiency.
Description
Technical Field
The invention relates to the technical field of laser ranging, in particular to a pulse laser radar device based on an FPGA.
Background
At present, laser ranging generally has two forms of phase type and pulse type, wherein the pulse type is to obtain the difference between the transmitting time of pulse laser and the receiving time of reflected pulse signal, i.e. obtain the flight time of pulse laser, so as to measure the distance. When receiving the reflected pulse signal, a series of circuits are needed to determine the time of the reflected pulse signal, and various noise including ambient light, circuit interference and the like exists in the process of flying the pulse laser. The cost is high, the system structure is complex, and the noise can cause the problems of inaccurate measurement results, difficult subsequent processing and the like.
Disclosure of Invention
The invention aims to provide a pulse laser radar device based on an FPGA, which is used for obtaining high-reliability flight time from laser emission to reflection in the presence of interference.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
The invention provides a pulse laser radar device based on an FPGA, which comprises an FPGA chip, wherein a laser emitter and a laser receiving and transmitting module are arranged in the FPGA chip, the laser receiving and transmitting module is connected with an optical lens and an APD module, the optical lens and the APD module are connected with an optical receiving and transmitting integrated chip, the optical receiving and transmitting integrated chip is connected with the FPGA chip, and the optical receiving and transmitting integrated chip is also connected with a reflection signal optimizing circuit;
The FPGA chip controls the laser transmitter to transmit a plurality of groups of pulse laser according to a preset transmitting frequency, each group of pulse laser is reflected by an object to be tested to form a group of reflected pulse signals, each group of reflected pulse signals comprises a real reflected pulse signal and a false reflected pulse signal, the reflected pulse signals are received by the laser receiving and transmitting module, the optical lens and the APD module and then are converted into electric signals in the optical receiving and transmitting integrated chip, and the reflected signal optimizing circuit amplifies and denoises the electric signals and outputs amplified signals; the FPGA chip performs grouping acquisition on a plurality of groups of amplified signals corresponding to a plurality of groups of pulse lasers according to the emission frequency to form a histogram, obtains a real reflected pulse signal according to the histogram and obtains a rough count of flight time, obtains a fine count on the basis of the rough count in a carry chain of the FPGA chip, and finally obtains the flight time between the laser emission and reflection according to the rough count and the fine count.
In some embodiments of the present invention, an FPGA-based pulse lidar device further includes an external communication circuit, where the external communication circuit is connected to an FPGA chip, and the flight time in the FPGA chip is transmitted to an external microprocessor or a computer for display or processing by the external communication circuit, and the distance to be measured is obtained by the processing.
In some embodiments of the present invention, a pulse laser emission clock and a processing clock in the FPGA chip are configured, where the frequency of the pulse laser emission clock corresponds to the emission frequency of the pulse laser during emission, and the frequency of the processing clock corresponds to the frequency of the acquisition speed during packet acquisition.
In some embodiments of the invention, the frequency of the processing clock is greater than the frequency of the pulsed laser emission clock.
In some embodiments of the present invention, for N sets of amplified signals corresponding to N sets of pulse lasers in a time range of a primary emission frequency, each set of amplified signals includes a signal to be sampled corresponding to a true reflected pulse signal and a false reflected pulse signal.
In some embodiments of the present invention, a weight storage address counter is set at each frequency of the processing clock, and an initial weight of the weight storage address counter is 0; when a frequency of the processing clock collects signals to be sampled, adding 1 to the weight of the corresponding weight storage address counter, repeating the operation to complete collection of the first group of amplified signals to the N group of amplified signals and obtain a first histogram of each group of amplified signals; and accumulating the weights of the address counters stored by the same weight in the first histograms of the first group of amplified signals to the N group of amplified signals to obtain a second histogram, wherein the signals to be sampled corresponding to the weights accumulated in the second histogram are true reflection pulse signals, the signals to be sampled not corresponding to the weights accumulated in the second histogram are false reflection pulse signals, and the false reflection pulse signals are noise signals.
In some embodiments of the present invention, a weight storage address counter is set at each frequency of the processing clock; for the first group of amplified signals, when the processing clock collects the signals to be sampled at one frequency, the corresponding weight storage address counter counts once, judges that the signals to be sampled are continuous and generate data as 1, when the processing clock does not collect the signals to be sampled at one frequency, the corresponding weight storage address counter does not count, judges that the signals to be sampled are discontinuous and generate data as 0, and gathers all the generated data as data 1 and uses a memory for storage; for the second group of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts the first group of amplified signals and the second group of amplified signals once, the first group of amplified signals and the second group of amplified signals are judged to be continuous and generate data as 1, otherwise, the second group of amplified signals are judged to be discontinuous and generate data as 0, all the generated data are summarized as data 2, the data 1 is updated as data 2, and the data are stored by using a memory; for the third group of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts the first group of amplified signals, the second group of amplified signals and the third group of amplified signals once, and judges that the signals are continuous and generate data as 1, otherwise, judges that the signals are discontinuous and generate data as 0, gathers all the generated data as data 3, updates the data 2 as data 3 and uses a memory for storage; similarly, for the nth set of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts from the first set of amplified signals to the nth set of amplified signals once, judges that the signals are continuous and generate data as 1, otherwise judges that the signals are discontinuous and generate data as 0, gathers all the generated data as data N, updates the data N-1 generated by the N-1 th set of amplified signals as data N and uses a memory for storage, and obtains a third histogram based on the data N; the signal to be sampled corresponding to the data 1 in the third histogram is a true reflection pulse signal, the signal to be sampled corresponding to the data not 1 is a false reflection pulse signal, and the false reflection pulse signal is a noise signal.
In some embodiments of the present invention, a phase offset is used to increase the frequency of the processing clock.
In some embodiments of the present invention, two sets of 90 degree phase shifted clocks are used to form a new processing clock.
Compared with the prior art, the invention has the following beneficial effects:
the invention reduces the error caused by noise, and more accurately positions the reflected signal, thereby enabling the obtained flight time to be more accurate; the FPGA chip is used for control and processing, so that the system structure is greatly simplified, the system volume is reduced, the manufacturing cost is reduced, and the measurement efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention.
Fig. 2 is a diagram of a first acquisition method based on a processing clock according to the present invention.
Fig. 3 is a second histogram obtained by the first acquisition method based on the processing clock of the present invention.
Fig. 4 is a diagram of a second acquisition method based on a processing clock according to the present invention.
Fig. 5 is a third histogram obtained by the second acquisition method based on the processing clock of the present invention.
Fig. 6 is a schematic diagram of increasing the frequency of a processing clock according to the present invention.
Detailed Description
Term interpretation:
FPGA chip: a field programmable gate array chip;
APD: avalanche photodiodes.
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the pulse laser radar device based on the FPGA disclosed by the invention comprises an FPGA chip, wherein a laser emitter and a laser receiving and transmitting module are deployed in the FPGA chip, the laser receiving and transmitting module is connected with an optical lens and an APD module, the optical lens and the APD module are connected with an optical receiving and transmitting integrated chip, the optical receiving and transmitting integrated chip is connected with the FPGA chip, and the optical receiving and transmitting integrated chip is also connected with a reflection signal optimizing circuit;
The FPGA chip controls the laser transmitter to transmit a plurality of groups of pulse laser according to a preset transmitting frequency, each group of pulse laser is reflected by an object to be tested to form a group of reflected pulse signals, each group of reflected pulse signals comprises a real reflected pulse signal and a false reflected pulse signal, the reflected pulse signals are received by the laser receiving and transmitting module, the optical lens and the APD module and then are converted into electric signals in the optical receiving and transmitting integrated chip, and the reflected signal optimizing circuit amplifies and denoises the electric signals and outputs amplified signals; the FPGA chip performs grouping acquisition on a plurality of groups of amplified signals corresponding to a plurality of groups of pulse lasers according to the emission frequency to form a histogram, obtains a real reflected pulse signal according to the histogram and obtains a rough count of flight time, obtains a fine count on the basis of the rough count in a carry chain of the FPGA chip, and finally obtains the flight time between the laser emission and reflection according to the rough count and the fine count. The invention discloses a pulse laser radar device based on an FPGA, which also comprises an external communication circuit, wherein the external communication circuit is connected with an FPGA chip, the flight time in the FPGA chip is transmitted to an external microprocessor or a computer for display or processing through the external communication circuit, and the distance to be measured is obtained through processing. Because of the flexibility of the FPGA chip, a series of communication modes such as a network port, an FMC, an RS232 and the like can be configured and transmitted to an external microprocessor or a computer.
In addition to the basic pulsed lidar device architecture, more important is the processing inside the FPGA chip. Preferably, a pulse laser emission clock and a processing clock in the FPGA chip are configured, wherein the frequency of the pulse laser emission clock corresponds to the emission frequency of the pulse laser during emission, and the frequency of the processing clock corresponds to the frequency of the acquisition speed during packet acquisition. The pulse laser emission clock and the processing clock are configured in the FPGA chip. More preferably, the frequency of the processing clock is greater than the frequency of the pulsed laser emission clock.
The pulse laser firing clock can be configured for replacement but must not be changed during a firing frequency time frame, i.e., a round of testing, using the 4MHz example below. Under the condition that the measuring range is not exceeded, the emitted laser is a short pulse, the emission time is taken as a starting point, and according to the difference of the distances of the reflecting wall surfaces (objects to be measured), the reflected signals can have the reflected short pulse at any position within the 4MHz frequency time range, namely, any position within the 4MHz frequency time range. For N groups of emission signals in the primary emission frequency time of 4MHz, the emission signals correspond to the pulse laser, each group of emission signals are reflected by an object to be detected to obtain a group of reflection signals, the reflection signals correspond to the reflection pulse signals, the reflection pulse signals are converted into electric signals, and then the electric signals are amplified and denoised to obtain a group of amplified signals, wherein each group of amplified signals comprises a real reflection pulse signal and a signal to be sampled, which corresponds to a false reflection pulse signal. Under the conditions that the positions of the reflecting wall surfaces are not changed and the ideal conditions, the FPGA chip can only identify one real reflecting pulse signal in the amplified signals corresponding to one group of reflecting pulse signals, but due to the existence of noise, the FPGA chip can identify multiple false reflecting pulse signals, so that the positions of the real reflecting signal pulses cannot be interpreted. For this purpose, it is necessary to introduce the use of a histogram, keeping the distance of the reflecting wall surface constant, the position of the return of the reflected pulse signal is fixed within the frequency time range of 4MHz, and the noise is completely random therein.
The processing clock is used to sample the N sets of amplified signals in the one-time transmit frequency time range. Preferably, the present invention provides a first acquisition method based on a processing clock, as shown in fig. 2, a weight storage address counter is set at each frequency of the processing clock, and the initial weight of the weight storage address counter is 0; when a processing clock collects signals to be sampled at one frequency, the weight of the corresponding weight storage address counter is increased by 1, so that a group of reflected signal pulses are recorded, and the repeated operation is completed to collect the first group of amplified signals to the N group of amplified signals and obtain a first histogram of each group of amplified signals; the weights of the same weight storage address counter in the first histogram of the first group of amplified signals to the nth group of amplified signals are accumulated to obtain a second histogram, as shown in fig. 3. Because the position of the real reflection pulse signal is fixed, the real reflection pulse signal corresponds to a certain weight, namely N times of weight is added on the second histogram, therefore, the signal to be sampled corresponding to the weight accumulated as N in the second histogram is the real reflection pulse signal, and the noise signal is random, namely the corresponding N times of weight cannot be reached, and the signal to be sampled, which is not corresponding to the weight accumulated as N, is the false reflection pulse signal, namely the noise signal. The one-time cumulative weight of the weight storage address counter can also be set to be n, and the weight of the signal to be sampled in the corresponding second histogram is added asWhen the signal to be sampled is a true reflected pulse signal; the summation of the weights is notIs a spurious reflection pulse signal.
For storage of N weight data, a memory with a spatial depth of N is generally used, and when the N value is too large, the resource of the memory is also huge. Whether the maximum frequency of the processing clock or the memory resources, is limited by the FPGA itself. Therefore, in order to reduce the cost of the FPGA, the related algorithm of the histogram processing needs to be optimized. To reduce the use of memory resources, the storage of the N weight data is optimized.
Since the N sets of reflected signals arrive intermittently within a single transmission frequency time range (e.g., within 4 MHz), they do not arrive at the same time. Preferably, the present invention provides a second acquisition method based on a processing clock, as shown in fig. 4, in which a weight storage address counter is set at each frequency of the processing clock; for the first group of amplified signals, when the processing clock collects the signals to be sampled at one frequency, the corresponding weight storage address counter counts once, judges that the signals to be sampled are continuous and generate data as 1, when the processing clock does not collect the signals to be sampled at one frequency, the corresponding weight storage address counter does not count, judges that the signals to be sampled are discontinuous and generate data as 0, and all the generated data are summarized as data 1 and stored by using a memory. Because the position of the real reflected pulse signal is fixed, and the noise signal is random, the real reflected pulse signal is continuous and stably exists, namely, the weight storage address counter counts once under the same frequency, and the noise signal is counted under different frequencies, namely, the acquisition position of the noise signal is randomly changed. Therefore, for the second set of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts once in the first set of amplified signals and the second set of amplified signals, the signal is judged to be continuous and generates data as 1, otherwise, the signal is judged to be discontinuous and generates data as 0, all the generated data are summarized as data 2, and the data 1 is updated as data 2 and stored by using a memory; for the third group of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts the first group of amplified signals, the second group of amplified signals and the third group of amplified signals once, and judges that the signals are continuous and generate data as 1, otherwise, judges that the signals are discontinuous and generate data as 0, gathers all the generated data as data 3, updates the data 2 as data 3 and uses a memory for storage; similarly, for the nth set of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts the first set of amplified signals to the nth set of amplified signals once, judges that the signals are continuous and generate data as 1, otherwise judges that the signals are discontinuous and generate data as 0, gathers all the generated data as data N, updates the data N-1 generated by the N-1 th set of amplified signals as data N and uses a memory for storage, and obtains a third histogram based on the data N, as shown in fig. 5; the signal to be sampled corresponding to the data 1 in the third histogram is a true reflection pulse signal, the signal to be sampled corresponding to the data not 1 is a false reflection pulse signal, and the false reflection pulse signal is a noise signal. Therefore, all data with depth of N is not required to be stored completely, only a memory far smaller than N is required to be used, only one group of data can be stored in extreme cases, the final data result can reflect the real reflected pulse signal, a large amount of memory resources are not required to be used, and resource expenditure is greatly saved.
Although the histogram can more precisely locate the true reflected pulse signal position, its accuracy is also related to the frequency of the processing clock, which is greater, the resolution of the coarse count is higher, i.e., the shorter the time per count, the lower the amount of carry chain resources required for the fine count. The effect of fine counting is to use the carry chain to count places where the resolution of coarse counting is not reached, so the higher the frequency of the processing clock, the less carry chain resources are required for fine counting. Therefore, increasing the processing clock frequency can greatly save resource overhead. The above method for raising the clock frequency is to cope with the limitation of the FPGA itself, because the FPGA has its own maximum clock setting limitation according to the different chips, and the need to raise the clock frequency again based on the setting limitation requires some equivalent processing, and the above method for spreading the frequency using the phase shift method is equivalent to raising the FPGA capable of setting the maximum clock frequency.
In order to increase the processing clock frequency and increase the coarse count resolution, it is preferable to increase the frequency of the processing clock using a phase offset. First, the maximum processing clocks allowed by the multi-path FPGA, i.e. the initial clocks, are generated, which although at the same frequency, can be set with a phase offset at an angle. The phase shift causes the rising edge and the falling edge of the clocks with the same frequency to be misplaced, namely, the phase shift clock with the same frequency can be obtained through the initial clock, the rising edge and the falling edge can be misplaced due to the phase difference, and the rising edge and the falling edge of the two clocks are used as the processing clock to be used for sampling, namely, the equivalent high-frequency clock is equivalent to the frequency of the lifting processing clock. More preferably, as shown in fig. 4, two sets of clocks with 90 degrees phase shift are used to form a new processing clock: the initial clock and the clock phase-shifted by 90 degrees, i.e., the phase-shifted clock, are used to constitute an equivalent high-frequency clock.
Finally, it should be noted that: the above embodiments are merely preferred embodiments of the present invention for illustrating the technical solution of the present invention, but not limiting the scope of the present invention; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions; that is, even though the main design concept and spirit of the present invention is modified or finished in an insubstantial manner, the technical problem solved by the present invention is still consistent with the present invention, and all the technical problems are included in the protection scope of the present invention; in addition, the technical scheme of the invention is directly or indirectly applied to other related technical fields, and the technical scheme is included in the scope of the invention.
Claims (5)
1. The pulse laser radar device based on the FPGA is characterized by comprising an FPGA chip, wherein a laser transmitter and a laser receiving and transmitting module are arranged in the FPGA chip, the laser receiving and transmitting module is connected with an optical lens and an APD module, the optical lens and the APD module are connected with an optical receiving and transmitting integrated chip, the optical receiving and transmitting integrated chip is connected with the FPGA chip, and the optical receiving and transmitting integrated chip is also connected with a reflection signal optimizing circuit;
The FPGA chip controls the laser transmitter to transmit a plurality of groups of pulse laser according to a preset transmitting frequency, each group of pulse laser is reflected by an object to be tested to form a group of reflected pulse signals, each group of reflected pulse signals comprises a real reflected pulse signal and a false reflected pulse signal, the reflected pulse signals are received by the laser receiving and transmitting module, the optical lens and the APD module and then are converted into electric signals in the optical receiving and transmitting integrated chip, and the reflected signal optimizing circuit amplifies and denoises the electric signals and outputs amplified signals; the FPGA chip performs grouping acquisition on a plurality of groups of amplified signals corresponding to a plurality of groups of pulse lasers according to the emission frequency to form a histogram, obtains a real reflected pulse signal according to the histogram and obtains a rough count of flight time, obtains a fine count on the basis of the rough count in a carry chain of the FPGA chip, and finally obtains the flight time between the laser emission and reflection according to the rough count and the fine count;
configuring a pulse laser emission clock and a processing clock in the FPGA chip, wherein the frequency of the pulse laser emission clock corresponds to the emission frequency of the pulse laser during emission, and the frequency of the processing clock corresponds to the frequency of the acquisition speed during grouping acquisition;
for N groups of amplified signals corresponding to N groups of pulse lasers in a primary emission frequency time range, each group of amplified signals comprises a true reflection pulse signal and a signal to be sampled corresponding to a false reflection pulse signal;
Setting a weight storage address counter at each frequency of the processing clock; for the first group of amplified signals, when the processing clock collects the signals to be sampled at one frequency, the corresponding weight storage address counter counts once, judges that the signals to be sampled are continuous and generate data as1, when the processing clock does not collect the signals to be sampled at one frequency, the corresponding weight storage address counter does not count, judges that the signals to be sampled are discontinuous and generate data as 0, and gathers all the generated data as data 1 and uses a memory for storage; for the second group of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts the first group of amplified signals and the second group of amplified signals once, the first group of amplified signals and the second group of amplified signals are judged to be continuous and generate data as1, otherwise, the second group of amplified signals are judged to be discontinuous and generate data as 0, all the generated data are summarized as data 2, the data 1 is updated as data 2, and the data are stored by using a memory; for the third group of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts the first group of amplified signals, the second group of amplified signals and the third group of amplified signals once, and judges that the signals are continuous and generate data as1, otherwise, judges that the signals are discontinuous and generate data as 0, gathers all the generated data as data 3, updates the data 2 as data 3 and uses a memory for storage; similarly, for the nth set of amplified signals, when the processing clock acquires the signal to be sampled at one frequency, and the corresponding weight storage address counter counts from the first set of amplified signals to the nth set of amplified signals once, judges that the signals are continuous and generate data as1, otherwise judges that the signals are discontinuous and generate data as 0, gathers all the generated data as data N, updates the data N-1 generated by the N-1 th set of amplified signals as data N and uses a memory for storage, and obtains a third histogram based on the data N; the signal to be sampled corresponding to the data 1 in the third histogram is a real reflection pulse signal, the signal to be sampled corresponding to the data not 1 is a false reflection pulse signal, and the false reflection pulse signal is a noise signal;
The frequency of the processing clock is increased using a phase offset.
2. The pulse laser radar device based on the FPGA according to claim 1, further comprising an external communication circuit, wherein the external communication circuit is connected with the FPGA chip, and the flight time in the FPGA chip is transmitted to an external microprocessor or a computer for display or processing through the external communication circuit, and the distance to be measured is obtained through processing.
3. The FPGA-based pulse lidar device of claim 1, wherein the frequency of the processing clock is greater than the frequency of the pulse lasing clock.
4. The FPGA-based pulse lidar device of claim 1, wherein a weight storage address counter is set at each frequency of the processing clock, and an initial weight of the weight storage address counter is 0; when a frequency of the processing clock collects signals to be sampled, adding 1 to the weight of the corresponding weight storage address counter, repeating the operation to complete collection of the first group of amplified signals to the N group of amplified signals and obtain a first histogram of each group of amplified signals; and accumulating the weights of the address counters stored by the same weight in the first histograms of the first group of amplified signals to the N group of amplified signals to obtain a second histogram, wherein the signals to be sampled corresponding to the weights accumulated in the second histogram are true reflection pulse signals, the signals to be sampled not corresponding to the weights accumulated in the second histogram are false reflection pulse signals, and the false reflection pulse signals are noise signals.
5. An FPGA-based pulse lidar device according to claim 1, wherein two sets of clocks with 90 degrees phase offset are used to form the new processing clock.
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| CN202411215480.3A CN118731909B (en) | 2024-09-02 | 2024-09-02 | A pulse laser radar device based on FPGA |
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| CN113325386A (en) * | 2021-04-16 | 2021-08-31 | 上海宏景智驾信息科技有限公司 | Method for real-time statistics of TDC (time-to-digital converter) by using dual random memories of SPAD (space-based radar) laser radar |
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| CN113325386A (en) * | 2021-04-16 | 2021-08-31 | 上海宏景智驾信息科技有限公司 | Method for real-time statistics of TDC (time-to-digital converter) by using dual random memories of SPAD (space-based radar) laser radar |
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