CN118730296A - Multi-pixel photon counter for front-illuminated single-photon imaging and manufacturing method thereof - Google Patents

Abstract

The multi-pixel photon counter for front-illuminated single-photon imaging and its manufacturing method disclosed in the present invention include a substrate and an epitaxial layer and a metal grid layer sequentially arranged thereon, a plurality of first richly doped regions are arranged in an array in the opening area corresponding to the metal grid layer on the epitaxial layer, and a second richly doped region forming a PN junction with the first richly doped region and connected to the metal grid layer is arranged thereon, and a plurality of columnar structures arranged in an array are formed by opening isolation grooves in the substrate corresponding to the plurality of first richly doped region spacing areas, and the bottom ends of the columnar structures are respectively connected to a signal readout circuit through electrodes. In the present invention, the avalanche current pulse is transmitted to the signal readout circuit through the columnar structure of the substrate below the G‑APD unit, thereby realizing single-photon detection and imaging of the front-incident analog MPPC. Since the detector chip surface does not require circuit structure and quenching resistor, it does not occupy area, thus achieving a high fill factor, thereby improving the detection efficiency of the detector.

Description

Multi-pixel photon counter for front-illuminated single-photon imaging and manufacturing method thereof

Technical Field

The present invention belongs to the technical field of semiconductor photoelectric detection chips, and in particular relates to a multi-pixel photon counter for front-illuminated single-photon imaging. The present invention also relates to a method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging.

Background Art

Multi-pixel photon counter (MPPC) is a highly sensitive single-photon response detector. It integrates a large number of Geiger-mode avalanche photodiode (G-APD) units in an array on the same single-crystal silicon wafer to form a solid-state photodetector device. It has been applied in many weak-light detection fields such as high-energy physics, nuclear detection, laser radar, medical imaging, and fluorescence detection. However, the existing front-illuminated analog MPPC cannot realize the single-photon imaging function. Only the back-illuminated analog MPPC combined with the signal readout circuit can realize the single-photon imaging function. The patent (CN115084295A) proposes a light back-illuminated analog silicon photomultiplier (SiPM, another name for MPPC) structure, which overcomes the problem that the filling factor of the light incident surface is affected by the layout of the surface quenching resistor (R _Q ), the top lead electrode and the pixel isolation structure, and in principle can achieve single-photon imaging, but this structure is a deeply buried avalanche pn junction structure, the pn junction depth and the high field region are very deep, when short-wavelength photons are incident, due to the small photon absorption depth, the generated photogenerated electron-hole pairs will recombine or absorb in the heavily doped surface area, unable to reach the high electric field area, and thus unable to respond to short-wavelength photons (such as ultraviolet photons). On the other hand, the trench isolation structure in this MPPC structure is connected to the high electric field area, and a large number of defects in the trench will greatly increase the dark count rate and the probability of after-pulses, reducing the signal-to-noise ratio of the MPPC. Furthermore, the MPPC of this structure needs to make the MPPC body above the silicon substrate (512) of the readout electronics transistor very thin in order to achieve full depletion of the P-type low-doped region, and the process manufacturing is difficult. Patent (CN109727970A) proposes to integrate the sensor (i.e., detector) chip and the signal readout chip together by flip-chip method, so as to realize the electrical connection between the avalanche photodiode and the corresponding quenching resistor of the sensor chip and the signal digital readout circuit of the signal readout chip, so as to read the electrical signal sampled from the quenching resistor through the signal digital readout circuit. This structure also belongs to the photon back-illuminated analog MPPC structure. Although it is beneficial to improve the filling factor (FF), it must adopt a flip-chip method, and the photons must be injected from the back of the detector. The photons must pass through a thicker substrate or fully deplete the substrate or the epitaxial layer, and can enter the high field area of the avalanche photodiode array through the long-distance drift of the photogenerated carriers to achieve photon avalanche detection. This detection mechanism will lead to low efficiency of short-wavelength photon detection. Digital MPPC or single-photon avalanche photodiode array (SPAD array), which is developed in parallel with analog MPPC, can realize front-illuminated single-photon imaging. However, the current digital MPPC makes the signal processing circuit next to each G-APD unit on the upper surface of the chip. The signal processing circuit is non-photosensitive, which limits the geometric fill factor of the detector, thereby affecting the overall photon detection efficiency of the single-photon sensitive imaging detector (reference Architecture-Level Optimization on Digital Silicon Photomultipliers for Medical Imaging, Sensors 2022, 22, 122).

Summary of the invention

The purpose of the present invention is to provide a multi-pixel photon counter for front-illuminated single-photon imaging, which solves the problem that the existing front-illuminated analog MPPC cannot realize single-photon imaging and the single-photon sensitive imaging device has low photon detection efficiency.

Another object of the present invention is to provide a method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging.

The first technical solution adopted by the present invention is: a multi-pixel photon counter for front-illuminated single-photon imaging, including a substrate, an epitaxial layer and a metal grid layer are sequentially arranged on the substrate, a plurality of first richly doped regions are arranged in an array in the opening area of the epitaxial layer corresponding to the metal grid layer, a second richly doped region is commonly arranged above the plurality of first richly doped regions to form a PN junction with the plurality of first richly doped regions and connected to the metal grid layer, a plurality of columnar structures arranged in an array are formed by opening isolation grooves in the corresponding interval areas of the plurality of first richly doped regions in the substrate, the bottom ends of the plurality of columnar structures are respectively connected to the electrode array of the signal readout circuit through electrodes, and there is no need to make a quenching resistor or a signal processing circuit on the front of the detector, thereby improving the filling factor of the imaging detector, and further improving the photon detection efficiency of the imaging detector. The specific structural implementation method may be:

1) A multi-pixel photon counter for short-wavelength light-sensitive front-illuminated single-photon imaging, comprising an N+ type silicon substrate, an N- epitaxial layer and a metal grid layer arranged in sequence on the N+ type silicon substrate, a plurality of N+ regions arranged in an array in an opening area of the N- epitaxial layer corresponding to the metal grid layer, a P++ region forming a PN junction with the plurality of N+ regions and connected to the metal grid layer being arranged above the plurality of N+ regions, a plurality of columnar structures arranged in an array are formed by opening isolation grooves in an area corresponding to the plurality of N+ regions in the N+ type silicon substrate, and the bottom ends of the plurality of columnar structures are connected to an electrode array of a signal readout circuit through electrodes.

2) A multi-pixel photon counter for front-illuminated single-photon imaging that is sensitive to long-wavelength light, comprising a P+ type silicon substrate, a P- epitaxial layer and a metal grid layer arranged in sequence on the P+ type silicon substrate, a plurality of P+ regions arranged in an array in an opening area of the P- epitaxial layer corresponding to the metal grid layer, an N++ region forming a PN junction with the plurality of P+ regions and connected to the metal grid layer being arranged above the plurality of P+ regions, a plurality of columnar structures arranged in an array are formed by opening isolation grooves in an area corresponding to the plurality of P+ regions in the P+ type silicon substrate, and the bottom ends of the plurality of columnar structures are connected to an electrode array of a signal readout circuit through electrodes.

The first technical solution of the present invention is also characterized in that:

The isolation trench is filled with an insulating medium.

The bottom end of the columnar structure is connected to the electrode through the N++ layer/P++ layer, the metal layer and the indium ball in sequence.

The second technical solution adopted by the present invention is:

The method for manufacturing the above-mentioned 1) short-wavelength light-sensitive front-illuminated single-photon imaging multi-pixel photon counter comprises the following steps:

Step 1, prepare an N+ type silicon substrate for epitaxial N- epitaxial layer, and after cleaning, thermally oxidize _SiO2 dielectric layer on both sides of the N+ type silicon substrate;

Step 2, applying photoresist on the front side of the N+ type silicon substrate to pattern the array window, etching the _SiO2 dielectric layer in the array window, injecting phosphorus ions through the array window to form an N+ region, and removing the photoresist;

Step 3, applying photoresist on the front side of the N+ type silicon substrate to photolithograph a large area window pattern, etching away the _SiO2 dielectric layer in the large area window, injecting boron ions through the large area window to form a P++ region, and removing the photoresist and _SiO2 dielectric layer;

Step 4, after implanting phosphorus ions on the back side of the N+ type silicon substrate, a full-area N++ layer is formed;

Step 5, activating phosphorus ions in the N-epitaxial layer and the N+ type silicon substrate through an annealing process;

Step 6: depositing a _SiO2 dielectric layer on the front side of the N+ type silicon substrate;

Step 7, apply photoresist on the front of the N+ type silicon substrate to form a large area window pattern aligned with the P++ area, and etch the SiO ₂ in the pattern cleanly;

Step 8, depositing a metal film on the front side;

Step 9, applying photoresist on the front side of the N+ type silicon substrate to photoetch an array window pattern corresponding to the N+ area, and etching away the metal film not protected by the photoresist to obtain a metal grid layer;

Step 10, depositing a metal layer on the back side of the N+ type silicon substrate;

Step 11, applying photoresist on the back side of the N+ type silicon substrate to photoetch isolation groove patterns between a plurality of columnar structures;

Step 12, first etching the metal layer on the back side of the N+ type silicon substrate that is not protected by the photoresist, and then etching the N+ type silicon substrate that is not protected by the photoresist to the lower surface of the N- epitaxial layer to form an isolation trench;

Step 13, filling the isolation trench with an insulating medium;

Step 14: Connect the metal layer below the columnar structure to the electrode of the signal readout circuit through the indium ball.

The method for manufacturing the above-mentioned 2) multi-pixel photon counter for front-illuminated single-photon imaging that is sensitive to long-wavelength light comprises the following steps:

Step 1, prepare a P+ type silicon substrate for epitaxial P- epitaxial layer, and after cleaning, thermally oxidize _SiO2 dielectric layer on both sides of the P+ type silicon substrate;

Step 2, applying photoresist on the front of the P+ type silicon substrate to pattern the array window, etching the _SiO2 dielectric layer in the array window, injecting phosphorus ions through the array window to form a P+ region, and removing the photoresist;

Step 3, applying photoresist on the front of the P+ type silicon substrate to photolithograph a large area window pattern, etching away the _SiO2 dielectric layer in the large area window, injecting boron ions through the large area window to form an N++ region, and removing the photoresist and _SiO2 dielectric layer;

Step 4, after injecting phosphorus ions into the back side of the P+ type silicon substrate, a full-area P++ layer is formed;

Step 5, activating phosphorus ions in the P-epitaxial layer and the P+ silicon substrate through an annealing process;

Step 6: depositing a _SiO2 dielectric layer on the front side of the P+ type silicon substrate;

Step 7, apply photoresist on the front of the P+ type silicon substrate to form a large area window pattern aligned with the N++ area, and etch the SiO ₂ in the pattern cleanly;

Step 8, depositing a metal film on the front side;

Step 9, applying photoresist on the front side of the P+ type silicon substrate to photoetch an array window pattern corresponding to the P+ area, and etching away the metal film not protected by the photoresist to obtain a metal grid layer;

Step 10, depositing a metal layer on the back side of the P+ type silicon substrate;

Step 11, applying photoresist on the back side of the P+ type silicon substrate to photoetch isolation groove patterns between a plurality of columnar structures;

Step 12, first etching the metal layer on the back side of the P+ type silicon substrate that is not protected by the photoresist, and then etching the P+ type silicon substrate that is not protected by the photoresist to the lower surface of the P- epitaxial layer to form an isolation trench;

Step 13, filling the isolation trench with an insulating medium;

Step 14: Connect the metal layer below the columnar structure to the electrode of the signal readout circuit through the indium ball.

The beneficial effects of the present invention are as follows: in the multi-pixel photon counter for front-illuminated single-photon imaging and the manufacturing method thereof, the avalanche current pulse is transmitted to the signal readout circuit through the columnar structure of the substrate below the G-APD unit, thereby realizing single-photon detection and imaging of the front-incident analog MPPC. Since the detector chip surface does not require a circuit structure and a quenching resistor and does not occupy an area, a high fill factor is achieved, and since the detector can detect front-incident photons, the detection efficiency of the detector is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG2 is a schematic flow chart of a method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG3 is a schematic diagram of the structure obtained in step 2 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG4 is a schematic diagram of the structure obtained in step 3 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG5 is a schematic diagram of the structure obtained in step 4 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG6 is a schematic diagram of the structure obtained in step 6 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG7 is a schematic diagram of the structure obtained in step 7 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG8 is a schematic diagram of the structure obtained in step 8 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG9 is a schematic diagram of the structure obtained in step 9 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG10 is a schematic diagram of the structure obtained in step 10 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG11 is a schematic diagram of the structure obtained in step 11 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG12 is a schematic diagram of the structure obtained in step 12 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG13 is a schematic diagram of the structure obtained in step 13 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention;

FIG. 14 is a schematic diagram of the structure obtained in step 14 of the method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging according to the present invention.

In the figure, 1. photoresist, 2. _SiO2 dielectric layer, 3. N+ region, 4. N- epitaxial layer, 5. N+ type silicon substrate, 6. P++ region, 7. high resistance depletion region, 8. N++ layer, 9. metal grid layer, 10. metal layer, 11. insulating medium, 12. indium ball, 13. electrode, 14. signal readout circuit.

DETAILED DESCRIPTION

The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

Example 1

The present invention provides a multi-pixel photon counter for front-illuminated single-photon imaging, as shown in FIG1 and FIG14, comprising a metal grid layer 9 electrode arranged on the surface of the MPPC, phosphorus ions are injected above the N-epitaxial layer 4 to form a plurality of N+ regions 3, and an array consisting of a plurality of G-APD units is obtained, boron ions are injected over a large area above the N+ region 3 to form a P++ region 6 and together form a PN junction, and the N+ regions 3 are electrically isolated through the high-resistance depletion region 7 spontaneously formed by the P++ region 6 and the N-epitaxial layer 4. The N-epitaxial layer 4 is connected to the N+ silicon substrate 5 below, and there are an N++ layer 8 and a metal layer 10 on the back of the substrate. The back of the substrate is etched into isolated columnar structures by a deep groove etching process, and only one end (i.e., the upper end) of the columnar structure is connected to the N-epitaxial layer 4, and the columnar structure is aligned with the N+ region 3 on the N-epitaxial layer 4. An independent indium ball 12 and a signal input terminal electrode 13 of a signal readout circuit 14 are connected to the metal layer 10 on the lower surface of the columnar structure.

The columnar structure under the G-APD unit and the metal grid electrode on the surface of the MPPC can be etched according to the shape of the G-APD unit, and the shape can be square, circular, hexagonal, etc.

The grooves between the columnar structures may be filled with an insulating medium 11 to increase the mechanical strength and improve the electrical isolation between the columnar structures under each G-APD unit. If the columnar structure has sufficient mechanical strength, the insulating medium 11 may not be filled.

The principle of the present invention is: most of the existing single-photon avalanche photodiode arrays place the signal processing circuit next to each G-APD unit on the upper surface of the chip, which limits the geometric filling factor of the imaging detector, thereby affecting the photon detection efficiency. The present invention carves grooves along the intervals of the G-APD units, from the back of the low-resistivity N+ type silicon substrate 5 to the lower surface of the high-resistance depletion region 7, and can fill the grooves with an insulating medium 11 to achieve electrical isolation of the substrate layer under each unit, thereby preventing the avalanche current signals generated by multiple G-APD units from being mixed and indistinguishable after being converged downward to the substrate. In this way, a reverse bias is applied to all G-APD units in the MPPC through the metal grid layer 9 electrode on the upper surface of the N-epitaxial layer 4, forming a high electric field avalanche region array between the P++ region 6 and the N+ region 3. The neutral region below the N+ region 3 can achieve quenching of the avalanche current of the G-APD unit, thereby forming an avalanche current pulse. The avalanche current pulse is input into the independent multi-channel signal readout circuit 14 or signal readout chip below through the trench-isolated columnar structure and the indium ball 12 for signal processing to achieve single-photon imaging. In the above manner, the present invention does not need to adopt a flip-chip method of injecting photons from the back of the sensor, and can detect photons incident from the front, thereby achieving single-photon detection and imaging of front-incident analog MPPC. And because the detector chip surface does not require circuit structure and quenching resistors, it does not occupy area, so a high fill factor is achieved, further improving the detection efficiency of the detector.

The multi-pixel photon counter for front-illuminated single-photon imaging provided by the present invention can replace all the N-type regions with P-type regions of corresponding concentration, and replace all the P-type regions with N-type regions of corresponding concentration, so as to achieve high-sensitivity detection and imaging of long-wavelength photons (such as near-infrared photons).

Example 2

The present invention provides a method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging, which is suitable for the response and imaging of short-wavelength photons (such as ultraviolet photons and blue-violet photons), as shown in FIG2, comprising the following steps:

Step 1, prepare an N+ type silicon substrate 5 for epitaxially growing an N- epitaxial layer 4, and after cleaning, thermally oxidize a thin and dense _SiO2 dielectric layer 2 on both sides of the N+ type silicon substrate 5;

Step 2, as shown in FIG. 3, a photoresist 1 is applied to the front of the N+ type silicon substrate 5 to pattern the array window, the _SiO2 dielectric layer 2 in the array window is etched away, phosphorus ions are injected through the array window to form an N+ region 3, and the photoresist 1 is removed;

Step 3, as shown in FIG. 4 , a photoresist 1 is applied to the front of the N+ type silicon substrate 5 to form a large area window pattern, the _SiO2 dielectric layer 2 in the large area window is etched away, boron ions are injected through the large area window to form a P++ region 6, and the photoresist 1 and the _SiO2 dielectric layer 2 are removed;

Step 4, as shown in FIG5 , phosphorus ions are implanted on the back side of the N+ type silicon substrate 5 to form a full-area N++ layer 8;

Step 5, activating the phosphorus ions implanted into the N- epitaxial layer 4 and the N+ type silicon substrate 5 by an annealing process;

Step 6, as shown in FIG6 , depositing a SiO ₂ dielectric layer 2 with a thickness of more than 200 nm on the front side of the N+ type silicon substrate 5;

Step 7, as shown in FIG. 7 , a photoresist 1 is applied to the front of the N+ type silicon substrate 5 to form a large area window pattern aligned with the P++ region 6, and SiO ₂ in the pattern is etched cleanly;

Step 8, as shown in FIG8 , depositing a metal film on the front side;

Step 9, as shown in FIG. 9 , a photoresist 1 is applied to the front side of the N+ type silicon substrate 5 to photoetch an array window pattern corresponding to the N+ region 3, and the metal film not protected by the photoresist is etched away to obtain a metal grid layer 9;

Step 10, as shown in FIG10 , depositing a metal layer 10 on the back side of the N+ type silicon substrate 5;

Step 11, as shown in FIG. 11 , a photoresist 1 is applied to the back of the N+ type silicon substrate 5 to photoetch isolation groove patterns between a plurality of columnar structures;

Step 12, as shown in FIG. 12 , first etch the metal layer 10 on the back side of the N+ type silicon substrate 5 that is not protected by the photoresist 1, control the etching time, and then etch the N+ type silicon substrate 5 that is not protected by the photoresist 1 to the lower surface of the N- epitaxial layer 4 to form an isolation trench;

Step 13, as shown in FIG13 , filling the isolation trench with an insulating medium 11;

Step 14, as shown in FIG. 14 , the metal layer 10 below the columnar structure is connected to the electrode 13 of the signal readout circuit 14 through the indium ball 12 .

Example 3

The present invention provides a method for manufacturing a multi-pixel photon counter for front-illuminated single-photon imaging, which is suitable for high-sensitivity detection and imaging of long-wavelength photons (such as near-infrared photons), comprising the following steps:

Step 1, prepare a P+ type silicon substrate for epitaxial P- epitaxial layer, and after cleaning, thermally oxidize a thin and dense _SiO2 dielectric layer on both sides of the P+ type silicon substrate;

Step 2, applying photoresist on the front of the P+ type silicon substrate to pattern the array window, etching the _SiO2 dielectric layer in the array window, injecting phosphorus ions through the array window to form a P+ region, and removing the photoresist;

Step 3, applying photoresist on the front of the P+ type silicon substrate to photolithograph a large area window pattern, etching away the _SiO2 dielectric layer in the large area window, injecting boron ions through the large area window to form an N++ region, and removing the photoresist and _SiO2 dielectric layer;

Step 4, after injecting phosphorus ions on the back side of the P+ type silicon substrate, a full-area P++ layer is formed;

Step 5, activating the phosphorus ions implanted into the P-epitaxial layer and the P+ silicon substrate by an annealing process;

Step 6: depositing a _SiO2 dielectric layer with a thickness of more than 200 nm on the front side of the P+ type silicon substrate;

Step 7, apply photoresist on the front of the P+ type silicon substrate to form a large area window pattern aligned with the N++ area, and etch the SiO ₂ in the pattern cleanly;

Step 8, depositing a metal film on the front side;

Step 9, applying photoresist on the front side of the P+ type silicon substrate to photoetch an array window pattern corresponding to the P+ area, and etching away the metal film not protected by the photoresist to obtain a metal grid layer;

Step 10, depositing a metal layer on the back side of the P+ type silicon substrate;

Step 11, applying photoresist on the back side of the P+ type silicon substrate to photoetch isolation groove patterns between a plurality of columnar structures;

Step 12, first etching the metal layer on the back of the P+ type silicon substrate that is not protected by the photoresist, controlling the etching time, and then etching the P+ type silicon substrate that is not protected by the photoresist to the lower surface of the P- epitaxial layer to form an isolation trench;

Step 13, filling the isolation trench with an insulating medium;

Step 14: Connect the metal layer below the columnar structure to the electrode of the signal readout circuit through the indium ball.

Claims (8)

1. The front irradiation type single photon imaging multi-pixel photon counter is characterized by comprising a substrate, wherein an epitaxial layer and a metal grid layer are sequentially arranged above the substrate, a plurality of first doped-rich regions are arranged on the epitaxial layer corresponding to an opening area array of the metal grid layer, a second doped-rich region which forms a PN junction with the first doped-rich region and is connected to the metal grid layer is jointly arranged above the first doped-rich regions, a plurality of columnar structures which are arranged in an array are formed in the substrate corresponding to a plurality of first doped-rich region interval regions by arranging isolation grooves, and the bottom ends of the columnar structures are respectively and jointly connected with a signal reading circuit through electrodes.

2. The front-illuminated single-photon imaging multi-pixel photon counter of claim 1 wherein the isolation trenches are filled with an insulating medium.

3. The front-illuminated single-photon imaging multi-pixel photon counter according to claim 1, comprising an n+ type silicon substrate (5), wherein an N-epitaxial layer (4) and a metal grid layer (9) are sequentially arranged above the n+ type silicon substrate (5), a plurality of n+ regions (3) are arranged on the N-epitaxial layer (4) corresponding to an opening region array of the metal grid layer (9), p++ regions (6) forming PN junctions with the n+ regions and connected to the metal grid layer (9) are commonly arranged above the n+ regions (3), a plurality of columnar structures arranged in an array are formed in the n+ type silicon substrate (5) corresponding to a plurality of n+ region (3) interval regions by opening isolation grooves, and the bottom ends of the plurality of columnar structures are commonly connected with a signal readout circuit (14) through electrodes (13) respectively.

4. A front-illuminated single-photon imaging multipixel photon counter as in claim 3 wherein the bottom end of the columnar structure is connected to an electrode (13) sequentially through an n++ layer (8), a metal layer (10) and indium spheres (12).

5. A method of fabricating a front-illuminated single photon imaging multi-pixel photon counter as in claim 3 comprising the steps of:

step 1, preparing an N+ type silicon substrate (5) of an epitaxial N-epitaxial layer (4), and thermally oxidizing SiO ₂ dielectric layers (2) on the front side and the back side of the N+ type silicon substrate (5) after cleaning;

Step 2, coating photoresist (1) on the front surface of an N+ type silicon substrate (5), photoetching an array window pattern, etching a SiO ₂ dielectric layer (2) in the array window, injecting phosphorus ions through the array window to form an N+ region (3), and removing the photoresist (1);

Step3, coating photoresist (1) on the front surface of the N+ type silicon substrate (5), photoetching a large-area window graph, etching a SiO ₂ dielectric layer (2) in the large-area window, injecting boron ions through the large-area window to form a P++ region (6), and removing the photoresist (1) and the SiO ₂ dielectric layer (2);

step 4, injecting phosphorus ions into the back surface of the N+ type silicon substrate (5) to form an N++ layer (8) with the whole area;

step 5, activating phosphorus ions in the N-epitaxial layer (4) and the N+ type silicon substrate (5) through an annealing process;

step 6, depositing a SiO ₂ dielectric layer (2) on the front surface of the N+ type silicon substrate (5);

Step 7, coating photoresist (1) on the front surface of the N+ type silicon substrate (5), photoetching a large-area window pattern aligned with the P++ region (6), and etching SiO ₂ in the pattern;

Step 8, depositing a metal film on the front surface;

Step 9, coating photoresist (1) on the front surface of the N+ type silicon substrate (5), photoetching an array window pattern corresponding to the N+ region (3), and etching a metal film which is not protected by the photoresist to obtain a metal grid layer (9);

step 10, depositing a metal layer (10) on the back surface of the N+ type silicon substrate (5);

Step 11, coating photoresist (1) on the back of the N+ type silicon substrate (5) to photoetching isolation groove patterns among a plurality of columnar structures;

Step 12, firstly etching a metal layer (10) which is not protected by the photoresist (1) on the back surface of the N+ type silicon substrate (5), and then etching the N+ type silicon substrate (5) which is not protected by the photoresist (1) to the lower surface of the N-epitaxial layer (4) to form an isolation groove;

step 13, filling an insulating medium (11) in the isolation trench;

And 14, connecting the metal layer (10) below the columnar structure with an electrode (13) of a signal reading circuit (14) through an indium ball (12).

6. The front-illuminated single-photon imaging multi-pixel photon counter according to claim 1, comprising a p+ type silicon substrate, wherein a P-epitaxial layer and a metal grid layer are sequentially arranged above the p+ type silicon substrate, a plurality of p+ regions are arranged on the P-epitaxial layer corresponding to an opening region array of the metal grid layer, N++ regions which form PN junctions with the p+ regions and are connected to the metal grid layer are commonly arranged above the p+ regions, a plurality of columnar structures which are arranged in an array manner are formed in the p+ type silicon substrate corresponding to the p+ regions by arranging isolation grooves, and the bottom ends of the columnar structures are commonly connected with a signal readout circuit through electrodes respectively.

7. The front side illuminated single photon imaging multipixel photon counter of claim 6 wherein the bottom end of the columnar structure is connected to an electrode through a p++ layer, a metal layer and an indium ball in sequence.

8. The method of fabricating a front-illuminated single-photon imaging multi-pixel photon counter as in claim 6 comprising the steps of:

Step 1, preparing a P+ type silicon substrate of an epitaxial P-epitaxial layer, and thermally oxidizing SiO ₂ dielectric layers on the front side and the back side of the P+ type silicon substrate after cleaning;

Step 2, coating photoresist photoetching array window patterns on the front surface of the P+ type silicon substrate, etching a SiO ₂ dielectric layer in the array window, injecting phosphorus ions through the array window to form a P+ region, and removing photoresist;

Step 3, coating photoresist on the front surface of the P+ type silicon substrate to photoetching a large-area window pattern, etching a SiO ₂ dielectric layer in the large-area window, injecting boron ions through the large-area window to form an N++ region, and removing the photoresist and the SiO ₂ dielectric layer;

step 4, injecting phosphorus ions into the back surface of the P+ type silicon substrate to form a P++ layer with a full area;

step 5, activating phosphorus ions in the P-epitaxial layer and the P+ type silicon substrate through an annealing process;

Step 6, depositing a SiO ₂ dielectric layer on the front surface of the P+ type silicon substrate;

Step 7, coating a large-area window pattern aligned with the N++ region by photoresist photoetching on the front surface of the P+ type silicon substrate, and etching SiO ₂ in the pattern;

Step 8, depositing a metal film on the front surface;

step 9, coating photoresist on the front surface of the P+ type silicon substrate to photoetch an array window pattern corresponding to the P+ region, and etching away a metal film which is not protected by the photoresist to obtain a metal grid layer;

Step 10, depositing a metal layer on the back surface of the P+ type silicon substrate;

step 11, coating photoresist on the back of the P+ type silicon substrate to photoetch isolation groove patterns among a plurality of columnar structures;

Step 12, etching the metal layer which is not protected by the photoresist on the back surface of the P+ type silicon substrate, and then etching the P+ type silicon substrate which is not protected by the photoresist to the lower surface of the P-epitaxial layer to form an isolation groove;

step 13, filling an insulating medium in the isolation trench;

and 14, connecting the metal layer below the columnar structure with an electrode of the signal reading circuit through an indium ball.