CN118714058B

CN118714058B - Bus controller module verification method, system, program product, device and medium

Info

Publication number: CN118714058B
Application number: CN202411195678.XA
Authority: CN
Inventors: 史宏利
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2024-08-29
Filing date: 2024-08-29
Publication date: 2025-01-10
Anticipated expiration: 2044-08-29
Also published as: CN118714058A

Abstract

The present invention discloses a bus controller module verification method, system, program product, device and medium, relates to the field of embedded industrial control technology, and is used to realize the verification of module-level CAN bus controller. In view of the problems of traditional scheme verification and high learning cost, a bus controller module verification method is provided, which can directly capture bus signal values from CAN bus based on CAN protocol and organize them into complete data frames. Based on this, the transmission frame information sent by the sending node, the bus frame information captured from the CAN bus during the data frame transmission process, and the receiving frame information obtained from the receiving node can be determined by pre-configured parameters, and a three-party full match can be achieved, and the verification of two bus controller modules can be realized at the same time, and the verification accuracy is higher than that of the two-party verification. In addition, in this method, there is no need to use the VIP of the CAN bus controller, which greatly reduces the verification and learning costs.

Description

Bus controller module verification method, system, program product, device and medium

Technical Field

The present invention relates to the field of embedded industrial control, and in particular, to a method, a system, a program product, a device, and a medium for verifying a bus controller module.

Background

The controller area network (Controller Area Network, CAN) bus is a serial data communication bus, is widely applied to the field of embedded industrial control, and provides a stable high-speed data exchange channel for data exchange between terminal controllers, sensors and other Internet of things equipment. Considering the high commercial value of the CAN bus and the consideration of the scene application of Chip manufacturers based on industrial control edge computing, the integration of a CAN bus controller module in a commercial System on Chip (SoC) has become a mainstream choice.

The traditional CAN bus controller module verification scheme uses a pre-configured CAN bus controller VIP (Verfication IP, verification IP; IP is Intellectual Property, intellectual property) as a verification reference model. The verification platform realizes a CAN communication network at least comprising two nodes of a CAN bus controller module and a CAN bus controller VIP. The verification platform sends test excitation to the CAN bus controller module, the CAN bus controller module node is controlled to broadcast frames to the CAN communication network, the CAN bus controller VIP node listens and normally receives the broadcast frames in the CAN communication network, and relevant information of the frames is analyzed. The verification platform compares the configuration information in the test excitation with the frame related information analyzed in the verification reference model, so that the whole verification process is completed.

Based on the above-mentioned traditional method to the verification of CAN bus controller module, need to use dedicated CAN bus controller VIP, cause actual verification cost too high, and need to confirm configuration and the use flow of VIP that different manufacturers provided, make the verification personnel learn with high costs, the chip development cycle is overlength.

Therefore, a method for verifying a bus controller module is needed by those skilled in the art, so as to solve the problems of high verification cost, high learning cost, overlong chip development period and the like existing in the conventional scheme that the conventional scheme depends on the implementation of the CAN bus controller VIP.

Disclosure of Invention

The invention aims to provide a bus controller module verification method, a system, a program product, a device and a medium, which are used for solving the problems of high verification cost, high learning cost, overlong chip development period and the like existing in the traditional scheme that the traditional scheme depends on a CAN bus controller VIP to realize.

In order to solve the technical problems, the invention provides a bus controller module verification method which is applied to a bus verification platform, wherein the bus verification platform is connected with two bus controller modules to be tested, and the two bus controller modules to be tested are connected through a controller local area network bus;

The method comprises the following steps:

generating a pre-configuration parameter through random constraint, wherein the pre-configuration parameter comprises a baud rate, a bit time sequence parameter and transmission frame information;

Writing the pre-configuration parameters into the sending node, and enabling the sending node to start frame transmission so that the sending node sends a data frame to the receiving node through the controller area network bus according to the pre-configuration parameters;

Synchronously grabbing bus signal values from the controller area network bus according to the baud rate and the bit time sequence parameters;

determining bus frame information according to the bus signal value;

after the data frame is sent, reading the received frame information from the receiving node;

and carrying out full matching on the sending frame information, the bus frame information and the receiving frame information, and determining a verification result according to the full matching result.

In one possible embodiment, synchronizing the grabbing of bus signal values from the controller area network bus according to the baud rate and bit timing parameters includes:

Determining sampling pulses according to the baud rate and the bit timing parameters;

Performing bit timing synchronization between the sampling pulse and a transmission bus signal in the controller area network bus;

And sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after the bit time sequence synchronization.

In one possible embodiment, the bit timing parameters include a sync segment parameter, a propagation time period parameter, a first phase buffer segment parameter, and a second phase buffer segment parameter;

Determining sampling pulses from the baud rate and the bit timing parameters comprises:

Determining a prescaled coefficient according to the baud rate and the bit time sequence parameter, wherein the prescaled coefficient is the number of times of clock cycle counting under a clock domain determined by the baud rate and the bit time sequence parameter, and the time length corresponding to the minimum time unit is required to be counted;

Taking the prescaled coefficient as a cycle count value of a pre-established bit timing counting unit, and pushing the count of the bit timing counting unit by using a bus clock signal determined by the baud rate and the bit timing parameter;

Each time the bit time sequence counting unit completes one cycle, sending out a time sequence counting plus one signal to obtain a counting pulse;

pushing the count of a preset minimum unit counting unit by the counting pulse;

Setting the bus sampling signal when the count value of the minimum unit counting unit reaches the sum of the synchronous section parameter, the propagation time section parameter and the first phase buffer section parameter so as to obtain the sampling pulse;

When the count value of the minimum unit count unit reaches the sum of the synchronous segment parameter, the propagation time segment parameter, the first phase buffer segment parameter and the second phase buffer segment parameter, the count value of the minimum unit count unit is cleared.

In one possible embodiment, performing bit timing synchronization between the count pulse and a transmit bus signal in the controller area network bus comprises:

Assigning the bus signal value to the 0 th bit of a predefined first merging array in the bit time sequence counting unit body, wherein the width of the first merging array is 2;

Shifting the first merge array logic left by 1 bit by a shift operator;

assigning the bus signal value to the 0 th bit of the first merging array when the rising edge of the bus clock signal is pushed;

Comparing the 1 st bit value of the first merging array with the 0 th bit inverse value of the first merging array to judge whether the bus waveform in the controller area network bus has a falling edge or not;

if a falling edge occurs, setting a bus falling edge mark signal;

When the bus falling edge flag signal is set, the count value of the minimum unit counting unit is cleared, and then the bus falling edge flag signal is cleared.

In one possible embodiment, sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after the bit timing synchronization includes:

sampling a bus signal value transmitted in the controller area network bus every time the bus sampling signal is set;

Stopping sampling of the bus signal value when the interrupt signal setting of the receiving node is monitored;

And setting the interrupt signal by the receiving node after the data frame is transmitted.

In one possible embodiment, determining bus frame information from the bus signal value comprises:

Performing bit filling processing on the sampled bus signal value according to a bit filling mechanism in a controller area network bus protocol to obtain a bit filling fixed format frame information queue, wherein the format of the bit filling fixed format frame information queue accords with a data frame format specified by the controller area network bus protocol;

Extracting data on specified data bits in the deblock filling fixed format frame information queue according to a data frame format specified by the controller area network bus protocol to determine the bus frame information;

The bus frame information comprises special identification bit information, frame data length, frame data information, a cyclic redundancy check value sequence and a response field slot bit value.

In one possible embodiment, the performing, according to a bit filling mechanism in a controller area network bus protocol, bit-removing filling processing on the sampled bus signal value to obtain a fixed format frame information queue after bit-removing filling includes:

When the bus signal value is obtained through sampling, assigning the bus signal value to the 0 th bit of a predefined second merging array, wherein the width of the second merging array is 12;

judging whether the values of the 1 st bit to the 5 th bit of the second merging array are the same or not;

If the values are the same, judging whether the values of the 1 st bit to the 11 th bit of the second merging array are all 1;

if the bus signal value obtained by the sampling is all '1', judging whether the bus signal value obtained by the sampling is '0';

If the value is '0', filling the bus signal value into the 0 th bit in the fixed format frame information queue, setting a start acquisition frame signal, reassigning the value of the 1 st bit and the 5 th bit of the second merging array to be '11101', and shifting the logic of the second merging array by 1 bit leftwards through a shifting operator;

If not, shifting the second merged array logic left by 1 bit through a shift operator;

if the initial acquisition frame signals are different, judging whether the initial acquisition frame signals are set or not;

If the initial acquisition frame signal is set, filling the bus signal value obtained by sampling this time into the fixed format frame information queue, and shifting the second merging array logic left by 1 bit through a shifting operator;

if the initial acquisition frame signal is not set, the second merge array logic is shifted left by 1 bit by a shift operator.

In one possible embodiment, the special identification bit information includes an extended identifier bit value, a remote send request bit value, a substitute remote request bit value, and a reserved bit value;

Extracting data on specified data bits in the deblock fill fixed format frame information queue according to a data frame format specified by the controller area network bus protocol to determine the bus frame information includes:

determining the format of the data frame to be transmitted this time as a standard format frame or an extended format frame according to the extended identifier bit value on the appointed data bit in the bit-removal filling fixed format frame information queue;

based on the data frame format of the current transmission, other special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot position value are extracted.

In one possible embodiment, the bus frame information further comprises a cyclic redundancy check value reference sequence;

After determining that the format of the current transmission data frame is a standard format frame or an extended format frame, the method further includes:

Based on the data frame format of the transmission, intercepting frame data from a frame start bit to the front of the cyclic redundancy check value sequence as a part of frame information queue to be checked;

Processing the part of frame information queue to be checked through a cyclic redundancy check unit to obtain the cyclic redundancy check value reference sequence;

The cyclic redundancy check unit adopts a cyclic redundancy check algorithm which is defined by the controller area network bus protocol.

In one possible embodiment, performing full matching on the transmission frame information, the bus frame information, and the reception frame information, and determining the verification result according to the full matching result includes:

Judging whether the transmission data frame is normally received by the receiving node according to the response field slot position value in the bus frame information, if so, carrying out subsequent verification, if not, returning verification failure information and exiting the method;

Performing full matching on the bus frame information, the sending frame information and the first special identification bit information in the receiving frame information, and outputting a first matching result;

checking whether second special identification bit information in the bus frame information accords with the controller local area network bus protocol or not, and outputting a checking result, wherein the first special identification bit information and the second special identification bit information are collected as the special identification bit information, and the second special identification bit information comprises a substitute remote request bit value and a reserved bit value;

Performing full matching on the bus frame information, the frame data length in the sending frame information and the receiving frame information and the frame data information, and outputting a second matching result;

Matching the cyclic redundancy check value sequence in the bus frame information with the cyclic redundancy check value reference sequence, and outputting a third matching result;

And determining the verification result according to the first matching result, the checking result, the second matching result and the third matching result.

In one possible embodiment, after determining the verification result according to the first matching result, the second matching result, the inspection result, and the third matching result, the method further includes:

If any result of the first matching result, the checking result, the second matching result and the third matching result is not passed, determining an abnormal position item according to a non-passed result item, wherein the abnormal position item represents a possible position of an abnormality which causes the verification failure at the time;

And returning verification failure information comprising the failed result item and the abnormal position item.

In order to solve the technical problems, the invention also provides a bus controller module verification system, which comprises a bus verification platform and two bus controller modules to be tested;

the bus verification platform is connected with two bus controller modules to be tested, and the two bus controller modules to be tested are connected through a controller local area network bus, wherein one bus controller module to be tested is used as a transmitting node, and the other bus controller module to be tested is used as a receiving node;

the bus verification platform comprises a bus controller reference model, a driver and a receiver;

The bus controller reference model is connected with the register of the sending node through the driver, the bus controller reference model is connected with the register of the receiving node through the receiver, and the bus controller reference model is used for realizing the steps of the bus controller module verification method.

To solve the above technical problem, the present invention also provides a computer program product, including a computer program/instruction, which when executed by a processor, implements the steps of the bus controller module verification method as described above.

In order to solve the technical problem, the present invention further provides a bus controller module verification device, including:

a memory for storing a computer program;

And a processor for implementing the steps of the bus controller module verification method as described above when executing the computer program.

To solve the above technical problem, the present invention further provides a nonvolatile storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the bus controller module verification method as described above.

The invention provides a bus controller module verification method, which is characterized in that a group of pre-configuration parameters are generated in advance in a random constraint mode, wherein the pre-configuration parameters comprise all parameter data required by completing one-time data frame transmission process in a CAN bus. And then, writing the pre-configuration parameters into a bus control module to be tested as a transmitting node so as to drive the transmitting node to complete one-time data frame transmission according to the pre-configuration parameters, and transmitting the data frame to a receiving node through a CAN bus. In the data frame transmission process, because the pre-configuration parameters are generated by the bus verification platform and are known to the bus verification platform, the bus verification platform CAN directly grasp bus signal values from the CAN bus based on the CAN protocol and sort the bus signal values into complete data frames transmitted in the CAN bus based on the CAN bus protocol and the pre-configuration parameters. And, after the data frame transmission is completed, the data frame information acquired by the receiving node is also acquired from the receiving node as the receiving frame information. Based on the method, the pre-configuration parameters CAN determine the sending frame information sent by the sending node, the bus frame information grabbed from the CAN bus in the data frame transmission process and the receiving frame information acquired from the receiving node, so that three-party full matching CAN be realized, meanwhile, the verification of two bus controller modules is realized, and the verification accuracy is higher compared with the verification of two parties.

In addition, in the verification method, the information required to be matched and verified subsequently CAN be directly captured from the CAN bus, and the VIP of the CAN bus controller is not required, so that the verification and learning cost is greatly reduced. In addition, in the method, the verification of two CAN bus controller modules CAN be realized by one data frame transmission, compared with the verification of one CAN bus controller module realized by two CAN bus controller VIP nodes in the traditional scheme, the verification efficiency is higher, and the development period of a chip is further shortened.

The bus controller module verification system, the program product, the device and the nonvolatile storage medium provided by the invention correspond to the method and have the same effect.

Drawings

For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a block diagram of a bus controller module verification system provided by the present invention;

FIG. 2 is a flowchart of a method for verifying a bus controller module according to the present invention;

FIG. 3 is a schematic diagram of a data frame format under the CAN bus protocol;

FIG. 4 is a flowchart of another method for verifying a bus controller module according to the present invention;

FIG. 5 is a block diagram of another bus controller module verification system provided by the present invention;

fig. 6 is a block diagram of a bus controller module verification device according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.

The core of the invention is to provide a bus controller module verification method, a system, a program product, a device and a medium.

In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.

In the related art, if the module level verification of the controller area network (Controller Area Network, CAN) bus controller is to be realized, a verification environment composed of two VIP (Verfication IP, verification IP, intellectual Property, intellectual property) nodes of the CAN bus controller and one module node of the CAN bus controller to be tested is constructed based on a universal verification methodology (Universal Verification Methodology, UVM), then one VIP node of the CAN bus controller and the module node of the CAN bus controller to be tested send frames simultaneously through a preset test sequence, and the other VIP node of the CAN bus controller receives broadcast frames on the bus sequentially, so that frame information is analyzed in a verification platform and compared with the preset test sequence information, and the whole verification process is completed.

That is, in the above scheme, the VIP to be used for two CAN bus controllers is needed to be used for implementing verification of one CAN bus controller module to be tested, and is used as a node of a CAN communication network in a verification environment, and the VIP node is used for implementing receiving frames and analyzing information so as to determine whether the function of the CAN bus controller to be tested is normal. On one hand, the use of the special CAN bus controller VIP in the scheme CAN cause the high practical verification cost, and the configuration and the use flow of the VIP provided by different manufacturers are required to be clarified, so that the verification personnel has high learning cost and the chip development period is overlong. On the other hand, in order to realize the verification of the CAN bus controller module to be tested, two verification sub-environments are respectively constructed for the two CAN bus controllers VIP, and the two verification sub-environments are used for independently configuring the VIP nodes of the CAN bus controllers, so that the verification difficulty is increased, and the verification efficiency is reduced.

Therefore, in view of the above-mentioned problems, the present invention provides a bus controller module verification method, which is applied to the bus verification platform shown in fig. 1. The bus verification platform is connected with two bus controller modules to be tested, the two bus controller modules to be tested are connected through a controller local area network bus, one bus controller module to be tested is used as a transmitting node, and the other bus controller module to be tested is used as a receiving node.

Further, as shown in fig. 2, the method includes:

S10, generating a pre-configuration parameter through random constraint.

The pre-configured parameters include, but are not limited to, baud rate, bit timing parameters, and transmit frame information.

And S20, writing the preconfigured parameters into the sending node, and enabling the sending node to start frame transmission so that the sending node sends the data frame to the receiving node through the controller local area network bus according to the preconfigured parameters.

S30, synchronously grabbing bus signal values from the controller area network bus according to the baud rate and the bit time sequence parameters.

And S40, determining bus frame information according to the bus signal value.

And S50, after the data frame is sent, reading the received frame information from the receiving node.

And S60, carrying out full matching on the sending frame information, the bus frame information and the receiving frame information, and determining a verification result according to the full matching result.

In step S10, the pre-configuration parameters are generated by random constraint, that is, the parameter configuration of the data frame transmitted between the two bus controller modules to be tested in the present verification is generated. Specifically, the baud rate included in the preconfigured parameters represents the number of bits (bits) sent or received by the CAN bus controller module within 1 second in the transmission process of the data frame. The bit timing parameters included in the preconfigured parameters are corresponding parameters of the CAN bus protocol for dividing each transmission bit into 4 timing segments on a time scale, namely, the bit timing parameters include parameters of the 4 timing segments, i.e., a Synchronization Segment (SS), a Propagation Time Segment (PTS), a phase buffer segment 1 (PBS 1), and a phase buffer segment 2 (PBS 2).

Based on the baud rate and the bit timing parameters, the following formula can be obtained:

;

Wherein CAN_ Baud is the baud rate, SS, PTS, PBS and PBS2 are the corresponding parameters of a Synchronous Segment (SS), a Propagation Time Segment (PTS), a phase buffer segment 1 (PBS 1) and a phase buffer segment 2 (PBS 2), respectively, and Tq is the minimum time unit.

In the above equation, (ss+pts+pbs1+pbs2) ×tq is the time required for the CAN bus to transmit one bit under the current preconfigured parameters. In addition, assuming that the clock frequency of the clock domain of the CAN bus is f _{CAN_clk} (generally 24 MHz), in order to implement bit timing transmission at the specified baud rate, the CAN bus controller may obtain the Tq time by dividing the clock frequency by the following formula:

;

Wherein BRP is a prescaler coefficient, and CAN be used to divide the clock of the CAN bus to obtain a clock signal meeting the Tq time requirement, and T _{CAN_clk} is the clock period of the CAN bus.

As CAN be seen from the above formula, the clock domain for transmitting the data frame in the CAN bus in the verification process CAN be determined by pre-configuring the baud rate and the bit time sequence parameter in the parameters. In addition, for the transmission frame information, that is, the specific frame information of the data frame transmitted in the CAN bus in the present verification process, the specific frame information may be freely set according to the actual verification requirement, which is not limited in this embodiment.

Based on the above, step S20 is to drive the transmitting node to transmit a specific data frame for subsequent comparison verification for the determined preconfigured parameters. In the case that the parameters are known, how to drive the CAN bus controller module to transmit a specific data frame is well known to those skilled in the art, and the description of this embodiment is omitted.

For step S30, also as described above, in the case where the parameters of the data frame are known and the clock domain of the CAN bus is known, the bus signal value being transmitted CAN be directly grasped from the CAN bus based on the CAN bus protocol to achieve acquisition of the data frame transmitted in the CAN bus. In order to distinguish different acquisition modes of the data frames, the data frames acquired from the CAN bus are called bus frames, the data frames transmitted by the transmitting node are called transmitting frames, and the receiving frames received by the receiving node are called receiving frames. In practice, however, the bus frame, the transmit frame, and the receive frame all refer to the same data frame during one authentication process.

Specifically, the present example also provides a possible implementation of step S30, including:

S31, determining sampling pulses according to the baud rate and the bit time sequence parameters;

S32, synchronizing bit time sequences between sampling pulses and transmission bus signals in a controller area network bus;

S33, sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after the bit time sequence synchronization.

As for step S31, it is apparent from the above that the duration of transmitting one bit in the CAN bus CAN be determined according to the baud rate and the bit timing parameter. Based on the above, a corresponding sampling frequency CAN be obtained to capture each bit of data of the data frame transmitted on the CAN bus, and a corresponding sampling pulse CAN be obtained.

The present embodiment also provides a specific embodiment of the sampling pulse, where the step S31 specifically further includes:

S311, determining a prescaler coefficient according to the baud rate and the bit sequence parameter.

The time length corresponding to the prescaled coefficient being the minimum time unit needs to be counted by clock cycles in a clock domain determined by the baud rate and the bit timing parameter, that is, BRP mentioned in the above embodiment formula.

S312, taking the prescaled coefficient as a cycle count value of a pre-established bit timing counting unit, and pushing the count of the bit timing counting unit by using a bus clock signal determined by the baud rate and the bit timing parameters.

S313, each time the bit time sequence counting unit completes one cycle, a time sequence counting plus one signal is sent out to obtain a counting pulse.

S314 the count of the minimum unit count unit established in advance is pushed by the count pulse.

S315, setting a bus sampling signal to obtain a sampling pulse when the count value of the minimum unit counting unit reaches the sum of the synchronous segment parameter, the propagation time segment parameter and the first phase buffer segment parameter.

S316, when the count value of the minimum unit count unit reaches the sum of the synchronous segment parameter, the propagation time segment parameter, the first phase buffer segment parameter and the second phase buffer segment parameter, the count value of the minimum unit count unit is cleared.

For step S311, the determination of the prescaled coefficient may be implemented according to the formula in the above embodiment, which is not described in detail in this embodiment.

As to step S312, it is known from the above embodiment that the prescaled coefficient indicates the number of counts of clock cycles required in the CAN clock domain for a minimum time unit Tq duration. That is, if counting is performed by a counter under the CAN clock domain, each time the counter counts BRP, it indicates that the duration of a minimum time unit Tq has elapsed. Therefore, step S312 passes through a counting loop body pushed by the bus clock signal determined by the baud rate and the bit timing parameter, and the loop value is set to the prescale coefficient BRP, and each time the counting loop body completes a loop, the simulation time of a minimum time unit Tq is marked. Corresponding to step S313, i.e. after each cycle of the bit sequence counting unit is completed, a sequence plus a signal is sent to indicate the simulation time of passing a minimum time unit Tq, so as to obtain counting pulses for counting the number of the current minimum time units.

For step S314, the count of the minimum time unit is also realized by one count cycle body. In order to distinguish the counting loop body in the step S312, the counting loop body in the step is called a minimum unit counting unit, and the counting loop body in the step S312 is called a bit timing counting unit.

As to step S315, it CAN be seen from the above embodiment that in the CAN bus protocol, each transmission bit is further divided into 4 timing segments on a time scale. In addition, when sampling the data bit is performed, sampling is generally performed at the end of the 3rd time period (i.e., the first phase buffer PBS 1) and at the beginning of the 4 th time period (i.e., the second phase buffer PBS 2). Therefore, in step S315, based on SS, PTS, PBS of the bit timing parameters, when the count value of the minimum time counting unit reaches the sum of the first 3 timing periods, sampling can be performed, which is implemented by the set bus sampling signal, so as to obtain the sampling pulse generated by the set bus sampling signal.

For step S316, it can be seen from the above description that the one-bit transmission bit includes 4 time periods, and when the count value of the minimum time unit reaches the sum of the 4 time periods, the end of the transmission bit is indicated, and the next transmission bit needs to be sampled. Step S316 clears the count value of the minimum time counting unit and clears the set bus sampling signal to prepare for the sampling of the next bit transmission bit.

In addition, for step S32, since the transmitting unit does not start data frame transmission at the instant when the pre-configuration parameter writing or verification simulation starts, in order to achieve more accurate bus signal value capture, it is also necessary to perform bit timing synchronization on the sampling pulse to synchronize the timing of the sampling pulse and the CAN bus. The bit timing synchronization CAN be implemented according to the bit timing synchronization function specified in the CAN bus protocol, and the description of this embodiment is omitted. However, this embodiment provides a possible bit timing synchronization scheme, and the step S32 specifically further includes:

S321, in the bit time sequence counting unit body, the bus signal value is assigned to the 0 th bit of the first predefined merging array.

Wherein the width of the first merge array is 2.

S322, shifting the first merged array logic left by 1 bit through a shift operator.

S323, assigning the bus signal value to the 0 th bit of the first merging array after the rising edge of the bus clock signal is pushed.

S324, comparing the 1 st bit value of the first merging array with the 0 th bit inverse value of the first merging array to judge whether the bus waveform in the controller area network bus has a falling edge or not.

If a falling edge occurs, the bus falling edge flag signal is set S325.

That is, the present embodiment uses a 2-wide merge array (i.e., the first merge array) to solve the implementation of the bit sync function. The method comprises the following steps of defining a combined array bus_status with the width of 2, wherein the array comprises two bits bus_status [0] and bus_status [1], assigning bus values to the bus_status [0] in a bit sequence counting unit, shifting the logic of the bus_status array by 1 bit by using a shifting operator after assigning, waiting for the clock pushing of the rising edge of a CAN bus clock, assigning the bus values to the bus_status [0], comparing the value of the bus_status [1] with the value of the bus_status [0] in a reverse mode to judge whether the bus waveform has a falling edge, and setting a bus falling edge flag signal if the falling edge occurs, wherein the signal setting indicates that the minimum unit count of the bit sequence should be cleared, so that the bit sequence synchronization is realized. Among them, the hard sync occurs in the start of frame (SOF) bit, and the resynchronization occurs in other bits than the SOF bit.

Then, step S33 is a step of sampling the bus signal value (i.e., the transmission bit) transmitted in the CAN bus by the sampling pulse after the bit timing synchronization determined and performed in accordance with the above steps. Similarly, although the present embodiment does not limit the specific sampling steps, a possible embodiment is provided, and the step S33 specifically includes:

s331, sampling a bus signal value transmitted in a controller area network bus whenever a bus sampling signal is set;

s332, stopping sampling of a bus signal value when the interrupt signal setting of the receiving node is monitored;

the interrupt signal is set by the receiving node after the data frame is transmitted.

That is, the present embodiment samples the bus signal value transmitted in the CAN bus based on the sampling pulse determined in the above embodiment, thereby grasping the bus signal value transmitted in the CAN bus for each bit. And, when the receiving unit receives the last bit of the data frame, a completion interrupt is set to indicate that the frame reception is completed. Therefore, the present embodiment uses the interrupt as a sampling end flag, and when detecting that the interrupt signal of the receiving node is set, the sampling of the bus signal value is stopped, so as to realize accurate sampling of one bus frame.

On the other hand, for step S40 in the method, the verification data for comparing and checking to verify the CAN bus controller module is determined according to the captured bus frame. From the above, it can be seen that the preconfigured parameters can be used as verification data for participating in verification, and are used for characterizing timing characteristics in frame transmission. In addition, the data characteristics in the frame transmission should be included, i.e. to verify that the specific data of the transmitted, captured during the transmission and received data frames are identical.

It should be noted that, in this embodiment, the capturing scheme of the bus frame information is not limited, and an appropriate extraction scheme may be selected according to the requirement of actually participating in the bus frame information of the subsequent verification. On the basis, the present embodiment further provides an extraction scheme of bus frame information, and step S40 specifically further includes:

S41, according to a bit filling mechanism in the controller area network bus protocol, performing bit filling processing on the sampled bus signal value to obtain a bit filling fixed format frame information queue.

The format of the fixed format frame information queue is filled in a bit-removing mode, and the format accords with the data frame format specified by a controller local area network bus protocol.

S42, extracting the data on the appointed data bit in the frame information queue with the fixed format according to the data frame format specified by the controller local area network bus protocol so as to determine the bus frame information.

It should be noted that, since it is specified in the CAN bus protocol that, between the SOF bits and Cyclic Redundancy Check (CRC) sequence segments (including the CRC sequence segments) in the frame format, five consecutive bits with the same level are then filled with a bit with opposite level polarity, which is bit filling, so as to ensure timeliness of bit synchronization and distinction from the error frame format. Therefore, the bus frame grabbed in the method also needs to be bit-stripped and filled to remove the useless data filled in the grabbed bus frame, and step S41 in this embodiment is a step of implementing bit-stripping and filling.

For the specific implementation of the step S41 bit stuffing function, the present embodiment is not limited but provides a possible implementation, and the step S41 specifically further includes:

and S411, when the bus signal value is obtained through sampling, assigning the bus signal value to the 0 th bit of the predefined second merging array.

Wherein the width of the second merge array is 12.

S412, judging whether the values of the 1 st bit to the 5 th bit of the second merging array are the same.

If the values are the same, S413, judging whether the values of the 1 st bit to the 11 th bit of the second merging array are all 1.

And S414, if the bus signal value obtained by the sampling is all '1', judging whether the bus signal value obtained by the sampling is '0'.

If the value is "0", the bus signal value is filled into the 0 th bit in the fixed format frame information queue, the initial acquisition frame signal is set, the value of the 1 st bit and the 5 th bit of the second merging array is reassigned to be "11101", and the logic of the second merging array is shifted to the left by 1 bit through a shift operator.

If not all "1", then the second merge array logic is shifted left by 1 bit by the shift operator S416.

S417, if different, judging whether the initial acquisition frame signal is set.

S418, if the initial acquisition frame signal is set, filling the bus signal value obtained by the sampling into a fixed format frame information queue, and shifting the second merging array logic by 1 bit leftwards through a shifting operator.

If the start acquisition frame signal is not set, the second merge array logic is shifted left by 1 bit by the shift operator S419.

It should be noted that "0", "1" and "11101" are binary data, and correspond to binary data on specific bits of the bus frame.

That is, in this embodiment, a merging array with a width of 12 is used as a bit-removing filling window array, the lower six bits of the array are bit-removing filling windows, and a queue is used as a bit-removing filling frame information queue to solve the implementation of bit-removing filling logic, and the specific scheme is as follows:

A merge array bit destuff check (i.e., the second merge array) of width 12 is defined and initialized to a value of 12' b0. When a bus sampling signal is received, the value of the grasped bus signal is assigned to bit_ destuff _check [0]. Because the CAN bus controller firstly transmits 11 bits 1 to the bus at the beginning of the simulation, the frame is transmitted after the bus is ensured to be idle. The bit-fill logic is used to determine if the bit-fill window bit_ destuff _check [5:1] is 5'b11111 or 5' b00000 when a bus sample signal is received, if so, to continue to determine if bit_ destuff _check [11:1] is 11'b1111_111, if so, to indicate that bit_ destuff _check has been written into 11 bits 1 in preparation for entering the bus frame transfer process, to continue to determine if the current fetch bus value bit_ destuff _check [0] is 0, if 0 indicates that this value is the transfer frame SOF bit, to add the bus value into the queue list, to set the start fetch frame signal, and to modify bit_ destuff _check [5:1] to reassign to 5' b11101, and finally to shift the bit_ destuff _check array logic to the left by 1 bit.

If the above judgment bit_ destuff _check [11:1] is not 11' b1111_1111_111, it indicates that the current CAN bus controller is still in the process of sending 11 bits 1 and waiting for bus idle. Or the current CAN bus controller is transmitting a frame, and the current grabbing bus value is a filling bit, and only the bit_ destuff _check array logic is shifted left by 1 bit.

If it is judged initially that bit_ destuff _check [5:1] is not 5'b11111 or 5' b00000, it is judged continuously whether the initial acquisition frame signal is set, if yes, it is indicated that the current bus transmission frame state is present and there are no five continuous same level bits, the current acquisition bus value bit_ destuff _check [0] is added into the queue, and then bit_ destuff _check array logic is shifted to the left by 1 bit.

If the above-mentioned judgment start acquisition frame signal is not set, it indicates that it is not bus transmission frame state currently, then only shift 1 bit to the left of bit_ destuff _check array logic.

After the bus frame transmission is completed, the receiving node sets a completion interrupt to indicate that the frame reception is completed, and the bus value capturing and processing unit monitors the interrupt signal setting in the verification platform to stop capturing and processing the bus signal, so that a complete bit-removing filling fixed format frame information queue can be obtained.

Based on the obtained bit-removed filling fixed format frame information queue, step S42 may extract any required frame information according to the frame format specified by the CAN bus protocol. Before explaining the specific embodiment of the present step, the implementation principle of the present step is explained:

As shown in fig. 3, the frame formats specified by the CAN bus protocol include two transmission function frames (data frames, remote control frames) and two formats (standard format, extended format), and based on the combination of the two formats, 4 main frame formats, namely, standard remote control frames, standard data frames, extended remote control frames and extended data frames, as shown in fig. 3 CAN be obtained.

Wherein the extended Identifier (IDE) bit value of the standard frame is 0, which is located at the 13 th bit (counting from left to right, SOF bit is the starting 0 th bit) in the standard frame format, and the IDE bit value of the extended frame is 1, which is also located at the 13 th bit in the extended frame format. The Remote Transmission Request (RTR) bit value of the data frame is 0, the RTR bit value of the remote control frame is 1, the RTR bit is positioned at the 12 th bit in the standard frame format, and is positioned at the 32 nd bit in the extended frame format. The original RTR position is occupied with a Substitute Remote Request (SRR) bit in the extended frame format, the SRR value is normally 1, and the SRR value is located at bit 12 in the extended frame format. The value of r0 in the reserved bits (r 0 and r 1) is 0, in the standard frame format at bit 14, in the extended frame format at bit 34, and the value of r1 in the reserved bits is 0, present only in the extended frame, in the extended frame format at bit 34. The frame Data Length (DLC) is a 4-bit binary number representing the frame data length in bytes, at bits 15-18 (high to low) in the standard frame format, and at bits 35-38 in the extended frame format.

It follows that, based on the specification of the frame format in the CAN bus protocol, the frame format of the bus frame CAN be determined by the specific identification bits in the bus frame, and any bus frame information required is extracted based on the frame format. Based on this, the present example also provides one possible implementation:

The special identification bit information described above includes an extended Identifier (IDE) bit value, a remote send request (RTR) bit value, a Substitute Remote Request (SRR) bit value, and reserved bit values (r 0 and r 1).

Step S42 specifically further includes:

S421, determining the format of the data frame to be transmitted is a standard format frame or an extended format frame according to the extended identifier bit value on the appointed data bit in the bit-fill fixed format frame information queue.

S422, based on the data frame format of the current transmission, extracting other special identification bit information, frame data length, frame data information, cyclic redundancy check value sequence and response field slot position value.

Specifically, in this embodiment, after the fixed format frame information queue is filled with the decompressed bits, the 13 th IDE parameter value in the queue is extracted, and the current frame is determined to be a standard format frame or an extended format frame. Then extracting other special identification bit values such as RTR, SRR, r0, r1, frame Data Length (DLC) and frame data information (frame data on other bits) according to the frame format type and fixed bits specified by CAN bus protocol, and CRC check value sequence and response field slot bit value (response field is ACK, which is composed of ACK slot and ACK separator, and has two bits).

After the above-mentioned bus frame information is obtained and the received frame information is obtained in step S50, the full matching of the transmitted frame information, the bus frame information and the received frame information in the subsequent step S60 may be performed. But further, the present embodiment also provides a possible implementation, where the bus frame information further includes a cyclic redundancy check value reference sequence.

In step S421, after determining that the format of the current transmission data frame is a standard format frame or an extended format frame, the method further includes:

S423, based on the data frame format of the current transmission, intercepting the frame data from the frame start bit to the front of the cyclic redundancy check value sequence as a part of frame information queue to be checked.

S424, processing the part of frame information queue to be checked through a cyclic redundancy check unit to obtain a cyclic redundancy check value reference sequence.

The cyclic redundancy check algorithm adopted by the cyclic redundancy check unit is a cyclic redundancy check algorithm specified by a controller area network bus protocol.

That is, in the present embodiment, a verification process of performing CRC check on the grasped bus frame is also added. Specifically, according to the part of data bits in the bus frame to be grabbed (namely, the part of frame information queue to be checked), a corresponding check value (namely, a cyclic redundancy check value reference sequence) is generated through a CRC check algorithm, and the corresponding check value is compared with the CRC check value sequence transmitted by the bus frame to finish CRC check of the bus frame.

It should be noted that, the CAN bus protocol specifies that the CRC-15 algorithm is used to implement the CRC check of the data frame, so that the cyclic redundancy check algorithm adopted by the cyclic redundancy check unit in this embodiment is the CRC-15 algorithm.

On the other hand, for the full matching of the three-way frame information implemented in step S60, it is easy to know whether the corresponding data items in the three-way frame information are completely identical, if so, it is indicated that the two CAN bus controller modules serving as the transmitting node and the receiving node are normal, and the verification passes, and if failed, the verification CAN be considered to fail or further verification is performed, which is not limited in this embodiment.

However, on the basis of the bus frame information determined in the above embodiment, the present embodiment also provides a possible full-match verification scheme, where step S60 specifically further includes:

S61, judging whether the transmission data frame is normally received by the receiving node according to the response field slot value in the bus frame information, if so, performing subsequent verification (namely, step S62 to step S66), and if not, returning verification failure information and exiting the method.

And S62, carrying out full matching on first special identification bit information in the bus frame information, the sending frame information and the receiving frame information, and outputting a first matching result.

S63, checking whether the second special identification bit information in the bus frame information accords with the controller local area network bus protocol, and outputting a checking result.

The first special identification bit information and the second special identification bit information are integrated into special identification bit information, and the second special identification bit information comprises a substitute remote request bit value and a reserved bit value.

And S64, carrying out full matching on the frame data length and the frame data information in the bus frame information, the sending frame information and the receiving frame information, and outputting a second matching result.

And S65, matching the cyclic redundancy check value sequence in the bus frame information with the cyclic redundancy check value reference sequence, and outputting a third matching result.

And S66, determining a verification result according to the first matching result, the second matching result, the checking result and the third matching result.

The embodiment firstly judges whether the ACK slot value in the bus frame information is 0 to judge whether the current frame is normally received by the receiving node, if 0 indicates that the frame is normally received, the parameters of the follow-up three-party frame information are fully matched, if 1 indicates that the frame is abnormally received, at the moment, the bus frame information is abnormally grabbed, verification is failed, so that parameter comparison is stopped, and the receiving normal or failure information is output.

The method comprises the steps of firstly, carrying out full matching on the extracted special identification bit value and the related parameter value in the preset parameter of the verification platform, and outputting matching success or failure information as a first matching result by a receiving node, wherein for part of special identification bit values (SRR, r0 and r 1), the part of parameters are automatically filled by a CAN bus controller according to the set frame format type, after the frame format type is determined, the value of the special identification bit values CAN be directly checked to judge whether the special identification bit values accord with the generating filling rule specified by a CAN bus protocol, and checking passing or failure information is output as a checking result. And performing full matching on the extracted frame data length and frame data information with the relevant parameter value in the preset parameters (namely sending frame information), and receiving the relevant parameter value in the frame information by the receiving node, and outputting successful or failed matching information as a second matching result. Further, for the CRC check on the bus frame information in the above embodiment, whether the CRC check value sequence in the bus frame is identical to the CRC check value reference sequence returned by the CRC-15 calculation unit is matched, and matching success or failure information is output as a third matching result. Based on the results of the 4 verification items, the final verification result can be determined.

Further, on the basis of the above example, this example also provides a possible implementation, and after step S66, the method further includes:

and S67, if any result of the first matching result, the checking result, the second matching result and the third matching result is not passed, determining an abnormal position item according to the non-passed result item.

Wherein the outlier location term characterizes the possible locations of anomalies that caused this verification failure.

And S68, returning verification failure information including the failed result item and the abnormal position item.

It is to be understood that in one of the simplest schemes for locating the abnormal position of verification failure, the method can be realized based on whether the data item with error belongs to any one of the sending frame information, the bus frame information or the receiving frame information. Because the matching of the method is three-party full matching, if one party is different from the data items corresponding to the other two parties and the other two parties are the same, the data items can be determined to be abnormal data items, and related personnel can be assisted to locate and verify the abnormal positions. In addition, other anomaly locating schemes may be used, which is not limited in this embodiment.

The present embodiment provides a possible implementation based on the foregoing provided concept of anomaly localization, where the step S67 specifically further includes:

S671, if the first matching result is not passed, determining that the abnormal data item in the first matching result belongs to the sending frame information, the bus frame information or the receiving frame information, if the abnormal data item belongs to the sending frame information, determining that the abnormal position item is a sending node, if the abnormal data item belongs to the bus frame information, determining that the abnormal position item is a CAN bus, and if the abnormal data item belongs to the receiving frame information, determining that the abnormal position item is a receiving node.

S672, if the checking result is not passed, determining that the abnormal position item is a CAN bus.

S673, if the second matching result is not passed, determining that the abnormal data item in the second matching result belongs to the sending frame information, the bus frame information or the receiving frame information, if the abnormal data item belongs to the sending frame information, determining that the abnormal position item is a sending node, if the abnormal data item belongs to the bus frame information, determining that the abnormal position item is a CAN bus, and if the abnormal data item belongs to the receiving frame information, determining that the abnormal position item is a receiving node.

S674, if the third matching result is not passed, determining that the abnormal position item is a CAN bus.

In particular, when the abnormal position item is determined to be the CAN bus, it is described that the bus frame information is abnormal. Further judgment is required at this time, and may be a problem in sampling the bus signal value from the CAN bus, or a problem in transmitting the data frame by the transmitting node. For the further judging scheme, the embodiment is not limited, and a suitable further judging scheme can be selected according to actual needs. According to the embodiment, the abnormal data item is analyzed, so that the abnormal position CAN be positioned to a certain extent, and the verification of the CAN bus controller module is realized by related personnel.

Based on the implementation manners provided in the foregoing embodiments, a complete flow of a bus controller module verification method provided by the present invention is shown in fig. 4. It CAN be seen that the bus controller module verification method provided by the invention CAN directly grasp the bus signal value from the CAN bus based on the CAN protocol, and sort the bus signal value into a complete data frame transmitted in the CAN bus based on the CAN bus protocol and the pre-configuration parameters. Based on the method, the pre-configuration parameters CAN determine the sending frame information sent by the sending node, the bus frame information grabbed from the CAN bus in the data frame transmission process and the receiving frame information acquired from the receiving node, so that three-party full matching CAN be realized, meanwhile, the verification of two bus controller modules is realized, and the verification accuracy is higher compared with the verification of two parties. In addition, in the method, the information required to be subjected to matching verification subsequently CAN be directly captured from the CAN bus, and the VIP of the CAN bus controller is not required, so that the verification and learning cost is greatly reduced. In addition, in the method, the verification of two CAN bus controller modules CAN be realized by one data frame transmission, compared with the verification of one CAN bus controller module realized by two CAN bus controller VIP nodes in the traditional scheme, the verification efficiency is higher, and the development period of a chip is further shortened.

In the above embodiments, a method for verifying a bus controller module is described in detail, and the present invention further provides a corresponding embodiment of a bus controller module verification system. As shown in fig. 1, the bus controller module verification system provided in this embodiment includes a bus verification platform and two bus controller modules to be tested;

the bus controller reference model is connected with the register of the transmitting node through a driver, the bus controller reference model is connected with the register of the receiving node through a receiver, and the bus controller reference model is used for realizing the steps of the bus controller module verification method according to the embodiment.

It should be noted that, the above-mentioned bus controller reference model may be written by using a System Verilog (an advanced hardware design verification language), so as to implement the building of the bus verification platform. In addition, the method for verifying a bus controller module provided by the above-mentioned method embodiment can be essentially regarded as a data stream processing method, and the execution subject of the method is the above-mentioned bus controller reference model in this embodiment. That is, the core of the present invention is that the bus controller reference model processes the data such as the preconfigured parameters, the bus signal values and the slave received frame information through the bus controller module verification method provided by the above method embodiment, so as to obtain the final verification result of the CAN bus controller module, and bring the technical effects described in the above method embodiment.

In addition, in a possible embodiment, the above-mentioned bus controller reference model is further divided into a plurality of functional modules to implement the different steps of the above-mentioned bus controller module verification method, and as shown in fig. 5, the bus controller reference model further includes a bit timing counting unit, a sampling signal flag generating unit, a bus value capturing and processing unit, a parameter comparison unit and a cyclic redundancy check calculating unit.

The method comprises a bit time sequence counting unit, a sampling signal mark generating unit, a bus value capturing and processing unit, a parameter comparison unit and a cyclic redundancy check calculating unit, wherein the bit time sequence counting unit is used for realizing the flow of a counting pulse generation part and a bit time sequence synchronization part in the embodiment of the method, the sampling signal mark generating unit is used for realizing a part flow of sampling pulse generation, the bus value capturing and processing unit is used for realizing the flow of sampling a bus signal value and a bit filling part removing, the parameter comparison unit is used for realizing a part flow of full matching of sending frame information, bus frame information and receiving frame information, and the cyclic redundancy check calculating unit is used for realizing the calculation of the cyclic redundancy check value reference sequence based on a CRC-15 algorithm.

Since the embodiments of the system portion and the embodiments of the method portion correspond to each other, the embodiments of the system portion refer to the description of the embodiments of the method portion, which is not repeated herein.

In addition to the embodiments of the method and the system for verifying a bus controller module provided in the foregoing embodiments, the present invention further provides a corresponding embodiment of a computer program product. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the bus controller module verification method according to any of the embodiments described above.

Since the embodiments of the computer program product portion and the embodiments of the method portion correspond to each other, the embodiments of the computer program product portion refer to the description of the embodiments of the method portion, which is not repeated herein.

FIG. 6 is a block diagram of a bus controller module verification apparatus according to another embodiment of the present invention, as shown in FIG. 6, the bus controller module verification apparatus includes a memory 10 for storing a computer program;

A processor 11 for implementing the steps of a bus controller module verification method according to the above embodiment when executing a computer program.

The bus controller module verification device provided in this embodiment may include, but is not limited to, a mobile terminal, a personal computer, a workstation, and the like.

Processor 11 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The Processor 11 may be implemented in at least one hardware form of a digital signal Processor (DIGITAL SIGNAL Processor, DSP), a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), a Programmable logic array (Programmable Logic Array, PLA). The processor 11 may also include a main processor, which is a processor for processing data in a wake-up state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor, which is a low-power processor for processing data in a standby state. In some embodiments, the processor 11 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 11 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.

Memory 10 may include one or more computer-readable storage media, which may be non-transitory. Memory 10 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 10 is at least used for storing a computer program 101, which, when loaded and executed by the processor 11, is capable of implementing the relevant steps of a bus controller module verification method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 10 may further include an operating system 102, data 103, and the like, and the storage manner may be transient storage or permanent storage. Wherein operating system 102 may include Windows, unix, linux, etc. The data 103 may include, but is not limited to, a bus controller module verification method, and the like.

In some embodiments, a bus controller module verification device may further include a display 12, an input/output interface 13, a communication interface 14, a power supply 15, and a communication bus 16.

Those skilled in the art will appreciate that the configuration shown in fig. 6 is not limiting of a bus controller module verification device and may include more or fewer components than shown.

The bus controller module verification device provided by the embodiment of the invention comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory.

Finally, the invention also provides a corresponding embodiment of the nonvolatile storage medium. The nonvolatile storage medium has stored thereon a computer program which, when executed by a processor, performs the steps described in the method embodiments described above.

It will be appreciated that the method of the above embodiments, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

The method, the system, the program product, the device and the medium for verifying the bus controller module provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Claims

1. The bus controller module verification method is characterized by being applied to a bus verification platform, wherein the bus verification platform is connected with two bus controller modules to be tested, and the two bus controller modules to be tested are connected through a controller local area network bus;

The method comprises the following steps:

determining bus frame information according to the bus signal value;

Performing full matching on the sending frame information, the bus frame information and the receiving frame information, and determining a verification result according to a full matching result;

wherein synchronously capturing bus signal values from the controller area network bus according to the baud rate and the bit timing parameters comprises:

Sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after the bit time sequence synchronization;

the bit time sequence parameters comprise a synchronization section parameter, a propagation time section parameter, a first phase buffer section parameter and a second phase buffer section parameter;

pushing the count of a preset minimum unit counting unit by the counting pulse;

Setting a bus sampling signal when the count value of the minimum unit counting unit reaches the sum of the synchronous section parameter, the propagation time section parameter and the first phase buffer section parameter so as to obtain the sampling pulse;

2. The bus controller module verification method of claim 1, wherein performing bit timing synchronization between the sampling pulse and a transmit bus signal in the controller area network bus comprises:

Shifting the first merge array logic left by 1 bit by a shift operator;

if a falling edge occurs, setting a bus falling edge mark signal;

3. The bus controller module verification method according to claim 2, wherein sampling the bus signal value transmitted in the controller area network bus according to the sampling pulse after the bit timing synchronization comprises:

4. A bus controller module verification method according to any one of claims 1 to 3, wherein determining bus frame information from the bus signal values comprises:

5. The method according to claim 4, wherein the performing, according to a bit filling mechanism in a controller area network bus protocol, a bit filling process on the sampled bus signal value to obtain a fixed format frame information queue after bit filling includes:

6. The bus controller module verification method of claim 4, wherein the special identification bit information comprises an extended identifier bit value, a remote transmission request bit value, a substitute remote request bit value, and a reserved bit value;

7. The bus controller module verification method of claim 6, wherein the bus frame information further comprises a cyclic redundancy check value reference sequence;

8. The bus controller module verification method according to claim 7, wherein performing full matching on the transmission frame information, the bus frame information, and the reception frame information, and determining a verification result based on the full matching result comprises:

9. The bus controller module verification method according to claim 8, further comprising, after determining the verification result from the first matching result, the second matching result, the check result, and the third matching result:

10. A bus controller module verification system is characterized by comprising a bus verification platform and two bus controller modules to be tested;

the bus controller reference model is connected with the register of the transmitting node through the driver, the bus controller reference model is connected with the register of the receiving node through the receiver, and the bus controller reference model is used for realizing the steps of the bus controller module verification method according to any one of claims 1 to 9.

11. A computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the bus controller module verification method of any one of claims 1 to 9.

12. A bus controller module verification apparatus, comprising:

a memory for storing a computer program;

A processor for implementing the steps of the bus controller module verification method according to any one of claims 1 to 9 when executing said computer program.

13. A non-volatile storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the bus controller module verification method of any one of claims 1 to 9.