CN115391181A - Verification method of SOC chip - Google Patents
Verification method of SOC chip Download PDFInfo
- Publication number
- CN115391181A CN115391181A CN202210948726.2A CN202210948726A CN115391181A CN 115391181 A CN115391181 A CN 115391181A CN 202210948726 A CN202210948726 A CN 202210948726A CN 115391181 A CN115391181 A CN 115391181A
- Authority
- CN
- China
- Prior art keywords
- verified
- chip
- processor
- data frame
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012795 verification Methods 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000003993 interaction Effects 0.000 claims abstract description 35
- 230000002452 interceptive effect Effects 0.000 claims abstract description 17
- 238000012360 testing method Methods 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims description 7
- 238000013461 design Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/3668—Testing of software
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/3668—Testing of software
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Prevention of errors by analysis, debugging or testing of software
- G06F11/3668—Testing of software
- G06F11/3696—Methods or tools to render software testable
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a verification method of an SOC chip, which comprises the following steps: the verification platform configures a module to be verified in a chip to be verified according to the test case; a processor of a chip to be verified generates a first data frame according to the current state of the processor and a set interactive frame structure configuration register, a verification platform reads and analyzes the first data frame to obtain a first analysis result, and if the processor is determined to be in an idle state by the first analysis result, the verification platform generates a second data frame requesting to enter a bus VIP control mode; the processor of the chip to be verified receives and analyzes the second data frame to obtain a second analysis result, and stops performing data interaction with the module to be tested through the bus to generate a third data frame; and the verification platform reads and analyzes the third data frame to obtain a third analysis result, and the VIP module of the verification platform performs data interaction with the to-be-verified module through the bus of the to-be-verified chip to complete verification of the to-be-verified chip. The method saves cost and improves verification speed.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to a verification method of an SOC chip.
Background
In the prior art, SOC chip design is often completed by multiple people, for example, a system S is designed, which includes a module AI, a module B1, and a module C1, a designer a designs the module A1, a designer B designs the module B1, and a designer designs the module C1, and when verification is performed, the module A1, the module B1, and the module C1 are integrated in a keil, compiled to form a bin file, and then the bin file is loaded into a UVM for verification, thereby completing verification of the chip system. In the system design which is jointly responsible for by a plurality of persons, because the keil provides the function of modifying the parameters for the user, when one designer or a plurality of designers modify the corresponding parameters in the keil and do not update the codes in time, other designers involved cannot use the newly modified module to carry out system verification, and the current verification result is unreliable. In addition, when two platforms are adopted for verification, the verification speed is low, so that the current verification result is unreliable.
Therefore, the SOC chip verification has the following defects: 1. the system verification is not convenient for designers to adopt the latest modified module; 2. two platforms need to be managed, a large amount of manpower is consumed, and the cost is high; 3. the verification speed is low, and the method is not suitable for the test case with the requirement on the verification speed.
Disclosure of Invention
The invention provides a verification method of an SOC chip, which aims to solve the problems that in the prior art, due to the fact that a designer modifies a module and does not adopt the latest modified module for verification, the verification result is inaccurate, manpower is consumed for managing two platforms, and the verification speed is low.
The first aspect of the present invention provides a verification method for an SOC chip, including:
the verification platform configures a module to be verified corresponding to the test case in the chip to be verified according to the test case;
the processor of the chip to be verified configures the register according to the current state of the processor and a set interactive frame structure to generate a first data frame;
the verification platform reads and analyzes the first data frame to obtain a first analysis result, and if the first analysis result determines that the processor is in an idle state, the verification platform configures the register to generate a second data frame requesting to enter a bus VIP control mode;
the processor of the chip to be verified receives and analyzes the second data frame to obtain a second analysis result, responds to the second result, stops performing data interaction with the module to be tested through the bus, and configures the register to generate a third data frame;
and the verification platform reads and analyzes the third data frame to obtain a third analysis result, and in response to the third analysis result, the VIP module of the verification platform performs data interaction with the to-be-verified module through a bus of the to-be-verified chip to complete verification of the to-be-verified chip.
Preferably, the interactive frame structure includes at least:
the firmware identification tag is used for recording the working state of the firmware in the processor of the chip to be verified;
the platform identification tag is used for recording the current working state of the verification platform;
an address entry for storing address information to which data is to be written;
a write data item for storing write data information;
and the read data item is used for storing read data information.
Preferably, the configuring, by the processor of the chip to be verified, the register according to the current state of the processor and the set interactive frame structure, and the generating the first data frame specifically includes:
and when the processor of the chip to be verified is in an idle state, the processor of the chip to be verified acquires a firmware identification code corresponding to the idle state, and writes the firmware identification code into the firmware identification tag to generate the first data frame.
Preferably, the configuring, by the verification platform, the register, and the generating the second data frame requesting to enter the bus VIP control mode specifically include:
and the verification platform acquires a platform identification code corresponding to the bus VIP control mode, writes the platform identification code into the platform identification tag and generates the second data frame.
Preferably, the step of stopping data interaction with the module to be tested through the bus by the processor of the chip to be verified, and configuring the register to generate the third data frame specifically includes:
and when the processor of the chip to be verified finishes stopping data interaction with the module to be tested through the bus, the processor of the chip to be verified acquires a corresponding firmware identification code, writes the firmware identification code into a firmware identification label of the interactive frame of the register, and generates a third data frame.
Preferably, the method further comprises:
when the verification platform detects interrupt processing, the VIP module suspends data interaction with the to-be-verified module through a bus in the to-be-verified chip and generates a fourth data frame, a processor of the to-be-verified chip reads and analyzes the fourth data frame, and in response to a fourth analysis result, the processor of the to-be-verified chip performs data interaction with the to-be-verified chip through the bus and performs interrupt processing.
Preferably, the pausing of the data interaction between the VIP module and the to-be-verified module through a bus in the to-be-verified chip and the generation of the fourth data frame specifically include:
after the VIP module suspends data interaction with the to-be-verified module through a bus in the to-be-verified chip, a program processor of the verification platform acquires a corresponding firmware identification tag, and writes the firmware identification tag into a firmware identification tag of an interactive data frame of the register to form a fourth data frame.
The embodiment of the invention has the following beneficial effects: the verification platform and the chip to be verified carry out data interaction through the interaction frame in the register, and the verification platform and the chip to be verified transmit the state information of the verification platform and the chip to be verified through the interaction frame, so that a user only needs to manage one verification platform, and in addition, data interaction is carried out through the VIP module, and the verification speed is improved. The verification method avoids the problem of verification caused by the fact that synchronization is forgotten due to modification and a newly modified model is not adopted for simulation, saves labor cost and provides verification speed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
Fig. 1 shows a block diagram of an SOC chip verification system according to a first embodiment of the present invention;
fig. 2 is a schematic flowchart illustrating an SOC chip verification method according to a first embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
Fig. 1 shows a block diagram of a chip verification system according to an embodiment of the present invention, where the chip verification system includes a chip to be verified and a verification platform, the chip to be verified and the verification platform interact with each other through corresponding interfaces, the chip to be verified includes a processor, a bus, a register, and modules to be verified, the processor in the chip to be verified performs data interaction with each module to be verified through the bus, and the verification platform includes a program processor, a sequence _ lib, a VIP verification component, and other verification components corresponding to the modules to be verified one by one, for example, the module to be verified of the chip to be verified includes an I2S module, a UART module, and a DSP module, and the verification components of the verification platform include at least an I2S verification component, a UART verification component, and a DSP verification component, where the sequence library includes a system-level read function, a write function, and a module-level read function and write function, where the system-level read function, the write function, and the write function in the verification component corresponding to the module to be verified.
As shown in fig. 2, a method for verifying an SOC chip according to an embodiment of the present invention includes the following steps:
s1, a verification platform executes a verification program, and configures a module to be verified corresponding to a test case in a chip to be verified according to the test case in the executed verification program.
And a program processor of the verification platform executes a verification program input by a client, and configures a corresponding module to be verified in the chip to be verified according to a test case in the executed verification program. For example, assuming that the currently executed test case is that the DSP reads data from the I2S for processing, the verification platform calls a system-level write function to write data to be read from the I2S by the DSP into a register of the I2S module.
S2, the processor of the chip to be verified configures the register according to the current state of the processor and the set interactive frame structure, and generates a first data frame.
The interactive frame structure at least comprises a firmware identification tag, an address, write data, read data and a platform identification tag. The 5 parts of the content in the interactive frame structure are respectively controlled by the processor of the chip to be verified and the verification platform, wherein the address, the write data and the firmware identification tag are written in by the verification platform, and the read data and the platform identification tag are written in by the processor of the chip to be verified.
To facilitate the forward and backward simulations, the frame structure is mapped into a selected set of RCC registers. Specifically, the firmware identification TAG is an RCC _ TC _ TAG register, the address is an RCC _ TC _ ADDR register, and the like, so that the reading and the writing of the processor of the chip to be verified are directly simple and universal reading and writing of the RCC register area.
When the current working state of the processor of the chip to be verified is idle, the processor of the chip to be verified acquires a platform identification tag corresponding to the idle state, for example, 0XF0, and writes the platform identification tag into the platform identification tag of the interactive frame of the register, thereby generating a first data frame.
And S3, the verification platform reads and analyzes the first data frame to obtain a first analysis result, and if the first analysis result determines that the processor is in an idle state, the verification platform configures the register to generate a second data frame requesting to enter a bus VIP control mode.
And the verification platform reads the first data frame in the register and analyzes the first interactive data frame to obtain a first analysis result, and when the first analysis result determines that the processor of the chip to be verified is in an idle state, the verification platform obtains a platform identification tag code corresponding to the bus VIP control mode, writes the platform identification tag code into a platform identification tag in an interactive frame structure of the register, and generates a second data frame.
And S4, reading and analyzing the second data frame by the processor of the chip to be verified to obtain a second analysis result, responding to the second result, stopping data interaction between the processor of the chip to be verified and the module to be tested through the bus, and configuring the register to generate a third data frame.
And the processor of the chip to be verified reads the second data frame in the register and analyzes the second data frame to obtain a second analysis result, if the second analysis result determines that the verification platform initiates a bus VIP control mode, the processor of the chip to be verified stops performing data interaction with a module to be tested through the bus, namely the processor of the chip to be verified releases a signal interacting with the bus, and after the processor of the chip to be verified releases the signal interacting with the bus, the processor of the chip to be verified obtains a firmware identification tag code corresponding to the release signal and writes the firmware identification tag code into a firmware identification tag of an interaction frame of the register to generate a third data frame.
And S5, the verification platform reads and analyzes the third data frame to obtain a third analysis result, and in response to the third analysis result, the VIP module of the verification platform performs data interaction with the to-be-verified module through a bus of the to-be-verified chip to complete verification of the to-be-verified chip.
And the verification platform reads and analyzes the third data frame to obtain a third analysis result, and if the third analysis result determines that the processor of the chip to be verified releases a signal for interacting with the bus, the VIP module of the verification platform performs data interaction with the module to be verified through the bus, namely, a signal between the VIP module enable and the bus.
The chip verification method of the embodiment of the invention further comprises the following steps: when a program processor of a verification platform is going to execute interrupt processing, the VIP module stops data interaction with the module to be verified through the bus, namely the VIP module releases signals with the bus, after the VIP module releases the signals with the bus, the program processor obtains a platform identification tag code corresponding to the verification platform at the moment, and writes the platform identification tag code into a corresponding platform identification tag to form a fourth data frame. And the processor of the chip to be verified reads and analyzes the fourth data frame to obtain a fourth analysis result, and after the fourth analysis result is determined to indicate that the VIP module releases a signal interacting with the bus, the processor of the chip to be verified enables an interaction signal between the processor of the chip to be verified and the bus to perform data interaction with a target object module in interrupt processing through the bus.
According to the chip verification method provided by the embodiment of the invention, the verification platform and the chip to be verified carry out data interaction through the interaction frame in the register, and the verification platform and the chip to be verified transmit the self state information through the interaction frame, so that a user only needs to manage one verification platform, and in addition, data interaction is carried out through the VIP module, and the verification speed is improved. The verification method avoids the verification problem caused by the fact that the latest modified model is not adopted for simulation due to the fact that synchronization is forgotten due to modification, saves labor cost, and provides verification speed.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (7)
1. An SOC chip verification method, comprising:
the verification platform configures a module to be verified corresponding to the test case in a chip to be verified according to the test case;
the processor of the chip to be verified configures the register according to the current state of the processor and a set interactive frame structure to generate a first data frame;
the verification platform reads and analyzes the first data frame to obtain a first analysis result, and if the first analysis result determines that the processor is in an idle state, the verification platform configures the register to generate a second data frame requesting to enter a bus VIP control mode;
the processor of the chip to be verified receives and analyzes the second data frame to obtain a second analysis result, responds to the second result, stops performing data interaction with the module to be tested through the bus, and configures the register to generate a third data frame;
and the verification platform reads and analyzes the third data frame to obtain a third analysis result, and in response to the third analysis result, the VIP module of the verification platform performs data interaction with the to-be-verified module through a bus of the to-be-verified chip to complete verification of the to-be-verified chip.
2. The method of claim 1, wherein the interactive frame structure comprises at least:
the firmware identification tag is used for recording the working state of the firmware in the processor of the chip to be verified;
the platform identification tag is used for recording the current working state of the verification platform;
an address entry for storing address information to which data is to be written;
a write data item for storing write data information;
and the read data item is used for storing read data information.
3. The method of claim 2, wherein the processor of the chip to be verified configures the register according to its current state and a set interactive frame structure, and generating the first data frame specifically includes:
and when the processor of the chip to be verified is in an idle state, the processor of the chip to be verified acquires a firmware identification code corresponding to the idle state, and writes the firmware identification code into the firmware identification tag to generate the first data frame.
4. The method of claim 3, wherein the authentication platform configuring the register to generate the second data frame requesting entry into the bus VIP control mode comprises:
and the verification platform acquires a platform identification code corresponding to the bus VIP control mode, writes the platform identification code into the platform identification tag and generates the second data frame.
5. The method of claim 4, wherein the step of stopping data interaction between the processor of the chip to be verified and the module to be tested through the bus and configuring the register to generate the third data frame specifically comprises:
and when the processor of the chip to be verified finishes stopping data interaction with the module to be tested through the bus, the processor of the chip to be verified acquires a corresponding firmware identification code, writes the firmware identification code into a firmware identification label of the interactive frame of the register, and generates a third data frame.
6. The method of claim 5, further comprising:
when the verification platform detects interrupt processing, the VIP module suspends data interaction with the to-be-verified module through a bus in the to-be-verified chip and generates a fourth data frame, a processor of the to-be-verified chip reads and analyzes the fourth data frame, and in response to a fourth analysis result, the processor of the to-be-verified chip performs data interaction with the to-be-verified chip through the bus and performs interrupt processing.
7. The method of claim 6, wherein the halting of the VIP module for data interaction with the module to be verified via a bus in the chip to be verified and the generating of the fourth data frame comprises:
after the VIP module suspends data interaction with the to-be-verified module through a bus in the to-be-verified chip, a program processor of the verification platform acquires a corresponding firmware identification tag, and writes the firmware identification tag into a firmware identification tag of an interactive data frame of the register to form a fourth data frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210948726.2A CN115391181A (en) | 2022-08-09 | 2022-08-09 | Verification method of SOC chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210948726.2A CN115391181A (en) | 2022-08-09 | 2022-08-09 | Verification method of SOC chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115391181A true CN115391181A (en) | 2022-11-25 |
Family
ID=84118633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210948726.2A Pending CN115391181A (en) | 2022-08-09 | 2022-08-09 | Verification method of SOC chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115391181A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952758A (en) * | 2023-03-10 | 2023-04-11 | 成都登临科技有限公司 | Chip verification method and device, electronic equipment and storage medium |
| CN118714058A (en) * | 2024-08-29 | 2024-09-27 | 山东云海国创云计算装备产业创新中心有限公司 | Bus controller module verification method, system, program product, device and medium |
-
2022
- 2022-08-09 CN CN202210948726.2A patent/CN115391181A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952758A (en) * | 2023-03-10 | 2023-04-11 | 成都登临科技有限公司 | Chip verification method and device, electronic equipment and storage medium |
| CN118714058A (en) * | 2024-08-29 | 2024-09-27 | 山东云海国创云计算装备产业创新中心有限公司 | Bus controller module verification method, system, program product, device and medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5838948A (en) | System and method for simulation of computer systems combining hardware and software interaction | |
| CN113868987B (en) | A verification platform and verification method for system-level chip | |
| US6427224B1 (en) | Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor | |
| US20050039174A1 (en) | Apparatus and method for co-simulating processors and DUT modules | |
| US20090024381A1 (en) | Simulation device for co-verifying hardware and software | |
| CN115391181A (en) | Verification method of SOC chip | |
| CN102184290B (en) | Cycle-accurate and bit-accurate system-level model building methods for embedded microprocessors | |
| US20050204345A1 (en) | Method and apparatus for monitoring computer software | |
| CN110321260B (en) | Uvm-based AXI bus interface read-write data comparison method and UVM verification platform | |
| Wang et al. | Exploration of Using Direct Programming Interface to Improve the Reusability of Verification IP | |
| US20130024178A1 (en) | Playback methodology for verification components | |
| US7584456B1 (en) | Method and apparatus for debugging embedded systems having read only memory | |
| US7577557B2 (en) | Simulator and simulation method for behaviors of processors | |
| Zachariah et al. | A novel algorithm to extract two-node bridges | |
| CN119476150A (en) | Method, device, equipment and medium for verifying chip functional coverage | |
| CN118036524A (en) | Chip design simulation method and related equipment | |
| CN118395918A (en) | Chip simulation method and device based on software and hardware, test terminal and medium | |
| US7729896B2 (en) | Cycle simulation method, cycle simulator, and computer product | |
| CN113806153B (en) | Chip verification method | |
| US20050144586A1 (en) | Automated generation method of hardware/software interface for SIP development | |
| CN116663461A (en) | DUT simulation verification platform, verification method thereof, medium and electronic equipment | |
| US20210173989A1 (en) | Simulation signal viewing method and system for digital product | |
| JP2013020425A (en) | Hardware and software cooperative verification method using open source software | |
| Carbognani et al. | Qualifying precision of abstract systemc models using the systemc verification standard | |
| US8914274B1 (en) | Method and system for instruction set simulation with concurrent attachment of multiple debuggers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |