CN118712202A - Display Panel - Google Patents

Abstract

The present application provides a display panel, including a display area, the display panel further comprising: a first substrate; a plurality of data lines, located in the display area, the film layer where the data lines are located is arranged on the first substrate; a plurality of metal oxide semiconductor layers, arranged on a surface of the data lines away from the first substrate and located in the display area, the metal oxide semiconductor layers are electrically connected to the data lines through first vias; and a plurality of drain electrodes, the drain electrodes are arranged on a surface of the metal oxide semiconductor layer away from the first substrate and located in the display area, the drain electrodes are electrically connected to the metal oxide semiconductor layers through second vias; wherein the metal oxide semiconductor layers are arranged in parallel with the data lines, and in a top view of the display panel, the metal oxide semiconductor layers at least partially overlap with the data lines. The display panel provided by the present application can further improve the pixel density.

Description

Display Panel

Technical Field

The present application relates to the field of display technology, and in particular to a display panel.

Background Art

Virtual reality (VR) products have extremely high requirements for the resolution of display panels. In order to eliminate the screen door effect and provide a more immersive visual experience, the pixel density (PPI, Pixels Per Inch) of the display panel of VR products needs to reach more than 1000.

To meet the above-mentioned high pixel density requirements, existing liquid crystal display panels use indium gallium zinc oxide (IGZO) to make thin-film transistors (TFTs). Indium gallium zinc oxide thin-film transistors have higher electron mobility and can significantly reduce the size of TFTs, thereby increasing pixel density.

However, the current structure of InGaZnO thin-film transistors is usually a planar structure, and the InGaZnO layer needs to be routed at an angle, which is not conducive to further improving the pixel density, and therefore cannot meet the requirements of virtual reality products for display panels with higher resolution.

Therefore, a new technical solution is urgently needed to further improve the pixel density.

Summary of the invention

The embodiments of the present application provide a display panel that can further improve pixel density.

An embodiment of the present application provides a display panel, which includes a display area, and the display panel includes: a first substrate; a plurality of data lines, which are located in the display area, and a film layer where the data lines are located is arranged on the first substrate; a plurality of metal oxide semiconductor layers, which are arranged on a surface of the data lines away from the first substrate and located in the display area, and the metal oxide semiconductor layers are electrically connected to the data lines through first vias; and a plurality of drain electrodes, which are arranged on a surface of the metal oxide semiconductor layer away from the first substrate and located in the display area, and the drain electrodes are electrically connected to the metal oxide semiconductor layers through second vias; wherein the metal oxide semiconductor layers are arranged in parallel with the data lines, and in a top view of the display panel, the metal oxide semiconductor layers and the data lines at least partially overlap.

In the above-mentioned display panel, the metal oxide semiconductor layer includes a first part and a second part, the first part is electrically connected to the data line, the second part is electrically connected to the drain, and the first part and the second part are located at different heights in a direction perpendicular to the plane where the display panel is located.

In the above-mentioned display panel, the display panel also includes: a first gate line, arranged below the second part of the metal oxide semiconductor layer; an interlayer insulating layer, arranged between the first gate line and the data line; a first gate insulating layer, arranged between the first gate line and the second part of the metal oxide semiconductor layer; a second gate line, arranged above the second part of the metal oxide semiconductor layer; and a second gate insulating layer, arranged between the second gate line and the metal oxide semiconductor layer.

In the above-mentioned display panel, the first gate line is arranged in parallel with the second gate line, the first gate line is arranged to cross the data line, and in the top view of the display panel, the first gate line at least partially overlaps with the metal oxide semiconductor layer and the data line, and the second gate line at least partially overlaps with the metal oxide semiconductor layer and the data line.

In the above display panel, the film layer where the first gate line is located is located above the film layer where the data line is located.

In the above display panel, in a top view of the display panel, the first gate line and the second gate line are both located between the first via hole and the second via hole.

In the above display panel, the first via hole penetrates the interlayer insulating layer and the first gate insulating layer, and the second via hole penetrates the second gate insulating layer.

In the above-mentioned display panel, the display panel also includes a peripheral area, and the part of the display panel located in the peripheral area includes: a gate driving circuit, the gate driving circuit includes a low-temperature polysilicon thin film transistor, and the first source and drain metal layer of the low-temperature polysilicon thin film transistor is arranged in the same layer as the data line.

In the above-mentioned display panel, the low-temperature polysilicon thin film transistor also includes a second source and drain metal layer, the second source and drain metal layer is electrically connected to the first source and drain metal layer, the second source and drain metal layer and the first gate line are arranged on the same layer, or the second source and drain metal layer and the second gate line are arranged on the same layer.

In the above display panel, the display panel further includes a third via hole, the third via hole penetrates the interlayer insulating layer, the first gate insulating layer and the second gate insulating layer, and the second source and drain metal layer is electrically connected to the first source and drain metal layer through the third via hole.

In the above display panel, in a top view of the display panel, the width of the metal oxide semiconductor layer is greater than the width of the data line, and the width of the drain electrode is greater than the width of the data line and less than or equal to the width of the metal oxide semiconductor layer.

In the above display panel, in a top view of the display panel, a connection line between the first via hole and the second via hole located at two ends of the same metal oxide layer is parallel to the data line.

The thin film transistor located in the display area of the display panel proposed in the embodiment of the present application is a vertical structure. In the thin film transistor, the source and the drain are arranged in layers and are respectively located below and above the metal oxide semiconductor layer, that is, the data line is placed in the lower layer of the metal oxide semiconductor layer, and the two are electrically connected through the first via hole, the drain is placed in the upper layer of the metal oxide semiconductor layer, and the two are electrically connected through the second via hole, the metal oxide semiconductor layer is parallel to the data line, and it is placed directly above the data line, and the orthographic projections of the two overlap. Compared with the traditional planar structure thin film transistor, the metal oxide semiconductor layer needs to have a part of the data line tilted (deflected) to increase the line spacing. The metal oxide semiconductor layer of the thin film transistor of the display panel of the present application does not have a tilted routing, which can greatly improve the pixel density, and can also reduce the occupied area of TFT, free up more space for improving the pixel density, and further improve the pixel density. Since the metal oxide semiconductor layer is all parallel to the data line and placed directly above the data line, and the two overlap at least partially, the length of the metal oxide semiconductor layer can be shortened, its resistance can be reduced, and thus the power consumption can be reduced. Since the source and drain metal layers of the thin film transistors in the peripheral area of the display panel share the same metal layer with the data lines and gate lines in the display area of the display panel, the number of masks in the manufacturing process is reduced, thereby reducing the production cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a display device provided in an embodiment of the present application.

FIG. 2 is a cross-sectional view of a first embodiment of a display panel provided by an embodiment of the present application.

FIG. 3 is a cross-sectional view of a second embodiment of a display panel provided by an embodiment of the present application.

FIG. 4 is a top view of the display panel shown in FIG. 2 and FIG. 3 .

DETAILED DESCRIPTION

To make the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

The term "parallel" includes absolute parallelism and approximately parallelism, wherein absolute parallelism refers to the situation where the angle between the straight lines corresponding to A and B is equal to 0 degrees, and approximately parallelism refers to the situation where the angle between the straight lines corresponding to A and B is greater than 0 degrees and less than or equal to 3 degrees.

The thin film transistors of the display panels in traditional virtual reality products adopt a planar structure. The metal oxide semiconductor layer in the thin film transistors of the planar structure is divided into three parts. The first part is parallel to the data line and mostly overlaps. The second part turns (inclined routing) to enter the opening area. The second part has a certain angle with the data line. The third part is parallel to the data line but does not overlap. Since the display panels in traditional virtual reality products generally have a high pixel density, that is, each pixel unit occupies a small area, in this case, the spacing at the inclined routing has to be designed to be smaller, but this will greatly increase the risk of short circuits and the pixel density cannot be further increased.

To this end, the embodiments of the present application provide a display device and a display panel that can overcome the above-mentioned technical problem that the pixel density cannot be further improved.

The display device provided by the embodiment of the present application includes an LCD display device, an OLED display device, etc. As shown in FIG1 , the display device includes a display panel, a timing controller TCON, a source driving circuit DD, and a power management chip (not shown in the figure). The power management chip can be integrated with the timing controller TCON into the same chip). The display panel includes a plurality of pixels P, a plurality of scan lines (GL1~GLn), a plurality of data lines (DL1~DLm), a gate driving circuit GOA, etc., the plurality of pixels P are arranged in rows and columns, the gate driving circuit GOA is electrically connected to the plurality of scan lines (GL1~GLn), the source driving circuit DD is electrically connected to the plurality of data lines (DL1~DLm), the scan lines (GL1~GLn) and the data lines (DL1~DLm) are electrically connected to the pixels P, and the timing controller TCON is electrically connected to the gate driving circuit GOA and the source driving circuit DD.

In the case where the display panel is an LCD display panel, the display panel includes a thin film transistor array substrate, an opposing substrate, and a liquid crystal material arranged between the thin film transistor array substrate and the opposing substrate. The thin film transistor array substrate includes a substrate, a gate drive circuit GOA, pixels P, scan lines (GL1~GLn), data lines (DL1~DLm), color resistance, etc. The pixel P includes a thin film transistor, a pixel electrode, etc. The thin film transistor is electrically connected to the pixel electrode, the scan line (GL1~GLn) and the data line (DL1~DLm).

In the case where the display panel is an OLED display panel, the display panel includes a substrate, a pixel P, a gate drive circuit GOA, an organic light-emitting device, an encapsulation layer, a polarizer, a color filter, etc. The substrate may be, for example, a glass substrate, a flexible substrate (for example, a polyimide substrate), etc. The pixel P includes an organic light-emitting device (OLED) and a drive circuit. The drive circuit includes a plurality of thin-film transistors. The organic light-emitting device is electrically connected to the drive circuit. The organic light-emitting device includes a light-emitting layer, an electron transport layer, a hole transport layer, a cathode and an anode, etc. The encapsulation layer includes an organic/inorganic alternating multilayer structure.

The gate driving circuit GOA includes a plurality of cascaded gate driving units. Each gate driving unit is electrically connected to a row of pixels P. The gate driving unit is used to provide a scanning signal to the pixels P.

The source driving circuit DD is used to provide data signals to the pixels P.

The timing controller TCON is used to receive externally input image data, and control the gate driving circuit GOA to output a scanning signal, and control the source driving circuit DD to output a data signal.

The power management chip is used to provide the required operating voltage for each part of the display device.

As shown in FIG. 2, FIG. 3 and FIG. 4, the embodiment of the present application provides a COA (Color-filter On Array) type LCD display panel, that is, the color filters R and G in the display panel provided in the embodiment of the present application are made on a thin film transistor array substrate. The display panel includes a thin film transistor array substrate, an opposing substrate, a liquid crystal material disposed between the thin film transistor array substrate and the opposing substrate, and a polarizer.

The thin film transistor array substrate includes a first substrate S1 made of a transparent material such as glass or plastic, and thin film transistors, data lines SE, gate lines (GE1, GE2, GE3), pixel electrodes, color filters (R, G), etc. arranged on the first substrate S1.

The counter substrate includes a second substrate S2 made of a transparent material such as glass or plastic, and a common electrode and the like are disposed on the second substrate S2.

The polarizer is arranged on the outer sides of the thin film transistor array substrate and the opposite substrate, and is used to adjust the polarization state of the light.

The display panel provided in the embodiment of the present application may further include a backlight module disposed on a side of the thin film transistor array substrate facing away from the opposite substrate.

The display panel provided in the embodiment of the present application includes a plurality of pixel units, each pixel unit generally includes three sub-pixels of red, green and blue, each sub-pixel is composed of a thin film transistor and a pixel electrode. A color filter is covered on the sub-pixel of the corresponding color to filter out light of other colors.

In order to achieve high pixel density (PPI), the size of the pixel unit needs to be reduced, which requires that the occupied area of the thin film transistor is smaller. Therefore, an embodiment of the present application provides a display panel, the display panel includes a display area AA, and the portion of the display panel located in the display area AA includes a plurality of metal oxide (IGZO) thin film transistors, which have a vertical structure, so the occupied area of the thin film transistor can be reduced. The display panel provided in the embodiment of the present application is suitable for VR products with extremely high PPI.

Specifically, the portion of the display panel located in the display area AA includes a plurality of data lines SE, a plurality of metal oxide semiconductor layers OS, and a plurality of drain electrodes DE. The data lines SE are located in the display area AA, and the film layer where the data lines SE are located is disposed on the first substrate S1. The material of the metal oxide semiconductor layer OS may be indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. The material of the drain electrode DE is a transparent conductive material, such as indium tin oxide (ITO).

The metal oxide semiconductor layer OS is disposed on a surface of the data line SE away from the first substrate S1 and is located in the display area AA. The metal oxide semiconductor layer OS is electrically connected to the data line SE through the first via hole H1. The metal oxide semiconductor layer OS is disposed in parallel with the data line SE, and in a top view of the display panel, as shown in FIG4 , the metal oxide semiconductor layer OS at least partially overlaps with the data line SE. The above technical solution can maximize the use of a limited area, thereby improving the aperture ratio.

The drain electrode DE is disposed above the metal oxide semiconductor layer OS, and the drain electrode DE is electrically connected to the metal oxide semiconductor layer OS through the second via hole H2.

The metal oxide semiconductor layer OS includes a first part and a second part, the first part is electrically connected to the data line SE, and the second part is electrically connected to the drain DE. The first part and the second part are located at different heights in a direction perpendicular to the plane where the display panel is located, thereby forming a vertically structured thin film transistor.

In the display area AA, the metal oxide semiconductor layer OS is a vertical structure. Specifically, the source electrode SE and the drain electrode DE of the metal oxide thin film transistor are respectively arranged on the upper and lower layers of the metal oxide semiconductor layer OS. In the embodiment of the present application, the source electrode, i.e., the data line SE, is arranged on the lower layer of the metal oxide semiconductor layer OS and is electrically connected to the metal oxide semiconductor layer OS through the first via hole H1. The drain electrode DE is arranged on the upper layer of the metal oxide semiconductor layer OS and is electrically connected to the metal oxide semiconductor layer OS through the second via hole H2.

This vertical thin film transistor structure allows the metal oxide semiconductor layer OS to be completely parallel to the data line SE, and the metal oxide semiconductor layer OS overlaps the data line SE. Compared with the planar thin film transistor, the vertical thin film transistor avoids the existence of a bypass branch (oblique line area) in the metal oxide semiconductor layer OS, thereby reducing the short circuit risk of the display panel when the display panel has a high PPI and improving reliability. In addition, the vertical thin film transistor allows the metal oxide semiconductor layer OS to be completely blocked under the data line SE, thereby greatly improving the aperture ratio.

To achieve the vertical structure, two parts (the first part and the second part) of the metal oxide semiconductor layer OS are connected by climbing. The first part is connected to the data line SE, and from the data line SE, it climbs into the first gate insulating layer GI2 and is connected to the second part. In other words, the metal oxide semiconductor layer OS has a vertical structure of climbing and crossing in the vertical direction, and is no longer in the same plane. The second part is electrically connected to the drain DE.

This vertical structure (layered climbing design) allows the metal oxide semiconductor layer OS to be arranged in a straight line in the plane layout without the need for a diagonal line, thus avoiding bypass branches (diagonal line areas in the plane structure), making it suitable for designs with extremely high pixel density, that is, the line width and line spacing can be further reduced to achieve an extremely high resolution of 2000+PPI. At the same time, since there is a height difference between the first part and the second part in the vertical direction, the occupied area of the metal oxide semiconductor layer OS can be reduced (increasing the area of the effective display area), further improving the aperture ratio and reducing power consumption. At the same time, since the metal oxide semiconductor layer OS is arranged in parallel with the data line SE, the overlapping area of the two is increased, further improving the aperture ratio.

The first part of the metal oxide semiconductor layer OS is located at a lower height and is electrically connected to the data line SE through the first via hole H1. The second part is located at a higher height and is electrically connected to the drain electrode DE through the second via hole H2. The first part and the second part are connected by a climbing structure (a transition structure in a direction perpendicular to the plane where the display panel is located), that is, the first part and the second part of the metal oxide semiconductor layer OS are stepped in the vertical direction.

As an improvement, a metal oxide film with different energy band structures is disposed on the upper and lower surfaces of the metal oxide semiconductor layer OS, respectively. This multilayer structure can improve the carrier mobility of the metal oxide semiconductor layer OS, thereby improving the switching characteristics and driving capability of the thin film transistor. At the same time, it can also improve the stability of the device and reduce performance degradation during long-term operation.

Furthermore, in the top view of the display panel, as shown in FIG. 4 , the width of the metal oxide semiconductor layer OS is greater than the width of the data line SE, and the width of the drain electrode DE is greater than the width of the data line SE and less than or equal to the width of the metal oxide semiconductor layer OS.

The display panel further includes a first gate line GE2, an interlayer insulating layer IL, a first gate insulating layer GI2, a second gate line GE3, and a second gate insulating layer GI3.

The first gate line GE2 is disposed under the second portion of the metal oxide semiconductor layer OS to control a conductive state of the second portion.

The interlayer insulating layer IL is disposed between the first gate line GE2 and the data line SE, and is used to isolate the first gate line GE2 from the data line SE.

The first gate insulating layer GI2 is disposed between the first gate line GE2 and the second portion of the metal oxide semiconductor layer OS, and is used to insulate the first gate line GE2 from the metal oxide semiconductor layer OS.

The second gate line GE3 is disposed above the second portion of the metal oxide semiconductor layer OS, and controls the conductive state of the second portion together with the first gate line GE2.

The second gate insulating layer GI3 is disposed between the second gate line GE3 and the metal oxide semiconductor layer OS, and is used to insulate the second gate line GE3 from the metal oxide semiconductor layer OS.

The film layer where the first gate line GE2 is located is located above the film layer where the data line SE is located.

In the top view of the display panel, as shown in FIG. 4 , the length direction of the metal oxide semiconductor layer OS is consistent with the length direction of the data line SE, and the metal oxide semiconductor layer OS crosses the first gate line GE2 and the second gate line GE3 .

The metal oxide semiconductor layer OS includes an active area, and the active area is located at the intersection of the first gate line GE2, the second gate line GE3 and the data line SE. The first gate line GE2 and the second gate line GE3 apply an electric field at a position corresponding to the active area to control the conductive state of the metal oxide semiconductor layer OS and realize the switching control of the pixel.

In the top view of the display panel, as shown in Figure 4, the first gate line GE2 and the second gate line GE3 are both located between the first via hole H1 and the second via hole H2, so the second portion of the metal oxide semiconductor layer OS is completely within the control range of the first gate line GE2 and the second gate line GE3, thereby optimizing the switching characteristics of the pixel.

The first gate line GE2 is arranged in parallel with the second gate line GE3, and the first gate line GE2 is arranged to cross the data line SE, and in the top view of the display panel, as shown in FIG4, the first gate line GE2 at least partially overlaps with the metal oxide semiconductor layer OS and the data line SE, and the second gate line GE3 at least partially overlaps with the metal oxide semiconductor layer OS and the data line SE. The first gate line GE2 and the second gate line GE3 are electrically connected in the peripheral area PA of the display panel.

The first gate line GE2 and the second gate line GE3 may have different driving voltages or the same driving voltage.

The first gate line GE2 and the second gate line GE3 may be synchronously driven or asynchronously driven.

The first via hole H1 penetrates the interlayer insulating layer IL and the first gate insulating layer GI2 , and the second via hole H2 penetrates the second gate insulating layer GI3 .

Specifically, in the manufacturing process, an interlayer insulating layer IL and a first gate insulating layer GI2 are deposited on the data line SE, and before the metal oxide semiconductor layer OS is formed, a first via hole H1 is opened in the interlayer insulating layer IL and the first gate insulating layer GI2 so that a first portion of the subsequently formed metal oxide semiconductor layer OS is electrically connected to the data line SE. Then, a second gate insulating layer GI3 is formed over the metal oxide semiconductor layer OS, and a second via hole H2 is opened in the second gate insulating layer GI3 so that a second portion of the metal oxide semiconductor layer OS is electrically connected to the drain electrode DE.

The first via hole H1 and the second via hole H2 may have different shapes and sizes. For example, the first via hole H1 has a larger size than the second via hole H2 to increase the contact area between the metal oxide semiconductor layer OS and the data line SE, and the second via hole H2 has a smaller size than the first via hole H1.

In the top view of the display panel, a connection line between the first via hole H1 and the second via hole H2 located at two ends of the same metal oxide layer OS is parallel to the data line SE.

In order to ensure that the inner wall of the first via hole H1 has good insulation properties and avoid leakage or short circuit between the metal oxide semiconductor layer OS and the data line SE, one improvement scheme is: making an insulating layer, such as an oxide insulating layer, on the inner wall of the first via hole H1. Another improvement scheme is: passivating the first via hole H1 to eliminate sharp corners, that is, the edge of the bottom surface of the first via hole H1 or the adjacent two surfaces of the edge of the opening are formed into obtuse angles or rounded corners.

The display panel also includes a peripheral area PA. The portion of the display panel located in the peripheral area PA includes a gate driving circuit. The gate driving circuit includes a low-temperature polycrystalline silicon thin film transistor. The first source and drain metal layer SD1 of the low-temperature polycrystalline silicon thin film transistor is arranged on the same layer as the data line SE. The film layer where the first source and drain metal layer SD1 is located is located above the film layer where the third gate GE1 of the low-temperature polycrystalline silicon thin film transistor is located.

The above metal oxide thin film transistor is arranged in the display area AA, and the low temperature polysilicon thin film transistor is arranged in the peripheral area PA, which is used to drive the first gate line GE2 and the second gate line GE3 of the display area AA. The first source and drain metal layer SD1 of the low temperature polysilicon thin film transistor is arranged in the same layer as the data line SE, so that they can be formed together in the same process step, simplifying the process.

The low temperature polysilicon thin film transistor further includes a second source-drain metal layer SD2, and the film layer where the second source-drain metal layer SD2 is located is located above the film layer where the first source-drain metal layer SD1 is located. The second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1, and the second source-drain metal layer SD2 and the first gate line GE2 are arranged in the same layer, as shown in FIG3, or the second source-drain metal layer SD2 and the second gate line GE3 are arranged in the same layer, as shown in FIG4.

If the second source-drain metal layer SD2 is disposed at the same layer as the first gate line GE2, the second source-drain metal layer SD2 can be formed together with the first gate line GE2 metal layer in the same process step. If the second source-drain metal layer SD2 is disposed at the same layer as the second gate line GE3, the second source-drain metal layer SD2 can be formed together with the second gate line GE3 metal layer in the same process step.

The display panel further includes a third via hole, which penetrates the interlayer insulating layer IL, the first gate insulating layer GI2 and the second gate insulating layer GI3, and the second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1 through the third via hole.

Specifically, in the manufacturing process, first, a data line SE, an interlayer insulating layer IL, a first gate line GE2, a first gate insulating layer GI2, a metal oxide semiconductor layer OS, and a second gate insulating layer GI3 are sequentially formed on a substrate. Then, a third via hole is opened in the interlayer insulating layer IL, the first gate insulating layer GI2, and the second gate insulating layer GI3, so that the third via hole penetrates the interlayer insulating layer IL, the first gate insulating layer GI2, and the second gate insulating layer GI3, and then a second source-drain metal layer SD2 is formed on the second gate insulating layer GI3, and the second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1 through the third via hole.

The third via hole may be in a special shape such as a cone or a step shape to ensure the electrical connection quality between the second source-drain metal layer SD2 and the first source-drain metal layer SD1 .

The third via has different diameters at different depths, which can ensure good step coverage and electrical connection.

There is a certain height difference between the second source-drain metal layer SD2 and the first source-drain metal layer SD1 , so the two are electrically connected through the third via hole.

The thin film transistor in the display panel in the embodiment of the present application, which is located in the display area AA, is a vertical structure. In the thin film transistor, the source electrode and the drain electrode DE are arranged in layers and are respectively located below and above the metal oxide semiconductor layer OS, that is, the data line SE is placed in the lower layer of the metal oxide semiconductor layer OS, and the two are electrically connected through the first via hole H1, the drain electrode DE is placed in the upper layer of the metal oxide semiconductor layer OS, and the two are electrically connected through the second via hole H2, the metal oxide semiconductor layer OS is parallel to the data line SE, and it is placed directly above the data line SE, and the orthographic projections of the two overlap partially. Compared with the traditional planar structure thin film transistor, the metal oxide semiconductor layer OS needs to be partially tilted (deflected) relative to the data line SE, resulting in an increase in line spacing. The metal oxide semiconductor layer OS of the thin film transistor of the display panel of the present application does not have a tilted routing, which can greatly improve the pixel density, and can also reduce the occupied area of TFT, free up more space for improving the pixel density, and further improve the pixel density. Since the metal oxide semiconductor layer OS is completely parallel to the data line SE and is placed directly above the data line SE, the two overlap at least partially, so the length of the metal oxide semiconductor layer OS can be shortened, its resistance can be reduced, and thus the power consumption can be reduced. Since the source and drain metal layers of the thin film transistors in the peripheral area PA of the display panel share the same metal layer with the data lines SE and gate lines in the display area AA of the display panel, the number of masks in the manufacturing process is reduced, thereby reducing production costs.

The embodiment of the present application provides a vertical structure LTPO design. In this design, the part of the display panel located in the display area AA adopts a vertical structure metal oxide semiconductor thin film transistor, the data line SE is placed below the metal oxide semiconductor layer OS, and the two are electrically connected through the first via H1, the drain DE is placed above the metal oxide semiconductor layer OS, and the two are electrically connected through the second via H2, the metal oxide semiconductor layer OS is all parallel to the data line SE, and is placed directly above the data line SE, and the orthographic projections of the two partially overlap. In this design, the metal oxide semiconductor layer OS does not need to turn (tilt routing) to enter the opening area, the occupied area of the thin film transistor can be further reduced, the size of the pixel unit can be further reduced, and thus a higher pixel density can be achieved, and the aperture ratio can be greatly improved.

In addition, the peripheral area PA of the display panel adopts low-temperature polysilicon thin film transistors, whose source and drain metal layers share the same metal layer with the data lines SE and gate lines of the display area AA, reducing the number of masks, lowering production costs and improving yield.

This solution proposes two embodiments:

Embodiment 1:

The metal oxide semiconductor thin film transistor of the display panel located in the display area AA adopts a vertical structure, the data line SE is arranged below the metal oxide semiconductor layer OS, and the drain DE is arranged above the metal oxide semiconductor layer OS. The metal oxide semiconductor layer OS is divided into two parts, the first part is connected to the data line SE, and the second part is connected to the drain DE, and the two parts are located at different heights in the vertical direction. This structure allows the metal oxide semiconductor layer OS to be routed in a straight line, which can be applied to ultra-high pixel density design requirements, such as 2000+ pixel density design requirements. The first source and drain metal layer SD1 of the low-temperature polysilicon thin film transistor located in the peripheral area PA of the display panel is arranged on the same layer as the data line SE in the display area AA, and the second source and drain metal layer SD2 is arranged on the same layer as the second gate line GE3 of the metal oxide thin film transistor, sharing the same layer of metal, saving the number of masks, reducing production costs, and improving yield.

Embodiment 2:

On the basis of the first embodiment, the second source-drain metal layer SD2 of the low-temperature polysilicon thin film transistor in the peripheral area PA of the display panel and the first gate line GE2 of the metal oxide thin film transistor are arranged on the same layer. This design reduces the height difference between the second source-drain metal layer SD2 and the first source-drain metal layer SD1, and only one interlayer insulating layer IL is separated, and the height difference is reduced from 0.6-1μm to 0.2-0.5μm, which greatly reduces the difficulty of the process and further improves the yield.

This solution proposes a new LTPO COA architecture display panel for extremely high pixel density display panels, which can significantly increase pixel density (for example, to more than 2000), increase aperture ratio, reduce power consumption, and improve color deviation. At the same time, the source and drain metal layer of the low-temperature polysilicon thin film transistor in the peripheral area PA of the display panel of this solution shares the same metal layer with the data line SE and gate line in the display area AA, which can reduce the number of masks, reduce costs, and improve yield.

The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims (12)

1. A display panel, the display panel comprising a display area, the display panel comprising:

a first substrate;

the data lines are positioned in the display area, and a film layer where the data lines are positioned is arranged on the first substrate;

The metal oxide semiconductor layers are arranged on one surface of the data line far away from the first substrate and are positioned in the display area, and the metal oxide semiconductor layers are electrically connected with the data line through first through holes; and

The drain electrodes are arranged on one surface of the metal oxide semiconductor layer, which is far away from the first substrate, and are positioned in the display area, and the drain electrodes are electrically connected with the metal oxide semiconductor layer through second through holes;

the metal oxide semiconductor layer is arranged in parallel with the data line, and the metal oxide semiconductor layer at least partially overlaps with the data line in a top view of the display panel.

2. The display panel according to claim 1, wherein the metal oxide semiconductor layer includes a first portion electrically connected to the data line and a second portion electrically connected to the drain electrode, the first portion and the second portion being located at different heights in a direction perpendicular to a plane in which the display panel is located.

3. The display panel according to claim 2, the display panel is characterized in that the display panel further comprises:

a first gate line disposed under the second portion of the metal oxide semiconductor layer;

an interlayer insulating layer disposed between the first gate line and the data line;

a first gate insulating layer disposed between the first gate line and the second portion of the metal oxide semiconductor layer;

A second gate line disposed over the second portion of the metal oxide semiconductor layer; and

And a second gate insulating layer disposed between the second gate line and the metal oxide semiconductor layer.

4. The display panel according to claim 3, wherein the first gate line is disposed in parallel with the second gate line, the first gate line is disposed to intersect the data line, and a portion where the first gate line overlaps the metal oxide semiconductor layer and the data line at least partially overlaps a portion where the second gate line overlaps the metal oxide semiconductor layer and the data line in a top view of the display panel.

5. The display panel of claim 3, wherein the film layer on which the first gate line is disposed is located above the film layer on which the data line is disposed.

6. The display panel of claim 3, wherein the first gate line and the second gate line are each located between the first via and the second via in a top view of the display panel.

7. The display panel of claim 3, wherein the first via penetrates the interlayer insulating layer and the first gate insulating layer, and the second via penetrates the second gate insulating layer.

8. A display panel according to claim 3, wherein the display panel further comprises a peripheral region, the portion of the display panel located in the peripheral region comprising:

the gate driving circuit comprises a low-temperature polysilicon thin film transistor, and a first source-drain metal layer of the low-temperature polysilicon thin film transistor and the data line are arranged on the same layer.

9. The display panel of claim 8, wherein the low temperature polysilicon thin film transistor further comprises a second source drain metal layer electrically connected to the first source drain metal layer, the second source drain metal layer being disposed on the same layer as the first gate line or the second source drain metal layer being disposed on the same layer as the second gate line.

10. The display panel of claim 9, further comprising a third via penetrating the interlayer insulating layer, the first gate insulating layer, and the second gate insulating layer, the second source drain metal layer being electrically connected to the first source drain metal layer through the third via.

11. The display panel according to claim 1, wherein a width of the metal oxide semiconductor layer is larger than a width of the data line, and a width of the drain electrode is larger than a width of the data line and smaller than or equal to a width of the metal oxide semiconductor layer in a top view of the display panel.

12. The display panel according to claim 1, wherein lines of the first via holes and the second via holes located at both ends of the same metal oxide layer are parallel to the data lines in a plan view of the display panel.