CN118676003B - Low-driving-loss trench gate silicon carbide VDMOS and preparation method thereof - Google Patents
Low-driving-loss trench gate silicon carbide VDMOS and preparation method thereof Download PDFInfo
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Abstract
本发明提供了一种低驱动损耗沟槽栅碳化硅VDMOS及其制备方法，包括：在碳化硅衬底下侧面淀积金属，形成漏极金属层，在碳化硅衬底上侧面外延生长，形成漂移层；形成阻挡层，刻蚀、离子注入，形成电流重新分配层；外延生长漂移层；去除原阻挡层，离子注入，在漂移层内形成第一P型阱区、第二P型阱区、P型源区及N型源区；重新形成阻挡层，刻蚀阻挡层形成通孔，刻蚀，干氧氧化，形成栅介质层，所述栅介质层内设有沟槽；淀积金属，形成栅极金属层及源极金属层，去除阻挡层，完成制备，降低器件驱动电压以及驱动损耗。
The invention provides a low-drive-loss trench-gate silicon carbide VDMOS and a preparation method thereof, comprising: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, epitaxially growing on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a current redistribution layer; epitaxially growing the drift layer; removing the original barrier layer, and ion implanting to form a first P-type well region, a second P-type well region, a P-type source region, and an N-type source region in the drift layer; reforming the barrier layer, etching the barrier layer to form a through hole, etching, and dry-oxygen oxidation to form a gate dielectric layer, wherein a groove is provided in the gate dielectric layer; depositing metal to form a gate metal layer and a source metal layer, and removing the barrier layer to complete the preparation, thereby reducing the device driving voltage and driving loss.
Description
Technical Field
The invention relates to a low-driving-loss trench gate silicon carbide VDMOS and a preparation method thereof.
Background
Silicon carbide MOSFETs are typical representatives of silicon carbide power devices and have wide application in the fields of electric automobiles, aerospace, power conversion, and the like. The excellent switching characteristics of silicon carbide VDMOS devices are particularly evident in high frequency applications, and as switching frequencies are increased, the drive loss and conduction loss of the device can be compared at certain operating frequencies, the drive loss becomes a non-negligible part of the device loss, and the reduction of the device drive loss is more important in silicon carbide devices.
Disclosure of Invention
The invention aims to solve the technical problem of providing a low-driving-loss trench gate silicon carbide VDMOS and a preparation method thereof, and the low-driving-loss trench gate silicon carbide VDMOS reduces the driving voltage and the driving loss of a device.
In a first aspect, the present invention provides a method for preparing a low driving loss trench gate silicon carbide VDMOS, including the steps of:
Step 1, depositing metal on the lower side surface of a silicon carbide substrate to form a drain electrode metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer;
step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a current redistribution layer;
step 3, removing the original barrier layer, and epitaxially growing a drift layer on the drift layer and the current redistribution layer;
step 4, ion implantation is carried out on the drift layer, and a first P-type well region is formed in the drift layer;
step 5, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a second P-type well region in the first P-type well region;
Step 6, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a P-type source region;
Step7, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form an N-type source region;
Step 8, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, the second P-type well region and the first P-type well region to form a groove, and performing dry oxygen oxidation in the groove to form a gate dielectric layer, wherein a groove is formed in the gate dielectric layer;
step 9, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, and depositing metal to form a gate metal layer;
And 10, removing the original barrier layer, reforming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, depositing metal to form a source metal layer, and removing the barrier layer to finish the preparation.
In a second aspect, the present invention provides a low-driving-loss trench-gate silicon carbide VDMOS, where the silicon carbide VDMOS is prepared by using the preparation method of the low-driving-loss trench-gate silicon carbide VDMOS described in the first aspect.
The invention has the advantages that:
1. the device constructs a double-P-type well region structure on the basis of a trench gate VDMOS device structure, the second P-type well region is low-doped, the total charge number of the well region with the inversion controlled by the device gate is reduced, the inversion balance voltage of the device can be effectively reduced, and the device driving voltage is reduced;
2. a current redistribution layer is constructed above the silicon carbide substrate of the device, so that the gate-drain capacitance of the device is reduced, the gate charge of the device can be effectively reduced, and the driving loss of the device is reduced;
3. The current redistribution layers of the device are distributed under the grid electrode and on the left side and the right side, so that the current on the left side and the right side of the grid electrode can be redistributed to the whole area of the device in the transverse direction of the drain electrode, and the current equalization effect is achieved;
4. the current redistribution layer of the device can also concentrate drain current to the current redistribution area, so that impact of large drain current on the corner of the grid electrode of the device is avoided, and the reliability of the grid electrode of the device is improved.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method for preparing a low-drive-loss trench-gate silicon carbide VDMOS according to the present invention.
Fig. 2 is a cross-sectional view of a process step of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 3 is a second process cross-sectional view of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 4 is a cross-sectional view of a process step three of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 5 is a cross-sectional view of a process of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 6 is a cross-sectional view of a process step of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 7 is a process cross-sectional view of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 8 is a cross-sectional view of a process step seven of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 9 is a cross-sectional view of a process step eight of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 10 is a cross-sectional view of a process nine of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 11 is a cross-sectional view of a process of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 12 is a cross-sectional view of a process of a low drive loss trench gate silicon carbide VDMOS of the present invention.
Fig. 13 is a schematic cross-sectional view showing a process of a low-drive-loss trench-gate silicon carbide VDMOS according to the present invention.
Fig. 14 is a schematic diagram of a low drive loss trench gate silicon carbide VDMOS according to the present invention.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
As shown in fig. 1 to 13, the preparation method of the trench gate silicon carbide VDMOS with low driving loss according to the embodiment of the present application includes the following steps:
Step 1, depositing metal on the lower side surface of a silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially growing on the upper side surface of the silicon carbide substrate 101 to form a drift layer 103;
Step 2, forming a barrier layer a on the drift layer 103, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 103 to form a current redistribution layer 102, wherein the ion implantation energy is 10-100kev;
Step 3, removing the original barrier layer a, and epitaxially growing a drift layer 103 on the drift layer 103 and the current redistribution layer 102;
Step 4, ion implantation is carried out on the drift layer 103, a first P-type well region 104 is formed in the drift layer 103, and the ion implantation energy is 200-300kev;
Step 5, forming a barrier layer b on the drift layer 103, etching the barrier layer b to form a through hole, and performing ion implantation on the drift layer 103 to form a second P-type well region 1041 in the first P-type well region 104, wherein the ion implantation energy is 200-270kev;
Step 6, removing the original barrier layer b, reforming the barrier layer c, etching the barrier layer c to form a through hole, and performing ion implantation on the drift layer 103 to form a P-type source region 105, wherein the ion implantation energy is 100-200kev;
step 7, removing the original barrier layer c, reforming the barrier layer d, etching the barrier layer d to form a through hole, and performing ion implantation on the drift layer 103 to form an N-type source region 106, wherein the ion implantation energy is 100-200kev;
Step 8, removing the original barrier layer d, reforming the barrier layer e, etching the barrier layer e to form a through hole, etching the drift layer 103, the second P-type well region 1041 and the first P-type well region 104 to form a groove 111, performing dry oxygen oxidation in the groove 111 to form a gate dielectric layer 107, wherein a groove 1071 is arranged in the gate dielectric layer 107;
Step 9, removing the original barrier layer e, reforming the barrier layer f, etching the barrier layer f to form a through hole, and depositing metal to form a gate metal layer 108;
and 10, removing the original barrier layer f, reforming the barrier layer g, etching the barrier layer g to form a through hole, etching the drift layer 103 to a depth of 300nm, depositing metal to form a source metal layer 109, and removing the barrier layer g to finish the preparation.
The doping concentration of the first P-type well region 104 is greater than the doping concentration of the second P-type well region 1041, the lower side of the second P-type well region 1041 and the lower side of the gate metal layer 108 are located on the same plane, the current redistribution layer 102 comprises a first distribution region 1021, a second distribution region 1022 and a third distribution region 1023, the first distribution region 1021, the second distribution region 1022 and the third distribution region 1023 are arranged at intervals, the second distribution region 1022 is arranged under the gate dielectric layer 107, the width of the second distribution region 1022 is equal to the width of the gate dielectric layer 107, the current redistribution layer 102, the silicon carbide substrate 101 and the drift layer 103 are all N-type, the doping concentration of the silicon carbide substrate 101 is 2e18cm -3, the doping concentration of the drift layer 103 is 5e16cm -3, the doping concentration of the current redistribution layer 102 is 5e17cm -3, the doping concentration of the first P-type region -3 e 5 cm 4 is the second P-type well region 107, the doping concentration of the second P-type well region is 37 cm 37, and the doping concentration of the drift layer 103 is 2e18cm -3, and the doping concentration of the current redistribution layer 103 is 5e18cm -3.
The gate dielectric layer 107 is silicon dioxide, the gate metal layer 108 is Al, the source metal layer 109 is Al, the drain metal layer 110 is Ni, al alloy, and the ratio is 2:8. The thickness of the silicon carbide substrate 101 of the device is 1 mu m, the thickness of the drift layer 103 is 20-30 mu m, the thickness of the current redistribution layer 102 is 290-310nm, the thickness of the first P-type well region 104 is 300nm, the thickness of the second P-type well region 1041 is 200nm, the bottom of the first P-type well region is flush with the bottom of the gate metal layer 108, the width of the second P-type well region 1041 is 100nm, the thickness of the bottom of the gate dielectric layer 107 is 30nm, the thickness of the side wall is 20nm, the thickness of the N-type source region 106 is 300nm, the thickness of the P-type source region 105 is 300nm, the thickness from the top of the source metal layer 109 to the top of the N-type source region 106 is 300nm, the thickness of the gate metal layer 108 is 800nm, and the withstand voltage of the device is 1200-3000V;
The concentration of the silicon carbide substrate 101 is used for forming low-resistance ohmic contact with the drain electrode metal layer 110, so that the on-resistance of the device is reduced, the thickness of the silicon carbide substrate is used for guaranteeing support during device epitaxy, the process stability is improved, the doping concentration of the current redistribution layer 102 is used for realizing the doping concentration transition of the silicon carbide substrate 101 and the drift layer 103, and the current redistribution function is guaranteed;
The current redistribution layer 102 can shield the capacitance effect from the grid electrode to the n+ SiC substrate, reduce the grid-drain capacitance of the device, effectively reduce the grid charge of the device and reduce the driving loss of the device.
The current redistribution layer 102 of the device can concentrate drain current to the current redistribution layer area, so that impact of large drain current on the corner of the gate of the device is avoided, and the reliability of the gate of the device is improved;
The doping concentration of the first P-type well region 104 of the device is larger than that of the second P-type well region 1041, so that the first P-type well region 104 can realize inversion and high electron concentration under smaller gate voltage, the well region structure can reduce the gate driving voltage of the device, further reduce the driving loss of the device, the doping concentration of the first P-type well region 104 of the device is relatively higher, the bottom of the first P-type well region 104 is equal to the bottom of the gate dielectric layer 107, and the inhibition of electric field concentration at the corners of the gate can be realized, so that the reliability of the gate is improved.
As shown in fig. 14, the silicon carbide VDMOS obtained by the above-described manufacturing method includes:
A silicon carbide substrate 101, a current redistribution layer 102, the lower side of the current redistribution layer 102 being connected to the upper side of the silicon carbide substrate 101;
A drift layer 103, wherein a lower side surface of the drift layer 103 is connected to an upper side surface of the silicon carbide substrate 101 and to a current redistribution layer 102;
A first P-type well region 104, wherein the lower side surface of the first P-type well region 104 is connected to the upper side surface of the drift layer 103, and a second P-type well region 1041 is arranged on the first P-type well region 104;
a P-type source region 105, wherein the lower side of the P-type source region 105 is connected to the upper side of the first P-type well region 104;
the lower side surface of the N-type source region 106 is connected with the upper side surface of the first P-type well region 104 and the upper side surface of the second P-type well region 1041 respectively, and the outer side surface of the N-type source region 106 is connected with the inner side surface of the P-type source region 105;
The lower side surface of the gate dielectric layer 107 is connected to the upper side surface of the drift layer 103, and the outer side surface of the gate dielectric layer 107 is respectively connected to the first P-type well region 104, the second P-type well region 1041 and the N-type source region 106; a trench 1071 is arranged in the gate dielectric layer 107;
A gate metal layer 108, the gate metal layer 108 being disposed within the trench 1071;
A source metal layer 109, wherein the source metal layer 109 is connected to the N-type source region 106 and the P-type source region 105, respectively;
And a drain metal layer 110, the drain metal layer 110 being connected to the underside of the silicon carbide substrate 101.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
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