CN118645132B

CN118645132B - Low-power Boolean operation circuit and chip based on 10T-SRAM unit

Info

Publication number: CN118645132B
Application number: CN202411129065.6A
Authority: CN
Inventors: 朱翠杰; 刘云炜
Original assignee: Suzhou Kuanwen Electronic Science & Technology Co ltd
Current assignee: Suzhou Kuanwen Electronic Science & Technology Co ltd
Priority date: 2024-08-16
Filing date: 2024-08-16
Publication date: 2024-11-12
Anticipated expiration: 2044-08-16
Also published as: CN118645132A

Abstract

The present invention relates to the technical field of static random access memory, and specifically provides a low-power Boolean operation circuit and chip based on 10T-SRAM cells, the circuit comprising: a precharge module, precharges RBL during data reading or Boolean operation; a storage module, comprising two 10T-SRAM cells that share RBL, WBL and WBLB and are both read-write separated, which are connected to the precharge module; a charge control module, controls an enable signal EN to collect or release leakage charge, which is connected to the storage module; a Boolean operation module, controls the reference voltage of a sensitive amplifier to perform Boolean operation, which is connected to the charge control module. The present invention performs in-memory calculation based on a 10T-SRAM cell with read-write separation, while realizing independent two-cell Boolean operation, ensuring that the storage node is not destroyed; the leakage charge during data reading and Boolean operation is collected and released, and the leakage power consumption is reused, which has the advantage of low power consumption.

Description

Low-power-consumption Boolean operation circuit and chip based on 10T-SRAM unit

Technical Field

The invention relates to the technical field of static random access memories, in particular to a low-power-consumption Boolean operation circuit and a chip based on a 10T-SRAM unit.

Background

With the rapid development of artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) technology, the demands of neural network processing units (Neural Network Processing Unit, NPU) for computing power are increasing, while the conventional von neumann architecture causes higher power consumption and delay due to frequent data transmission between the memory and the arithmetic logic unit, and as the frequency of the processing units increases, the memory bottleneck is also becoming more obvious.

The in-memory computing (Computing In Memory, abbreviated as CIM) is used as a framework for directly embedding the computing unit into the memory, and the data processing is directly carried out in the memory, so that the data movement between the computing unit and the memory is reduced, the power consumption and the delay expenditure of the traditional framework can be effectively reduced, and the computing efficiency is improved.

However, the frequent reading of memory and computation by the CIM results in a significant amount of read power consumption. Along with the continuous improvement of the semiconductor process, the main frequency of the chip is also continuously improved, and the power consumption generated by CIM becomes more and more non-negligible. In addition, the existing CIM structure has a risk of damaging storage nodes when using conventional storage units, which can lead to data and operation result errors.

Disclosure of Invention

Therefore, the main purpose of the invention is to provide a low-power-consumption Boolean operation circuit and a chip based on a 10T-SRAM unit, which aim to solve the technical problems that the power consumption of the existing CIM structure is large and the risk of damaging storage nodes exists when a conventional storage unit is used.

In order to solve the above technical problems, the present invention provides a low power consumption boolean operation circuit based on a 10T-SRAM cell, comprising:

a precharge module for precharging the first read bit line RBL at the time of data reading or boolean operation, and precharging the first write bit line WBL and the second write bit line WBLB at the time of data writing;

a storage module for storing data; the memory module comprises two 10T-SRAM units, wherein the two 10T-SRAM units share the first read bit line RBL, the first write bit line WBL and the second write bit line WBLB and are of a read-write separation structure; the storage module is connected with the pre-charge module through the first write bit line WBL, the second write bit line WBLB and the first read bit line RBL;

The charge control module is used for controlling the enable signal EN to collect or release electric leakage charges when the data reading or the Boolean operation is performed; the charge control module is connected with the storage module through a first virtual ground line VGA, a second virtual ground line VGB and the first read bit line RBL;

The Boolean operation module is used for controlling the reference voltage of the sense amplifier and performing Boolean operation; the boolean operations include NAND and NOR; the Boolean operation module is connected with the charge control module.

In one embodiment of the invention, the two 10T-SRAM cells each include 8 NMOS tubes and 2 PMOS tubes;

The first NMOS tube, the second NMOS tube, the first PMOS tube and the second PMOS tube form a mutual coupling latch, a first storage node is arranged at the joint of the drain electrode of the first PMOS tube and the source electrode of the first NMOS tube, and a second storage node is arranged at the joint of the drain electrode of the second PMOS tube and the source electrode of the second NMOS tube; the grid electrode of the third NMOS tube is connected with a first write word line, the source electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the third NMOS tube is connected with the first write bit line WBL; the grid electrode of the fourth NMOS tube is connected with the first write word line, the source electrode of the fourth NMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the fourth NMOS tube is connected with the second write bit line WBLB; the grid electrode of the fifth NMOS tube is connected with the first storage node, the source electrode of the fifth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the drain electrode of the fifth NMOS tube is connected with a second read bit line from the first leakage path; the grid electrode of the sixth NMOS tube is connected with the first storage node, the source electrode of the sixth NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the sixth NMOS tube is connected with a third read bit line from the second leakage path; the grid electrode of the seventh NMOS tube is connected with a first read word line, and the source electrode of the seventh NMOS tube is connected with the first virtual ground line VGA; and the grid electrode of the eighth NMOS tube is connected with a second read word line, and the source electrode of the eighth NMOS tube is connected with the second virtual ground line VGB.

In one embodiment of the present invention, when the data is read, the first read bit line RBL is precharged to a high level, and the switching signal of the sense amplifier is set to a high level; and setting the first read word line and the second read word line connected with one 10T-SRAM unit to be high, wherein the seventh NMOS tube and the eighth NMOS tube of the 10T-SRAM unit are both conducted.

In one embodiment of the present invention, the first read bit line RBL is precharged to a high level while the boolean operation NAND or NOR is performed; setting the first read word line connected with one 10T-SRAM unit to be high level so as to enable the corresponding seventh NMOS tube to be conducted, and setting the second read word line connected with the other 10T-SRAM unit to be high level so as to enable the corresponding eighth NMOS tube to be conducted; setting a switching signal of the sense amplifier to a high level; the enable signal EN is set to a high level.

In one embodiment of the present invention, the reference voltage is set to 0.4V when the boolean operation NAND is performed; setting the reference voltage to 0.8V when the Boolean operation NOR is performed;

When the Boolean operation NAND or NOR is between a logic high level and a logic high level, setting the first storage nodes of the two 10T-SRAM units to be high level 1V; when the Boolean operation NAND or NOR is between a logic low level and a logic low level, setting the first storage nodes of the two 10T-SRAM units to be 0V at a low level; when the boolean operation NAND or NOR is between a logic high level and a logic low level, the first storage node of one of the 10T-SRAM cells is set to a high level 1V and the first storage node of the other 10T-SRAM cell is set to a low level 0V.

In one embodiment of the present invention, when the data writing is performed, the first write bit line WBL and the second write bit line WBLB are precharged to a high level, and then the first write bit line WBL and the second write bit line WBLB are discharged based on the written data to form a pair of high and low levels; and setting the first writing line to be high level, wherein the third NMOS tube and the fourth NMOS tube are conducted, and the pair of high and low levels are written into the first storage node and the second storage node.

In one embodiment of the present invention, the charge control module includes a first capacitor, a second capacitor, a ninth NMOS transistor, a tenth NMOS transistor, and a third PMOS transistor;

In the leakage period, the switching signal of the sense amplifier is set to be high level, the enabling signal EN is set to be high level, the ninth NMOS tube and the tenth NMOS tube are conducted, and the third PMOS tube is cut off; when the first read bit line RBL leaks electricity through the first virtual ground line VGA, the first capacitor is charged; when the first read bit line RBL leaks electricity through the second virtual ground line VGB, the second capacitor is charged; the first capacitor and the second capacitor are connected in parallel when being charged;

After the leakage period is finished, setting a switching signal of the sense amplifier to be low level, setting the enable signal EN to be low level, cutting off the ninth NMOS tube and the tenth NMOS tube, conducting the third PMOS tube, and discharging the first capacitor and the second capacitor in series; when the potential of the first virtual ground line VGA is higher than the potential of the first read bit line RBL, the first virtual ground line VGA charges the first read bit line RBL; when the potential of the first virtual ground line VGA is equal to or less than the potential of the first read bit line RBL, the first read bit line RBL is held by the first virtual ground line VGA.

In one embodiment of the present invention, the charge control module further includes an eleventh NMOS transistor, where the eleventh NMOS transistor is connected to the boolean operation module; the eleventh NMOS tube is used for preventing the charging current from flowing back to the sense amplifier to cause error output in the leakage period.

In one embodiment of the invention, the charge control module further comprises a diode.

In a second aspect, in order to solve the above technical problem, the present invention further provides a chip, to which the low power boolean operation circuit based on the 10T-SRAM cell is applied.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

The invention provides a low-power-consumption Boolean operation circuit and a chip based on a 10T-SRAM unit, wherein (1) the 10T-SRAM unit based on read-write separation performs in-memory calculation, and the memory node is ensured not to be damaged while realizing the Boolean operation of two independent units; (2) The Boolean operation is performed by controlling the reference voltage, and the leakage charges during data reading and Boolean operation are collected and released, so that leakage current loss is reduced, the reutilization of leakage power consumption is realized, and the method has the advantage of low power consumption.

Drawings

In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings.

FIG. 1 is a schematic diagram of a low power Boolean operation circuit based on a 10T-SRAM cell in a preferred embodiment of the present invention;

FIG. 2 is a block diagram of a 10T-SRAM cell of the schematic diagram of FIG. 1;

FIG. 3 is a schematic diagram showing an internal structure of the Boolean operation module S4 in the schematic diagram shown in FIG. 1;

FIG. 4 is a logic diagram of Boolean operation in a preferred embodiment of the invention;

FIG. 5 is a graph showing the reference voltage VREF in accordance with the preferred embodiment of the present invention;

FIG. 6 is a diagram of the logic output waveforms of Boolean operation in the preferred embodiment of the present invention;

fig. 7 is a waveform diagram of the RBL potential of the first read bit line according to a preferred embodiment of the present invention.

Description of the specification reference numerals:

s1, a pre-charging module; s2, a storage module; s3, a charge control module; s4, a Boolean operation module;

P1 to P3 are three PMOS tubes; BLPR precharge signal;

An RBL first read bit line; WBL first write bit line; WBLB second write bit line; VGA first virtual ground wire; VGB second virtual ground wire; WWL first write word line; q a first storage node; a QB second storage node; RWLA a first read word line; RWLB second read word lines; RBLA second read bit lines; a RBLB third read bit line; cell1 first leakage path; cell2 second leakage path; RWL read word line;

An EN enable signal; c1 a first capacitor; c2 second capacitance; d1 diode;

A DO sense amplifier output; VREF reference voltage; a SAEN switching signal; q1 is a positive input node; a QB1 inverting input node;

A first NMOS tube of MN 1; a second NMOS transistor of MN 2; a third NMOS transistor of MN 3; a fourth NMOS transistor of MN 4; MN5 fifth NMOS transistor; MN6 sixth NMOS transistor; MN7 seventh NMOS transistor; an MN8 eighth NMOS tube; MN9 ninth NMOS transistor; MN10 tenth NMOS transistor; MN11 eleventh NMOS transistor; MN12 twelfth NMOS transistor; MN13 thirteenth NMOS transistor; MN14 fourteenth NMOS transistor;

MP1 first PMOS tube; MP2 second PMOS tube; MP3 third PMOS tube; MP4 fourth PMOS tube; MP5 fifth PMOS tube.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. In the present application, the description as relating to "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance thereof or implicitly indicating the number of technical features indicated.

Due to the continuous improvement of the AI calculation force demand, a calculation system with separated storage and calculation is more and more not suitable for the current technical system, and the CIM integrated with calculation and storage is generated.

However, the conventional CIM requires a large number of data reading operations, which generates dynamic power consumption occupying a considerable proportion, and does not conform to the concept of low power consumption design of the current System on Chip (SoC). The existing CIM does not fully consider the problem of leakage power consumption during operation, and the conventional storage unit is used, so that the storage node is damaged, and data and operation results are wrong.

It can be seen that it becomes important to design low power in-memory computing circuits that use non-conventional memory cells. Therefore, the embodiment of the application provides a low-power-consumption Boolean operation circuit and a chip based on a 10T-SRAM unit.

Examples

The embodiment provides a low-power-consumption Boolean operation circuit based on a 10T-SRAM unit, as shown in FIG. 1, comprising:

a precharge module S1 for precharging the first read bit line RBL at the time of data reading or boolean operation, and precharging the first write bit line WBL and the second write bit line WBLB at the time of data writing;

A storage module S2 for storing data; the memory module S2 includes two 10T-SRAM cells, and the two 10T-SRAM cells share the first read bit line RBL, the first write bit line WBL, and the second write bit line WBLB, and are both read-write separation structures; the storage module S2 is connected to the precharge module S1 through the first write bit line WBL, the second write bit line WBLB and the first read bit line RBL;

A charge control module S3 for controlling the enable signal EN to collect or release the leakage charge when the data reading or the boolean operation is performed; the charge control module S3 is connected to the storage module S2 through a first virtual ground line VGA, a second virtual ground line VGB and the first read bit line RBL;

A boolean operation module S4, which controls the reference voltage VREF of the sense amplifier, for performing the boolean operation; the boolean operations include NAND and NOR; the boolean operation module S4 is connected to the charge control module S3.

The following describes the low-power boolean operation circuit based on the 10T-SRAM cell in detail:

1. Prefill module S1

For example, referring to fig. 1, the pre-charging module S1 includes three PMOS transistors P1 to P3; the gates of the PMOS tubes P1-P3 are connected with a precharge signal BLPR;

Specifically, when the precharge signal BLPR is set to a low level, the PMOS transistors P1 to P3 are all turned on; when the precharge signal BLPR is set to a high level, the PMOS tubes P1-P3 are all turned off.

2. Storage module S2

For example, referring to FIG. 1, the memory module S2 includes two 10T-SRAM cells in the same column, each 10T-SRAM cell being used for storing 1Bit of data.

Specifically, referring to FIG. 2, the two 10T-SRAM cells each include 8 NMOS tubes and 2 PMOS tubes;

optionally, the first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1, and the second PMOS transistor MP2 form a mutual coupling latch, a first storage node Q is disposed at a connection position between a drain electrode of the first PMOS transistor MP1 and a source electrode of the first NMOS transistor MN1, and a second storage node QB is disposed at a connection position between a drain electrode of the second PMOS transistor MP2 and a source electrode of the second NMOS transistor MN 2;

Further, a gate of the third NMOS transistor MN3 is connected to the first write word line WWL, a source of the third NMOS transistor MN3 is connected to a drain of the first PMOS transistor MP1, and a drain of the third NMOS transistor MN3 is connected to the first write bit line WBL;

Further, a gate of the fourth NMOS transistor MN4 is connected to the first write word line WWL, a source of the fourth NMOS transistor MN4 is connected to a drain of the second PMOS transistor MP2, and a drain of the fourth NMOS transistor MN4 is connected to the second write bit line WBLB;

Further, a gate of the fifth NMOS transistor MN5 is connected to the first storage node Q, a source of the fifth NMOS transistor MN5 is connected to a drain of the seventh NMOS transistor MN7, and the drain of the fifth NMOS transistor MN5 is connected to the second read bit line RBLA from the first leakage path Cell 1;

Further, a gate of the sixth NMOS transistor MN6 is connected to the first storage node Q, a source of the sixth NMOS transistor MN6 is connected to a drain of the eighth NMOS transistor MN8, and the drain of the sixth NMOS transistor MN6 is connected to the third read bit line RBLB from the second leakage path Cell 2;

Further, a gate of the seventh NMOS transistor MN7 is connected to the first read word line RWLA, and a source of the seventh NMOS transistor MN7 is connected to the first virtual ground line VGA;

further, a gate of the eighth NMOS transistor MN8 is connected to the second read wordline RWLB, and a source of the eighth NMOS transistor MN8 is connected to the second virtual ground line VGB.

3. Charge control module S3

For example, referring to fig. 1, the charge control module S3 includes a first capacitor C1, a second capacitor C2, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a third PMOS transistor MP3, and a diode D1;

the first end of the first capacitor C1 is connected to the first virtual ground line VGA and the positive electrode of the diode D1, and the second end of the first capacitor C1 is connected to the drain electrode of the ninth NMOS transistor MN9 and the source electrode of the third PMOS transistor MP3, respectively; the cathode of the diode D1 is respectively connected with the first read bit line RBL and the drain electrode of the eleventh NMOS tube MN 11; the source electrode of the eleventh NMOS tube MN11 is connected with the sense amplifier; the source electrode of the ninth NMOS tube MN9 is grounded; the drain electrode of the third PMOS MP3 is connected to the first end of the second capacitor C2 and the source electrode of the tenth NMOS MN10, respectively; the drain electrode of the tenth NMOS transistor MN10 is connected with the second virtual ground line VGB; the second end of the second capacitor C2 is grounded; the gates of the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, and the third PMOS transistor MP3 are all connected to the enable signal EN.

Specifically, in the leakage period, the switching signal SAEN of the sense amplifier is set to a high level, the enable signal EN is set to a high level, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are all turned on, and the third PMOS transistor MP3 is turned off; when the first read bit line RBL leaks electricity through the first virtual ground line VGA, the first capacitor C1 is charged; when the first read bit line RBL leaks electricity through the second virtual ground line VGB, the second capacitor C2 is charged; the first capacitor C1 and the second capacitor C2 are connected in parallel when being charged;

Specifically, after the leakage period is ended, the switching signal SAEN of the sense amplifier is set to a low level, the enable signal EN is set to a low level, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are all turned off, the third PMOS transistor MP3 is turned on, and the first capacitor C1 and the second capacitor C2 are discharged in series.

Specifically, the eleventh NMOS MN11 is configured to prevent the charging current from flowing back to the sense amplifier during the leakage period to cause erroneous output.

Specifically, when the first storage nodes Q of the two 10T-SRAM cells are both at a low level, if the data reading or the boolean operation is performed, the diode D1 may prevent a charge feedback path from being formed between the first virtual ground line VGA and the first read bit line RBL, so that unnecessary interference of the first capacitor C1 and the second capacitor C2 due to charge backflow may be avoided, thereby improving accuracy in the next data reading or boolean operation, and reducing potential loss of the first read bit line RBL.

4. Boolean operation module S4

For example, referring to fig. 1, the boolean operation module S4 includes the sense amplifier;

optionally, referring to fig. 3, the sense amplifier includes 3 NMOS transistors and 2 PMOS transistors;

Specifically, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 form a mutual coupling latch; a forward input node Q1 is arranged at the connection position of the fourth PMOS transistor MP4 and the twelfth NMOS transistor MN12, and the forward input node Q1 is connected with the first read bit line RBL; a reverse input node QB1 is arranged at the connection position of the fifth PMOS transistor MP5 and the thirteenth NMOS transistor MN13, and the reverse input node QB1 is connected with the reference voltage VREF; the gate of the fourteenth NMOS transistor MN14 is connected to the switching signal SAEN, the drain of the fourteenth NMOS transistor MN14 is connected to the source of the twelfth NMOS transistor MN12 and the source of the thirteenth NMOS transistor MN13, respectively, and the source of the fourteenth NMOS transistor MN14 is grounded.

5. Principle of operation

1. Boolean operation

Specifically, when the boolean operation NAND or NOR is performed, the precharge signal BLPR is set to a low level, the PMOS transistors P1 to P3 are all turned on, and the first read bit line RBL is precharged to a high level;

Further, the first read word line RWLA connected to one of the 10T-SRAM cells is set to a high level to turn on the corresponding seventh NMOS transistor MN7, and the 10T-SRAM cell is the first 10T-SRAM cell; setting the second read word line RWLB connected to another 10T-SRAM cell to a high level to turn on the corresponding eighth NMOS transistor MN8, where the 10T-SRAM cell is a second 10T-SRAM cell;

Further, the enable signal EN is set to a high level;

further, the switching signal SAEN of the sense amplifier is set to a high level.

Optionally, when performing the boolean operation NAND, setting the reference voltage VREF to 0.4V; when the boolean operation NOR is performed, the reference voltage VREF is set to 0.8V.

(1) Logic high level and logic high level

Specifically, when the boolean operation NAND or NOR is between a logic high level and a logic high level, the first storage nodes Q of the first 10T-SRAM cell and the second 10T-SRAM cell are both set to a high level 1V; the first 10T-SRAM cell, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 of the second 10T-SRAM cell are all conducted;

As can be seen, the first leakage path Cell1 of the first 10T-SRAM Cell is turned on and the second leakage path Cell2 is turned off, the first 10T-SRAM Cell is electrically leaked through the first virtual ground VGA; the first leakage path Cell1 of the second 10T-SRAM Cell is cut off and the second leakage path Cell2 is conducted, and the second 10T-SRAM Cell leaks electricity through the second virtual ground line VGB; the first capacitor C1 and the second capacitor C2 are charged in parallel, the potential of the first read bit line RBL drops rapidly to be close to 0V in the leakage period, and the output DO of the sense amplifier is at a low level.

(2) Logic low level and logic low level

Specifically, when the boolean operation NAND or NOR is between a logic low level and a logic low level, the first storage nodes Q of the first 10T-SRAM cell and the second 10T-SRAM cell are both set to a low level 0V; the first 10T-SRAM cell, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 of the second 10T-SRAM cell are all turned off;

As can be seen, the first leakage path Cell1 and the second leakage path Cell2 of the first 10T-SRAM Cell, the second 10T-SRAM Cell are all off; the first capacitor C1 and the second capacitor C2 are not charged, the first read bit line RBL is kept at a high potential, and the output DO of the sense amplifier is at a high level.

(3) Logic high level and logic low level

Optionally, when the boolean operation NAND or NOR is between a logic high level and a logic low level, the first storage node Q of the first 10T-SRAM cell is set to a high level 1V, and the first storage node Q of the second 10T-SRAM cell is set to a low level 0V; the fifth NMOS tube MN5 and the sixth NMOS tube MN6 of the first 10T-SRAM unit are both turned on, and the fifth NMOS tube MN5 and the sixth NMOS tube MN6 of the second 10T-SRAM unit are both turned off;

as can be seen, the first leakage path Cell1 of the first 10T-SRAM Cell is on and the second leakage path Cell2 is off, both the first leakage path Cell1 and the second leakage path Cell2 of the second 10T-SRAM Cell are off; the first capacitor C1 is charged and the second capacitor C2 is not charged, and the potential of the first read bit line RBL slowly drops to about 0.6V in the leakage period;

wherein, when the boolean operation NAND is performed, the output DO of the sense amplifier is at a high level; when the boolean operation NOR is performed, the output DO of the sense amplifier is low.

Similarly, if the first storage node Q of the first 10T-SRAM cell is set to a low level 0V, the first storage node Q of the second 10T-SRAM cell is set to a high level 1V; the first leakage path Cell1 and the second leakage path Cell2 of the first 10T-SRAM Cell are both off, the first leakage path Cell1 of the second 10T-SRAM Cell is off and the second leakage path Cell2 is on; the first capacitor C1 is not charged and the second capacitor C2 is charged, the potential of the first read bit line RBL slowly drops to about 0.6V in the leakage period; when the boolean operation NAND is performed, the output DO of the sense amplifier is at a high level; when the boolean operation NOR is performed, the output DO of the sense amplifier is low.

Specifically, after the leakage period is finished, the switching signal SAEN of the sense amplifier is set to a low level, the enabling signal EN is set to a low level, and the first capacitor C1 and the second capacitor C2 are discharged in series connection;

Further, when the potential of the first virtual ground line VGA is higher than the potential of the first read bit line RBL, the first read bit line RBL is charged by the first virtual ground line VGA; when the potential of the first virtual ground line VGA is equal to or less than the potential of the first read bit line RBL, the first read bit line RBL is held by the first virtual ground line VGA.

For example, please refer to fig. 4 for the logic of performing the boolean operation; the two independent first storage nodes Q respectively correspond to the inputs X and Y of the Boolean operation, the type of the Boolean operation is judged according to the reference voltage VREF, and a NAND or NOR result is output from the DO end of the sense amplifier;

for example, the distribution of the reference voltage VREF is shown in fig. 5;

Specifically, when the reference voltage VREF is NAND-VREF (here, 0.4V), if the final potential of the first read bit line RBL is greater than the NAND-VREF, NAND01, NAND10, NAND00 results are output; outputting a NAND11 result if the final potential of the first read bit line RBL is lower than the NAND-VREF;

Specifically, when the reference voltage VREF is NOR-VREF (here, 0.8V), if the final potential of the first read bit line RBL is lower than the NOR-VREF, the results of NOR01, NOR10, NOR11 are output; and outputting a NOR00 result if the final potential of the first read bit line RBL is higher than the NOR-VREF.

Further, the logic output waveform when performing the boolean operation is shown in fig. 6;

Specifically, when the boolean operation NAND is performed, the reference voltage VREF is set to 0.4V;

If the boolean operation NAND input is 00, the first read bit line RBL is kept at a potential, and the DO output logic is 1;

If the Boolean operation NAND input is 01 or 10, the first read bit line RBL potential slowly drops to a 0.4V-1V interval, and DO output logic is 1;

if the Boolean NAND input is 11, the first read bit line RBL potential drops rapidly below 0.4V and DO output logic is 0.

Specifically, when the boolean operation NOR is performed, the reference voltage VREF is set to 0.8V;

wherein, if the boolean operation NOR input is 00, the first read bit line RBL potential is maintained and DO output logic is 1;

if the Boolean operation NOR input is 01, 10 or 11, the first read bit line RBL potential is reduced to 0V-0.8V, and DO output logic is 0.

2. Data reading

Specifically, when the data is read, the precharge signal BLPR is set to a low level, the PMOS transistors P1 to P3 are all turned on, and the first read bit line RBL is precharged to a high level;

Further, the first read word line RWLA and the second read word line RWLB connected to one 10T-SRAM cell are both set to high level, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 of the 10T-SRAM cell are both turned on, and the 10T-SRAM cell is a third 10T-SRAM cell;

Further, the enable signal EN is set to a high level;

Specifically, when the first storage node Q is at a high level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 of the third 10T-SRAM Cell are turned on simultaneously, the first leakage path Cell1 and the second leakage path Cell2 of the third 10T-SRAM Cell are both turned on, the first capacitor C1 and the second capacitor C2 are both charged, and the first read bit line RBL is discharged; when the first storage node Q is at a low level, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 of the third 10T-SRAM Cell are turned off at the same time, the first leakage path Cell1 and the second leakage path Cell2 of the third 10T-SRAM Cell are both turned off, the first capacitor C1 and the second capacitor C2 are both not charged, and the first read bit line RBL is not discharged.

Further, the sense amplifier outputs the result of the data reading according to the discharge condition of the first read bit line RBL in a fixed period.

For example, in the process of performing the data reading or the boolean operation, the waveform of the first read bit line RBL potential regulated by the charge control module S3 is shown in fig. 7.

Specifically, the waveform of the first read bit line RBL potential is divided into 5 phases:

(1) A pre-charging stage: setting the precharge signal BLPR to a low level, the first read bit line RBL potential being maintained at a high level as the precharge module S1 is turned on;

(2) Charging phase (data read/boolean operation): setting a read word line RWL to a high level (the read word line RWL includes the first read word line RWLA and the second read word line RWLB, specifically, refer to "1, boolean operation" and "2, data reading" portions), setting the precharge signal BLPR to a high level to turn off the precharge module S1, setting the switching signal SAEN to a high level to operate the sense amplifier, and holding the enable signal EN to a high level to make the charge control module S3 enter a parallel charge charging mode, wherein the first read bit line RBL potential decreases as a leakage path is turned on (the leakage path includes the first leakage path Cell1 and the second leakage path Cell2, specifically, refer to "1, boolean operation" and "2, data reading" portions);

(3) Discharge phase: after the charging phase is finished, the read word line RWL is set to a low level, the switch signal SAEN is set to a low level to turn off the sense amplifier, and the enable signal EN is set to a low level to enable the charge control module S3 to enter a series charge discharging mode, at this time, the potential of the first read bit line RBL rises along with discharging of a capacitor (the capacitor includes the first capacitor C1 and the second capacitor C2, and in specific cases, please refer to the "1, boolean operation" and "2, data reading" parts);

(4) And (3) a holding stage: after the discharging phase is finished, the enable signal EN is set to be high level, the charge control module S3 is switched from the series charge discharging mode to the parallel charge charging mode to wait for the next data reading or Boolean operation, and the first read bit line RBL potential is simultaneously maintained;

(5) A new pre-charging stage: the precharge signal BLPR is set to a low level, and the first read bit line RBL potential continues to rise to a high level as the precharge module S1 is turned on.

It should be noted that the 5 stages shown in fig. 6 correspond to a case where the first storage node Q is at a high level when the data reading is performed, or at least one of the first storage nodes Q is at a high level when the boolean operation is performed; in other cases, the first read bit line RBL will always be high, leaving the level logic of the remaining signal unchanged.

3. Data writing

Specifically, when the data is written, the precharge signal BLPR is set to a low level, the PMOS transistors P1 to P3 are all turned on, the first write bit line WBL and the second write bit line WBLB are both precharged to a high level, and then the first write bit line WBL and the second write bit line WBLB are discharged based on the written data to form a pair of high and low levels; and setting the first write word line WWL to a high level, wherein the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both conducted, and the pair of high and low levels are written into the first storage node Q and the second storage node QB.

In summary, the present embodiment provides a low-power-consumption boolean operation circuit based on a 10T-SRAM cell, (1) performing in-memory computation based on a 10T-SRAM cell with separate read and write operations, and ensuring that storage nodes are not destroyed while implementing boolean operation of independent two units; (2) The Boolean operation is performed by controlling the reference voltage, and the leakage charges during data reading and Boolean operation are collected and released, so that leakage current loss is reduced, the reutilization of leakage power consumption is realized, and the method has the advantage of low power consumption.

Examples

The embodiment provides a chip, which is applied with the low-power-consumption Boolean operation circuit based on the 10T-SRAM unit.

For the description of the chip provided in this embodiment, refer to embodiment one, and this embodiment is not described herein again.

The embodiment provides a chip which has the same beneficial effects as the low-power-consumption Boolean operation circuit based on the 10T-SRAM unit.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims

1. A low-power Boolean operation circuit based on 10T-SRAM unit, characterized by comprising:

A precharge module, which is used to precharge the first read bit line RBL when data is read or Boolean operation is performed, and to precharge the first write bit line WBL and the second write bit line WBLB when data is written;

A storage module for storing data; the storage module comprises two 10T-SRAM units, the two 10T-SRAM units share the first read bit line RBL, the first write bit line WBL and the second write bit line WBLB, and both are read-write separation structures; the storage module is connected to the precharge module through the first write bit line WBL, the second write bit line WBLB and the first read bit line RBL;

A charge control module, which is used to control the enable signal EN to collect or release the leakage charge when performing the data reading or the Boolean operation; the charge control module is connected to the storage module through the first virtual ground line VGA, the second virtual ground line VGB and the first read bit line RBL;

A Boolean operation module, comprising a sensitive amplifier; the Boolean operation module controls the reference voltage of the sensitive amplifier for performing the Boolean operation; the Boolean operation includes NAND and NOR; the Boolean operation module is connected to the charge control module; wherein,

The two 10T-SRAM units each include 8 NMOS tubes and 2 PMOS tubes; the first NMOS tube, the second NMOS tube, the first PMOS tube, and the second PMOS tube constitute a mutually coupled latch, a first storage node is provided at the connection between the drain of the first PMOS tube and the source of the first NMOS tube, and a second storage node is provided at the connection between the drain of the second PMOS tube and the source of the second NMOS tube; the gate of the third NMOS tube is connected to the first write word line, the source of the third NMOS tube is connected to the drain of the first PMOS tube, and the drain of the third NMOS tube is connected to the first write bit line WBL; the gate of the fourth NMOS tube is connected to the first write word line, the source of the fourth NMOS tube is connected to the drain of the second PMOS tube, and the The drain of the fourth NMOS tube is connected to the second write bit line WBLB; the gate of the fifth NMOS tube is connected to the first storage node, the source of the fifth NMOS tube is connected to the drain of the seventh NMOS tube, and the drain of the fifth NMOS tube is connected to the second read bit line from the first leakage path; the gate of the sixth NMOS tube is connected to the first storage node, the source of the sixth NMOS tube is connected to the drain of the eighth NMOS tube, and the drain of the sixth NMOS tube is connected to the third read bit line from the second leakage path; the gate of the seventh NMOS tube is connected to the first read word line, and the source of the seventh NMOS tube is connected to the first virtual ground line VGA; the gate of the eighth NMOS tube is connected to the second read word line, and the source of the eighth NMOS tube is connected to the second virtual ground line VGB;

The charge control module includes a first capacitor, a second capacitor, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a third PMOS tube and a diode; the first end of the first capacitor is respectively connected to the first virtual ground line VGA and the positive electrode of the diode, and the second end of the first capacitor is respectively connected to the drain of the ninth NMOS tube and the source of the third PMOS tube; the negative electrode of the diode is respectively connected to the first read bit line RBL and the drain of the eleventh NMOS tube; the source of the eleventh NMOS tube is connected to the sensitive amplifier to prevent the charging current from flowing back to the sensitive amplifier to cause erroneous output during the leakage cycle; the source of the ninth NMOS tube is grounded; the drain of the third PMOS tube is respectively connected to the first end of the second capacitor and the source of the tenth NMOS tube; the drain of the tenth NMOS tube is connected to the second virtual ground line VGB; the second end of the second capacitor is grounded; the gates of the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube and the third PMOS tube are all connected to the enable signal EN;

During the leakage cycle, the switch signal of the sense amplifier is set to a high level, the enable signal EN is set to a high level, the ninth NMOS tube and the tenth NMOS tube are turned on, and the third PMOS tube is turned off; when the first read bit line RBL leaks through the first virtual ground line VGA, the first capacitor is charged; when the first read bit line RBL leaks through the second virtual ground line VGB, the second capacitor is charged; when the first capacitor and the second capacitor are both charged, they are connected in parallel; after the leakage cycle ends, the switch signal of the sense amplifier is set to a low level, the enable signal EN is set to a low level, the ninth NMOS tube and the tenth NMOS tube are turned off, the third PMOS tube is turned on, and the first capacitor and the second capacitor are discharged in series; wherein, when the potential of the first virtual ground line VGA is higher than the potential of the first read bit line RBL, the first virtual ground line VGA charges the first read bit line RBL; when the potential of the first virtual ground line VGA is equal to or less than the potential of the first read bit line RBL, the first virtual ground line VGA maintains the potential of the first read bit line RBL.

2. The low-power Boolean operation circuit based on the 10T-SRAM unit according to claim 1 is characterized in that, when the data is read, the first read bit line RBL is precharged to a high level, and the switch signal of the sensitive amplifier is set to a high level; the first read word line and the second read word line connected to one of the 10T-SRAM units are both set to a high level, and the seventh NMOS tube and the eighth NMOS tube of the 10T-SRAM unit are both turned on.

3. The low-power Boolean operation circuit based on 10T-SRAM unit according to claim 1 is characterized in that, when performing the Boolean operation NAND or NOR, the first read bit line RBL is pre-charged to a high level; the first read word line connected to one of the 10T-SRAM units is set to a high level to turn on the corresponding seventh NMOS tube, and the second read word line connected to another of the 10T-SRAM units is set to a high level to turn on the corresponding eighth NMOS tube; the switch signal of the sense amplifier is set to a high level; and the enable signal EN is set to a high level.

4. The low-power Boolean operation circuit based on 10T-SRAM unit according to claim 1 is characterized in that when performing the Boolean operation NAND, the reference voltage is set to 0.4V; when performing the Boolean operation NOR, the reference voltage is set to 0.8V; wherein,

When the Boolean operation NAND or NOR is between a logic high level and a logic high level, the first storage nodes of the two 10T-SRAM units are both set to a high level of 1V;

When the Boolean operation NAND or NOR is between a logic low level and a logic low level, the first storage nodes of the two 10T-SRAM units are both set to a low level of 0V;

When the Boolean operation NAND or NOR is between a logic high level and a logic low level, the first storage node of one of the 10T-SRAM cells is set to a high level of 1V, and the first storage node of the other 10T-SRAM cell is set to a low level of 0V.

5. The low-power Boolean operation circuit based on the 10T-SRAM unit according to claim 1 is characterized in that, when the data is written, the first write bit line WBL and the second write bit line WBLB are pre-charged to a high level, and then the first write bit line WBL and the second write bit line WBLB are discharged based on the written data to form a pair of high and low levels; the first write word line is set to a high level, the third NMOS tube and the fourth NMOS tube are turned on, and the pair of high and low levels are written into the first storage node and the second storage node.

6. A chip, characterized in that it uses the low-power Boolean operation circuit based on 10T-SRAM unit as described in any one of claims 1 to 5.