CN115810374A - Memory circuit and memory computing circuit with BCAM addressing and logic operation functions - Google Patents

Abstract

The invention relates to the technical field of static random access memory, in particular to a storage circuit and an in-memory calculation circuit with BCAM addressing and logic operation functions. The storage circuit includes NMOS transistors N1-N5 and PMOS transistors P0-P1; among them, N1-N4 and P0-P1 form a 6T-SRAM unit, and N5 is connected between two MOS transistors corresponding to any storage node of the 6T-SRAM unit , and the gate of N5 is controlled by the control signal line EN. Compared with the traditional 6T-SRAM, the storage circuit designed by the present invention adds a transistor for isolating the read port from the storage node, thereby improving the read damage problem of the 6T structure. At the same time, compared with the traditional 8T-SRAM with read-write separation, it has one less transistor and has a greater advantage in area.

Description

Storage circuits, in-memory computing circuits with BCAM addressing and logical operation functions

technical field

The invention relates to the technical field of static random access memory, in particular to a storage circuit, an in-memory computing circuit based on the storage circuit with BCAM addressing and logic operation functions, and a storage chip based on the storage circuit.

Background technique

In order to overcome the computing limitations brought by the traditional von Neumann architecture, the concept of Computing In Memory (CIM) was proposed. In-memory computing does not need to frequently transfer data from the memory to the processor, and directly integrates the calculation part into the storage array to perform calculations, which not only reduces the transmission of intermediate data, but also reduces the workload of the processor; another aspect of in-memory computing A significant advantage is the ability to perform multi-row reading. Through multi-row reading technology, the discharge amount of the bit line has a linear relationship with the stored data. Use the bit line voltage to complete some simple logic operations, thereby reducing the number of accesses to the memory, thus reducing energy consumption to a certain extent and increasing data throughput. As a memory widely used in the cache field, SRAM occupies an increasing proportion in chip area and power consumption, and the research on SRAM-based in-memory computing has become particularly important.

A conventional 6T-SRAM has cross-coupled inverters and two access transistors for read and write operations. During a read operation, bit lines BL and BLB are precharged to VDD, and word line WL is set to VDD for reading. The read path of 6T-SRAM goes through the storage node to ground (GND), which usually causes read disturb. The key technology of in-memory computing is the multi-row read technology, that is, during the read operation, multiple rows are turned on at the same time instead of one row of word lines; while the traditional 6T-SRAM can only read one row of data during a data read process.

In order to solve the problem of read interference, an 8T-SRAM structure with read coupling is proposed. This structure has the structural advantages of read-write separation. There are also 9T-SRAM with read-write separation, and even 10T-SRAM units are used to realize in-memory computing. Compared with the traditional 6T-SRAM, although these structures can improve the read disturbance problem, the area also increases accordingly.

Contents of the invention

Based on this, it is necessary to address the problem of improving read disturbance at the expense of the area of the existing SRAM unit, and provide a storage circuit, an in-memory computing circuit with BCAM addressing and logic operation functions based on the storage circuit, and a storage circuit-based memory chips.

To achieve the above object, the present invention adopts the following technical solutions:

A storage circuit includes NMOS transistors N1-N5 and PMOS transistors P0-P1. Among them, N1-N4 and P0-P1 form a 6T-SRAM unit, and N5 is connected between two MOS transistors corresponding to any storage node of the 6T-SRAM unit, and the gate of N5 is controlled by the control signal line EN. The specific connection method of the storage circuit is as follows:

The gate of N1 is electrically connected to the drain of N2, the drain of N4, and the gate of P1. The drain of N1 is electrically connected to the drain of N3 and the source of N5. The source of N1 and the source of N2 are connected to GND. The gate of P2 is electrically connected to the drain of P1, the gate of N2, and the drain of N5. The drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1. The source of P1 and the source of P2 are connected to VDD. The gate of N3 is connected to the right word line WLR, the gate of N4 is connected to the left word line WLL, and the gate of N5 is electrically connected to the external control signal line EN. The source of N3 is connected to the bit line BLB, and the source of N4 is connected to the bit line BL.

Wherein, P2 and N2 form an inverter, and N3 and N4 form transmission tubes of the storage circuit. The storage node Q is connected to the bit line BL through N4, and the storage node QB is connected to the bit line BLB through N5 and N3.

Further, the storage circuit implementing the SRAM mode includes holding operation, writing operation and reading operation. When the storage circuit performs the hold operation, the control signal line EN maintains a high level, the left word line WLL and the right word line WLR maintain a low level, and the latch structure formed by P1, P2, N1, N2, and N5 controls the storage nodes Q and QB. The stored data is latched. When the storage circuit performs a write operation, the control signal line EN maintains a high level, the left word line WLL and the right word line WLR are pulled to a high level, and at the same time, the data to be written is loaded onto the write bit line. When the storage circuit performs a read operation, the bit line BLB is precharged to a high level, the control signal line EN is at a low level, the left word line WLL is pulled low, and the right word line WLR is kept at a high level, and read through the sense amplifier SA result.

The invention also relates to an in-memory computing circuit with BCAM addressing and logic operation functions, which is composed of a plurality of identical memory cells in the form of an N*M array. Wherein, N is the number of rows of the storage unit, and M is the number of columns of the storage unit. Each row of memory cells shares a left word line WLL and a right word line WLR. Each column of memory cells shares bit lines BL, BLB.

The storage unit adopts the circuit structure of the aforementioned storage circuit, and realizes the complete functions of the circuit structure.

Further, all the bit lines BL, BLB are connected to the sense amplifiers in a one-to-one correspondence. The bit line BL or BLB in each column of memory cells is respectively used as one input of a sense amplifier, and the other input of the sense amplifier is a reference voltage. When the level of BL or BLB is higher than the reference voltage, the sense amplifier outputs a high level, otherwise it outputs a low level.

Further, the bit lines BL and BLB of each column of memory cells are connected to an AND gate through a single-ended sense amplifier. The outputs of the two single-ended sense amplifiers are respectively used as two inputs of an AND gate. When the outputs of the two sense amplifiers are both high, the AND gate outputs a high level, otherwise it outputs a low level.

Further, when the in-memory calculation circuit executes the in-memory Boolean logic operation, the output terminal of the sense amplifier connected to the bit line BLB serves as the output terminal of the result of the operation. When the in-memory calculation circuit executes the BCAM operation, the output end of the AND gate is used as the output end of the result of the operation. When the in-memory calculation circuit executes the multiplication operation, the discharge amount of the bit line BLB is the result of the multiplication operation. Further, the method of implementing the Boolean logic operation in the memory by the calculation circuit in the memory is as follows: keep the left word line WLL and the control signal line EN of the same row of memory cells at low level, and set the The right word line WLR is set to high level, and the other word lines are set to low level. The sense amplifier compares the voltage on the bit line BLB with a reference voltage and then outputs the corresponding Boolean logic operation result in the memory.

Further, the method of realizing the BCAM operation by the calculation circuit in the memory is as follows: keep the control signal line EN of the memory cells of the same column at a low level; pass the voltage signal corresponding to the search data and its opposite signal through the left word line WLL and the right word line respectively WLR is input to the storage unit that pre-stores the data to be searched; the voltage signal output of the bit line BL and BLB representing the operation result is output through two single-ended sense amplifiers and an AND gate; the output of the AND gate outputs a high level, indicating the search data Match the data to be searched; the output terminal of the AND gate outputs a low level, indicating that the search data does not match the data to be searched.

Further, the method of implementing the multiplication operation by the in-memory computing circuit is as follows:

Keep the control signal line EN and the left word line WLL of the same column of memory cells at low level, and input the voltage signal corresponding to the multiplicand to the memory cell pre-stored with the multiplier through the right word line WLR, according to the discharge capacity of the bit line BLB to get the desired multiplication result.

The present invention also relates to a storage chip, which is packaged by the aforementioned storage circuit. The pins of the memory chip include:

The ground pin is connected to the sources of the PMOS transistors P1 and P2.

The power supply pin is connected to the sources of the NMOS transistors N1 and N2.

The first pin is connected to the source of the NMOS transistor N4.

The second pin is connected to the source of the NMOS transistor N3.

The third pin is connected to the gate of the NMOS transistor N4.

The fourth pin is connected to the gate of the NMOS transistor N3.

The technical scheme provided by the invention has the following beneficial effects:

1. Compared with the traditional 6T-SRAM, the storage circuit designed by the present invention adds a transistor for isolating the read port from the storage node, thereby improving the read damage problem of the 6T structure. At the same time, compared with the traditional 8T-SRAM that separates read and write, it has one less transistor and has a greater advantage in area.

2. The in-memory calculation circuit of the array distribution designed by the present invention can carry out normal maintenance, read and write SRAM mode, and can also perform simple Boolean logic operations, BCAM addressing operations and multiplication operations, thereby meeting various computing needs .

Description of drawings

Fig. 1 is the circuit structural diagram of the memory circuit of embodiment 1 of the present invention;

FIG. 2 is a schematic circuit diagram of AND and NAND operations performed by two rows of memory cells in Embodiment 2 of the present invention;

Fig. 3 is the simulation result figure based on the AND and NAND operation of Fig. 2;

4 is a schematic circuit diagram of OR and NOR operations performed by two rows of memory cells in Embodiment 2 of the present invention;

Fig. 5 is the simulation result figure based on the OR and OR non-operation of Fig. 4;

FIG. 6 is a schematic circuit diagram of BCAM addressing with 4×4 memory cells as an example in Embodiment 2 of the present invention;

Fig. 7 is the simulation result figure based on the BCAM addressing of Fig. 6;

Fig. 8 is the circuit structural diagram of the execution 4bit * 1bit binary multiplication operation of embodiment 2 of the present invention;

Fig. 9 is a simulation result diagram based on the execution of 4bit * 1bit binary multiplication in Fig. 8;

FIG. 10 is a linearity variation diagram of the 4bit×1bit binary multiplication operation result based on FIG. 8 .

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Example 1

Please refer to FIG. 1 . FIG. 1 shows a storage circuit introduced in this embodiment, including NMOS transistors N1 - N5 and PMOS transistors P0 - P1 . Among them, N1-N4 and P0-P1 form a 6T-SRAM unit, and N5 is connected between two MOS transistors corresponding to any storage node of the 6T-SRAM unit, and the gate of N5 is controlled by the control signal line EN. The specific connection method of the storage circuit is as follows:

The drain of N2 is electrically connected to the gate of N1, and the source of N2 is electrically connected to the source of N1. The gate of N3 is electrically connected to the right word line WLR, the drain of N3 is electrically connected to the drain of N1, and the source of N3 is electrically connected to the bit line BLB. The gate of N4 is electrically connected to the right word line WLL, the drain of N4 is electrically connected to the drain of N2 and the gate of N1, and the source of N4 is electrically connected to the bit line BL. The gate of N5 is electrically connected to the external control signal EN, the drain of N5 is electrically connected to the gate of N2, and the source of N5 is electrically connected to the drain of N1 and the drain of N3. The gate of P1 is electrically connected to the gate of N1, the drain of N2, and the drain of N4, and the drain of P1 is electrically connected to the gate of N2 and the drain of N5. The gate of P2 is electrically connected to the gate of N2 and the drain of N5, the drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1 is electrically connected to the source of P1 and the gate of P2 source electrical connection.

An NMOS transistor N5 is added between the drain of P1 and the drain of N1 in the right half of the circuit. The gate of N5 is controlled by the external control signal line EN, and P2 and N2 in the left half form an inverter. When the N5 transistor When turned on, the left and right sides latch the data stored in the storage nodes Q and QB, the sources of the transistors P1 and P2 are electrically connected to VDD, and the storage nodes Q and QB are connected to the power supply, and the source electrodes of the transistors N1 and N2 are electrically connected to VDD. Connect to GND, open storage nodes Q, QB to ground path. When the N5 tube is turned off, the transistor P1 and the transistor N1 are disconnected. At this time, the gate of N1 is controlled by Q, and the drain of N1 is no longer directly affected by QB. The transistor N3 is controlled by the word line WLR, and the transistor N1 and the transistor N3 is connected to the right bit line BLB. When both transistors N1 and N3 are turned on, the right bit line BLB can form a path to the ground. By controlling the conduction degree of transistors N1 and N3, the discharge amount of the right bit line BLB can be controlled. This principle enables different computing modes.

The storage node Q is connected to the bit line BL through the transistor N4, and the storage node QB is connected to the bit line BLB through the transistors N5 and N3. , Right word line WLR control.

The circuit of this embodiment is a 7T-SRAM composed of 7 transistors. Compared with the traditional 6T-SRAM, since the read port is isolated from the storage node, the read corruption problem of the 6T structure is improved. Compared with the traditional 8T-SRAM that separates read and write, it has one less transistor and has a greater advantage in area.

The specific operation of the storage circuit of this embodiment in the SRAM mode will be described below. In SRAM mode, including hold operation, write operation and read operation, the specific operation steps are as follows:

(1) Hold mode

During the data holding period, the external control signal line EN maintains a high level, the left word line WLL and the right word line WLR maintain a low level, the NMOS transistors N3 and N4 are turned off, and N5 is turned on. The latch structure formed by the PMOS transistors P1, P2 and the NMOS transistors N1, N2, N5 latches the values of the storage nodes Q, QB, and the changes of the bit lines BL, BLB will not affect the storage nodes Q, QB.

(2) Write operation

During the write operation, the external control signal line EN, the left word line WLL, and the right word line WLR maintain a high level, and the NMOS transistors N3, N4, and N5 are all turned on, and the data to be written is loaded onto the write bit line.

Assume that the storage node Q is at high level and QB is at low level before the write operation, that is, the stored data is "1", and when writing data "0", load the data "0" to be written on the write bit line , that is, BL is low level and BLB is high level. BL pulls down storage node Q through NMOS transistor N2, BLB pulls up storage node QB through PMOS transistor P1, the feedback mechanism of the latch structure is broken, and data "0" is written into the storage circuit.

Assume that the storage node Q is low level and QB is high level before the write operation, that is, the stored data is "0", and when writing data "1", load the data "1" to be written on the write bit line , that is, BL is high level, and BLB is low level. BL pulls up storage node Q through P2, BLB pulls down storage node QB through N1, the feedback mechanism of the latch structure is broken, and data "1" is written into the storage circuit.

(3) Read operation

During the read operation, the external control signal line EN, the left word line WLL are at low level, and the right word line WLR is at high level, the NMOS transistors N4 and N5 are turned off, and the NMOS transistor N3 is turned on, that is, the unilateral read operation is performed.

Assuming that before the read operation, the storage node Q is at a high level and QB is at a low level, that is, the stored data is "1", at the beginning of the read operation, the bit line BLB is precharged to a high level, and the storage node Q controls the gate of N1 , when Q is at a high level, N1 is turned on, the bit line BLB is discharged to a low level through the NMOS transistors N3 and N1, and the operation of reading "1" is completed through the sense amplifier SA.

Assuming that the storage node Q is at low level and QB is at high level, that is, when the stored data Q is "0", at the beginning of the read operation, the bit line BLB is also precharged to high level, and the storage node Q is at low level. The NMOS transistor N1 is controlled to be turned off, the bit line BLB cannot be discharged, and remains at a high level, and the operation of reading "0" is completed through the sense amplifier SA.

Based on this, the truth table for implementing the SRAM mode is shown in the following table, where L stands for low level, H stands for high level, Read stands for read operation, Write stands for write operation, and Hold stands for hold state.

Table 1: SRAM truth table

Therefore, the storage circuit of this embodiment can not only improve the problem of read disturbance when reading the data stored inside the storage circuit through the bit line by separating the read port from the storage node Q. At the same time, only one transistor is added. Compared with 8T-SRAM, 9T-SRAM, and 10T-SRAM, the area occupied is reduced on the basis of improving read disturbance, so compared with the existing structure for improving read disturbance, it has good performance. area advantage.

Example 2

This embodiment introduces an in-memory computing circuit with BCAM addressing and logical operation functions, which consists of a plurality of identical storage units in the form of an N×M array; where N is the number of rows of storage units, and M is the number of storage units. The number of columns of cells; each row of memory cells shares the left word line WLL and the right word line WLR; each column of memory cells shares the bit lines BL and BLB; the memory cells adopt the circuit structure of the aforementioned memory circuit and realize the complete functions of the circuit structure .

The number of sense amplifiers is the same as the number of bit lines, and the bit line BL or BLB in each column of memory cells is used as one input of a sense amplifier, and the other input reference voltage of the sense amplifier; when the level of BL or BLB is higher than the reference voltage , the sensitive amplifier outputs a high level, otherwise it outputs a low level. The number of AND gates is half of the number of memory cell columns, and the output terminals of the two sense amplifiers in each column of memory cells are respectively used as two inputs of an AND gate; when the outputs of the two sense amplifiers are both high, the AND gate Output high level, otherwise output low level.

Based on the aforementioned circuit, this embodiment can not only realize the SRAM mode function, but also realize Boolean logic operation, BCAM addressing and multiplication operation in the memory based on the cooperation between different columns and rows. The implementation of these operations will be described in detail below.

1. In-memory Boolean logic operations

When performing the Boolean logic operation in the memory, the left word line WLL and the control signal line EN of the memory cells in the same column are kept at a low level, and the right word line WLR of the memory cells required to participate in the Boolean logic operation in the memory is set to a high level, The rest of the word lines are set to low level; the voltage on the bit line BLB is compared with a reference voltage through the sense amplifier SA, and then the corresponding internal Boolean logic operation results are output.

As shown in Figure 2, taking the logical AND and NAND of two 1-bit stored data as an example, it introduces the function of storing data between two rows in the same column to realize AND and NAND.

The left word line WLL and the external control signal line EN of the two memory cells are always at low potential, so the NMOS transistors N4 and N5 are always in the off state, and the memory cells of the two rows are respectively marked as A and B, and the word line of row A It is marked as WLL0 and WLR0, the word line of row B is marked as WLL1 and WLR1, and A and B share bit lines BL and BLB. Whether the right word line WLR is turned on determines whether the row participates in the operation, and a sense amplifier SA is prepared for it. The other end of SA is connected to the reference voltage VREF1. The sense amplifier compares the voltage of the bit line BLB with the reference voltage VREF1, and then outputs A and B The results of logical AND and NAND operations.

The bit line BLB is precharged to a high level, and the right word lines WLR0 and WLR1 of the two cells are turned on at the same time, that is, WLR0 and WLR1 are at a high level. When the data stored in the cell is "1", that is, when Q is high and QB is low, a path to ground is formed between the bit line BLB and GND, and the charge on BLB flows to GND. At this time, the bit line BLB Discharge, when the stored data of A or B is 1, the discharge speed of the bit line BLB is the same. When the stored data of A and B are both 1, the discharge speed of BLB is faster, and the stored data of the two cells are both "1" and When only one cell stores data as "1", the discharge speed of the bit line is different, and the reference voltage VREF1 of the sense amplifier SA is set, that is, the reference voltage VREF1 of the sense amplifier SA is at the same time as the bit line voltage after two cells are discharged and one cell is discharged Between the subsequent bit line voltages, if VBLB>VREF1, at least one of the stored data of A and B is “0” or both are “0”. If VBLB<VREF1, the data stored in A and B are both "1".

Since the principle of the AND operation is to output a high level only when both operands are high, and the non-operation is to output a low level only when both operands are high. Therefore, the simulation experiment is carried out in this embodiment, and it can be seen from the simulation results in Fig. 3 that the output of the sense amplifier is "0" if and only when both the upper and lower units are discharged, and the output is "1" in other cases, and the outputs A and B The output of the other end of the sense amplifier SA is the opposite of the output of this end, and the result of the AND operation of A and B phases is output. The principle of AND and NAND operations between multiple rows is the same as the operation principle between two rows.

As shown in Figure 4, the logical OR and NOR of two 1-bit stored data is taken as an example to introduce the OR and NOR function of storing data between two rows in the same column.

The setting conditions for A and B to perform AND or NOT operations are the same as those for AND and NOR operations. The difference is that when A and B perform OR and OR NOT operations, one end of SA is connected to the bit line BLB, and the other end is connected to the reference voltage VREF2. SA compares the voltage of the bit line BLB with the reference voltage VREF2, and outputs the result of the logical OR and NOR operation of A and B.

First precharge the bit line BLB to a high level, and turn on the right word lines WLR0 and WLR1 of the two cells at the same time. When any or all of the stored data in the cell is "1", that is, when Q is 1 and QB is 0, the bit line A path to ground is formed between BLB and GND, charges on the bit line BLB flow to GND, and the bit line BLB discharges. Judgment is made by using the principle that the bit line BLB is not discharged when the stored data in row A and row B are both low level and the bit line BLB is discharged when one of the stored data in row A or B is high level. The SA reference voltage VREF2 is between the bit line voltage without discharge and the bit line voltage after a cell discharge. If VBLB>VREF2, then the data stored in A and B are both "0"; if VBLB<VREF2, then at least one of the stored data in A or B is "1" or both are "1".

Because the principle of the OR operation is to output a low level only when both operands are low, and the principle of NOR is to output a high level only when the two operands are low, so this embodiment performs From the simulation experiment, it can be seen from the simulation results in Figure 5 that only when the storage data of the two cells are "0", that is, when the right bit line BLB in the two cells is not discharged to the ground, BLB remains high, and SA The output result of SA is "1", and any cell stores data "1", that is, when the right bit line BLB in any cell is discharged to the ground, the output result of SA is "0", and the reference voltage VREF2 of SA at this time is located at bit Between the undischarged line voltage and the bit line voltage after a cell is discharged, one end of the sense amplifier SA outputs the NOR operation result of A and B, and the other end outputs the opposite, and outputs the OR operation result of A and B phases. The OR and OR NOT operation between multiple rows works in the same way as the operation between two rows.

Based on this, the in-memory calculation circuit of this embodiment can realize logical operation AND and NAND operation, OR and NOR operation; it should be emphasized that the output of the two output terminals of the sense amplifier is the opposite result, and the bit line BLB The output terminal on the same side as the connected input terminal outputs the result of NAND or NOR, and the output terminal on the same side as the input terminal connected to the reference voltage outputs the result of AND or OR.

Realize the truth table of logical AND and NAND, OR and NOR mode between two rows in the same column in Boolean logic operations as shown in the following table, where A represents the stored data in row A, and B represents the stored data in row B. L stands for low level and H stands for high level.

Table 2: In-memory Boolean logic operation truth table

Two, BCAM addressing operation

Keep the control signal line EN of the memory cell in the same row at low level; input the voltage signal corresponding to the search data and its opposite signal through the left word line WLL and the right word line WLR respectively to the memory cell with pre-stored data to be searched; its matching and No result is represented by two single-ended sense amplifiers SA and an AND gate output. The output terminal of the AND gate outputs a high level, indicating a match; the output terminal of the AND gate outputs a low level, indicating a mismatch.

As shown in Figure 6, in the BCAM operation mode, the external control signal line EN is always at low level, that is, the NMOS transistor N5 is in the off state, the binary data to be searched is stored in the internal Q node of the storage unit, and the search line is the left word line WLL, the left word line WLL is the high level or low level corresponding to the binary data of the search data, the right word line WLR is the high level or low level corresponding to the inverse code of the binary data of the search data, and the data is When the data is "1", the corresponding word line is set to high level, when the data is "0", the corresponding word line is set to low level, the lower ends of the left and right bit lines BL and BLB are each connected to a sense amplifier SA, and the output of the two SAs Connected to an AND gate, the output of the AND gate indicates whether there is a match. Before the data search, the storage unit stores the binary data to be searched, the left and right bit lines BL and BLB are precharged to high level, and the left and right word lines are respectively set to high level or low level according to the search data, and then according to the data to be searched and Whether the search data matches or not controls whether the bit line is discharged. When it matches, it does not discharge, otherwise it discharges. Only when the left and right bit lines of the column are not discharged, the output of the sense amplifier SA is high, and the output is high after passing through the AND gate. The level indicates a match, otherwise, the output of the AND gate is a low level, indicating a mismatch.

The data comparison process is analyzed below. When the search data is "0", the left word line WLL is at low level, the NMOS transistor N4 is turned off, BL cannot be discharged, and remains at high level. At this time, the right word line WLR is at high level , the NMOS transistor N3 is turned on, assuming that the storage node Q is "0", the gate acting on the NMOS transistor N1 controls N1 to turn off, the BLB discharge path is pinched off, and the BLB does not discharge, indicating that the bit lines BL and BLB are at this time No discharge is performed, and the data of this cell matches; assuming that the storage node Q is "1", the gate acting on the NMOS transistor N1 controls N1 to be turned on, and the BLB is discharged, then the bit line BL is not discharged at this time, and the bit line BLB is discharged , the cell data does not match. Similarly, when the search data is "1", the right word line WLR is at low level, the NMOS transistor N3 is turned off, BLB cannot be discharged and remains at high level, at this time the left word line WLL is at high level, and the NMOS transistor N3 N3 is turned on, assuming that the storage node Q is "0" and the storage node QB is "1", the gate acting on N2 controls the NMOS transistor N2 to turn on, and BL discharges, then the bit line BLB does not discharge at this time, and the bit line BL discharges, the cell data does not match, assuming that the storage node Q is "1" and the storage node QB is "0", the gate acting on N2 controls the NMOS transistor N2 to turn off, and BL does not discharge, then the bit line at this time BL and BLB are not discharged, and the data of this unit matches.

In combination with Figure 6, taking 4×4 memory cells to perform BCAM operations as an example, the four pairs of word lines from the first row to the fourth row are respectively marked as WLL0, WLR0; WLL1, WLR1; WLL2, WLR2; WLL3, WLR3, the first The four pairs of bit lines from columns 1 to 4 are respectively marked as BL0, BLB0; BL1, BLB1; BL2, BLB2; BL3, BLB3. In order to show the technical solution provided by the present invention and its technical effects more clearly, take the column search of four-bit binary data "0011" as an example, that is, the searched data is "0011", and "0" is low level , "1" is high level. Therefore, the left word lines WLL0, WLL1, WLL2, and WLL3 are respectively placed at low level, low level, high level, and high level, and the right word lines WLR0, WLR1, WLR2, and WLR3 are respectively placed at high level and high level. , low level, low level. There are four columns in the array, and the data stored in each column from left to right is "0111", "0011", "1011", and "1101".

According to the above analysis, it can be seen that the data stored in the first column is "0111", although the data stored in the second row is "1", but because the left word line WLL1 is at low level and is in an off state, the left bit line BL0 is not discharged , SA outputs "1", but the state of the right word line WLR1 is opposite to that of the left word line WLL1, so the right word line WLR1 is at high level, and the transmission tube N3 is turned on. At this time, BLB0 discharges, and SA outputs "0". The result of the AND gate output is "0", so the stored data in the first column does not match the search data.

The data stored in the second column is "0011". At this time, the bit lines BL1 and BLB1 are not discharged, and the two SA outputs are both "1", and "1" is output through the AND gate, so the second column matches the search data.

The data stored in the third column is "1011", although the data "1" stored in the first row does not match the search data, but because the left word line WLL0 is low and in the off state, the left bit line BL2 is not discharged , SA outputs "1", but the state of the right word line WLR0 is opposite to that of the left word line WLL0. At this time, WLR0 is at high level, the transmission transistor N3 is turned on, the right bit line BLB2 is discharged, and SA outputs "0". The result is "0" after being output by the AND gate, so the stored data in the third column does not match the search data.

The data stored in the fourth column is "1101", and the data stored in the first row, the second row, and the third row are different from the search data, but because the left word lines WLL0 and WLL1 of the first row and the second row are low Level, transmission tube N4 is not turned on, does not affect the left bit line BL3, the third line left word line WLL2 is high level, transmission tube N4 is turned on, BL3 discharges, SA outputs "0", right word lines WLR0, WLR1 , WLR2 is opposite to the left word line WLL0, WLL1, WLL2, the transmission transistor N4 of the first row and the second row is turned on, the right bit line BLB3 is discharged, SA outputs "0", and the results of the two SAs are output by the AND gate. "0", so the fourth column store data does not match the search data.

Eventually it can be known that only the second column matches the search data. As can be seen from the simulation results of BCAM in Figure 7, when the four cell data in a column are all matched, the left and right bit lines BL and BLB are not discharged to maintain a high level, then BL and BLB pass through two sense amplifiers and an AND gate Then output a high level, indicating that the search data matches the data to be searched; on the contrary, when there are units with unmatched data in the four cells in a column, one of the left and right bit lines BL and BLB must be discharged, and then BL And BLB outputs low level after passing through two sensitive amplifiers and an AND gate, indicating that the search data does not match the data to be searched.

3. Multiplication

The left word line WLL and the external control signal EN keep low level, the multiplicand is represented by different voltages working on the right word line WLR, the multiplier is stored inside the memory cell, and the multiplication output result is discharged through the right bit line BLB amount to express. Each storage unit completes 2bit×1bit multiplication in each calculation stage, and the 2bit multiplicand acts on the right word line WLR, which is realized by converting the multiplicand into a word line voltage, and the multiplier acts on the inside of the storage unit.

Referring to FIG. 8 , the method of realizing this function in this embodiment is described by taking the realization of 4bit×1bit binary multiplication as an example. To realize 4bit×1bit binary multiplication operation, only two units that realize 2bit×1bit binary multiplication operation need to be discharged through a bit line.

First, set a single storage unit to realize the binary multiplication of 2-bit multiplicand and 1-bit multiplier. The 2-bit multiplicands are "00", "01", "10", and "11", which correspond to the four WLRs respectively. Voltage 0, V _WLR1 , V _WLR2 , V _WLR3 , different voltages of the right word line act on the gate of the NMOS transistor N3, at the same time, different gate voltages control the conduction degree of the NMOS to be different, and the current flowing through it is also different. In this way, different weighted multiplicands are distinguished, and the binary multipliers are "0" and "1", which are stored in the internal node Q of the storage unit. First, precharge the bit line BLB. When the binary multiplier is "0", no matter how much the gate voltage of the transistor N3 is, the discharge amount on the bit line BLB is always zero. When the binary multiplier is "1", the control The NMOS transistor N1 is turned on, and the discharge amount of the bit line BLB at this time depends on the magnitude of the gate voltage of the control transistor N3, so as to achieve the purpose of distinguishing 2bit×1bit binary multiplication results.

The truth table for realizing 2bit×1bit binary multiplication operation is shown in the following table, where X represents any 2bit data and its corresponding word line voltage.

Table 3: 2bit×1bit binary multiplication result truth table

Two units that realize 2bit×1bit binary multiplication operation realize 4bit×1bit binary multiplication through a bit line discharge, and the distinction between high 2bit and low 2bit can be achieved through transistor size weighting technology, capacitor array weighting technology, pulse number/height/width Weighting technology and other technologies to achieve. In this explanation, pulse width modulation technology is chosen as an example. Other technologies are similar to pulse width modulation technology. The bit line BLB is precharged to a high level, and different weighted currents are obtained according to different multiplicands and multipliers. .

The truth table for realizing 4bit×1bit binary multiplication operation is shown in the following table, where X represents any 4bit data.

Table 4: 4bit×1bit binary multiplication result truth table

Figure 9 is a schematic diagram of the result of the 4bit×1bit binary multiplication operation. A calculation capacitor is externally connected to the bit line BLB to convert the weighted current into a weighted voltage, and perform analog-to-digital conversion through the ADC to obtain a binary number representing the result of the 4bit×1bit binary multiplication operation. . Therefore, the in-memory computing circuit of this embodiment can obtain 16 multiplication results of 4bit×1bit binary multiplication operations when performing multiplication operations.

The method of the present invention to distinguish the multiplication results is to distinguish the different discharge amounts of the bit lines, and the linearity between the different discharge amounts of the bit lines can be measured by the change of the bit line voltage and the integral nonlinearity (INL: Integralnonlinearity). Figure 10 shows the measured INL value. It can be seen from Figure 9 that the linearity is the worst when the multiplication result is 9. At this time, the INL value is 0.62LSB, but the INL value is still small and the linearity is better. Therefore, this embodiment can effectively implement a 4bit×1bit binary multiplication operation.

To sum up, the in-memory calculation circuit of this embodiment not only has the same effect as that of Embodiment 1, but also can perform operations on the entire array in the array formed on the basis of Embodiment 1. In addition, simple Boolean logic operations, BCAM addressing operations, and 4bit×1bit binary multiplication operations can be performed to meet various operations.

Example 3

This embodiment introduces a memory chip, which is packaged by the aforementioned memory circuit. The pins of the memory chip include: a ground pin, which is connected to the sources of the PMOS transistors P1 and P2; a power pin, which is connected to the sources of the NMOS transistors N1 and N2; a first pin, which is connected to the source electrodes of the NMOS transistor N4 The source is connected; the second pin is connected with the source of the NMOS transistor N3; the third pin is connected with the gate of the NMOS transistor N4; the fourth pin is connected with the gate of the NMOS transistor N3.

The mode of packaging the storage circuit into a chip is easier for those skilled in the art to use, and is also conducive to the promotion and use of the storage circuit.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above examples only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the scope of the patent for the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. A storage circuit, characterized in that it comprises NMOS transistors N1～N5 and PMOS transistors P0～P1; wherein, N1～N4 and P0～P1 form a 6T-SRAM unit, and N5 is connected to any of the 6T-SRAM units Between two MOS transistors corresponding to a storage node, and the gate of N5 is controlled by the control signal line EN; the specific connection method of the storage circuit is as follows: The gate of N1 is electrically connected to the drain of N2, the drain of N4, and the gate of P1; the drain of N1 is electrically connected to the drain of N3 and the source of N5; the source of N1 is connected to the source of N2 to GND The gate of P2 is electrically connected to the drain of P1, the gate of N2, and the drain of N5; the drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1; The source of P1 and P2 are connected to VDD; the gate of N3 is connected to the right word line WLR, the gate of N4 is connected to the left word line WLL, the gate of N5 is electrically connected to the external control signal line EN; the source of N3 is connected to Bit line BLB, the source of N4 is connected to bit line BL; Wherein, P2 and N2 form an inverter, N3 and N4 form transmission tubes of the storage circuit; the storage node Q is connected to the bit line BL through N4, and the storage node QB is connected to the bit line BLB through N5 and N3. 2. The storage circuit according to claim 1, wherein the implementation of the SRAM mode by the storage circuit includes a hold operation, a write operation and a read operation; when the storage circuit performs a hold operation, the control signal line EN maintains a high level , the left word line WLL and the right word line WLR maintain a low level, and the latch structure formed by P1, P2, N1, N2, and N5 latches the stored data of the storage nodes Q and QB; when the storage circuit performs a write operation , the control signal line EN maintains a high level, the left word line WLL and the right word line WLR are pulled to a high level, and at the same time, the data to be written is loaded onto the bit line; when the storage circuit performs a read operation, the bit line BLB Precharge to high level, the control signal line EN is low level, the left word line WLL is pulled low, the right word line WLR remains high level, and the result is read through the sense amplifier SA. 3. A calculation circuit in memory with BCAM addressing and logical operation functions, which is composed of a plurality of identical memory cells in the form of an N×M array; wherein, N is the number of rows of memory cells, and M is the column of memory cells number; each row of memory cells shares the left word line WLL and the right word line WLR; each column of memory cells shares the bit lines BL and BLB; It is characterized in that the storage unit adopts the circuit structure of the storage circuit according to any one of claims 1-2, and realizes the complete functions of the circuit structure. 4. the computing circuit with BCAM addressing and logical operation function according to claim 3, is characterized in that all bit lines BL, BLB are connected with sense amplifiers in one-to-one correspondence; bit line BL or BLB is used as one input of a sense amplifier, and the other input reference voltage of the sense amplifier; when the level of BL or BLB is higher than the reference voltage, the sense amplifier outputs a high level, otherwise it outputs a low level. 5. the calculation circuit in memory with BCAM addressing and logic operation function according to claim 3, is characterized in that, the bit line BL, BLB of every column memory unit is connected on an AND gate by single-ended sense amplifier; The output terminals of the two single-ended sense amplifiers are respectively used as two-way inputs of an AND gate; when the outputs of the two sense amplifiers are both high level, the AND gate outputs high level, otherwise it outputs low level. 6. according to claim 4 or 5 described computing circuit with BCAM addressing and logic operation function in the storage, it is characterized in that, when the calculation circuit in the storage carries out the boolean logic operation in the storage, the sensitivity connected on the bit line BLB The output terminal of the amplifier is used as the output terminal of the result of performing the operation; when the calculation circuit in the memory performs the BCAM operation, the output terminal of the AND gate is used as the output terminal of the result of performing the operation; when the calculation circuit in the storage performs the multiplication operation, the bit line BLB The discharge capacity is the result of multiplication. 7. the calculation circuit with BCAM addressing and logic operation function in the memory according to claim 6, is characterized in that, the mode that the calculation circuit in the memory realizes the Boolean logic operation in the memory is as follows: Keep the left word line WLL and the control signal line EN of the same column of memory cells at low level, set the right word line WLR of the memory cells that need to participate in the Boolean logic operation in the memory to high level, and set the other word lines to low level level; the sense amplifier compares the voltage on the bit line BLB with a reference voltage and outputs the corresponding in-memory Boolean logic operation result. 8. the calculation circuit with BCAM addressing and logic operation function in the storage according to claim 6, is characterized in that, the mode that the calculation circuit in the storage realizes BCAM operation is as follows: Keep the control signal line EN of the memory cell in the same column at low level; input the voltage signal corresponding to the search data and its opposite signal to the memory cell pre-stored with the data to be searched through the left word line WLL and the right word line WLR respectively; A single-ended sense amplifier input and an AND gate will output the voltage signal of the bit line BL and BLB representing the operation result; the output terminal of the AND gate outputs a high level, indicating that the search data matches the data to be searched; the output terminal of the AND gate outputs a low voltage Ping, indicating that the search data does not match the data to be found. 9. the calculation circuit with BCAM addressing and logic operation function in the storage according to claim 6, is characterized in that, the mode that the calculation circuit in the storage realizes multiplication is as follows: Keep the control signal line EN and the left word line WLL of the same column of memory cells at low level, and input the voltage signal corresponding to the multiplicand to the memory cell pre-stored with the multiplier through the right word line WLR, according to the discharge capacity of the bit line BLB to get the desired multiplication result. 10. A memory chip, characterized in that it is packaged by the memory circuit according to any one of claims 1-2; the pins of the memory chip include: A ground pin, which is connected to the sources of the PMOS transistors P1 and P2; Power supply pins, which are connected to the sources of NMOS transistors N1 and N2; The first pin is connected to the source of the NMOS transistor N4; The second pin is connected to the source of the NMOS transistor N3; The third pin is connected to the gate of the NMOS transistor N4; The fourth pin is connected to the gate of the NMOS transistor N3.

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