CN114446350A - A row-column Boolean operation circuit for in-memory computing - Google Patents

Abstract

The invention discloses a row-column Boolean operation circuit for in-memory calculation, comprising an SRAM array, a row decoding unit, a read word line control unit and a sense amplifier SA; each Bitcell in the SRAM array adopts an 8-tube SRAM unit; On the basis of the traditional 6-tube SRAM cell, the 8-tube SRAM cell adds a control port that can read data, that is, an NMOS transistor N5 and an NMOS transistor N6, and adds a read word line RWL and a read bit line RBL, so that the present invention not only It can realize the Boolean operation of the column, the Boolean operation of the row, and the transpose calculation of the matrix, which greatly improves the ability of in-memory calculation.

Description

A row-column Boolean operation circuit for in-memory computing

technical field

The invention relates to the field of in-memory computing circuits, in particular to a row-column Boolean operation circuit for in-memory computing.

Background technique

Since the development of human science and technology, it has entered the era of artificial intelligence, and related applications such as machine learning, speech recognition, image recognition, photo search, target positioning, etc. have emerged. The computations required for these applications pose great challenges to current computing devices because they require efficient computational processing, large amounts of data storage, and high-speed data exchange between computation and storage. At present, almost all state-of-the-art computing platforms are based on a bus structure, the famous von Neumann architecture. Data is acquired from memory outside the processing unit, and after processing, it is written back to memory, even if the processing speed of the computing core is not considered. Unlike the speed of accessing memory, the limited bus bandwidth directly limits the speed at which data can be exchanged between the processor and storage, a so-called von Neumann bottleneck. Therefore, it is very meaningful to implement a row-column Boolean operation circuit for in-memory computing to break through the von Neumann bottleneck.

As shown in Figure 1, it is a traditional 6-tube SRAM (Static Random Access Memory, Chinese for static random access memory) cell structure, its PMOS transistor P1, NMOS transistor N1 and PMOS transistor P2, NMOS transistor N2 constitute two inverters respectively Thus, the data is latched, and the word line WL controls the NMOS transistor N3 and NMOS transistor N4, thereby controlling the reading and writing of the SRAM cell structure; the data of this traditional 6-tube SRAM cell structure is transmitted through the bit line BL and the bit line BLB. Currently, only column Boolean operations can be implemented, and row Boolean operations cannot be implemented yet.

In view of this, the present invention is proposed.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a row-column Boolean operation circuit for in-memory calculation, so as to solve the above-mentioned technical problems existing in the prior art. The invention can realize not only the Boolean operation of the column, but also the Boolean operation of the row, and also the transposition operation of the matrix, thereby greatly improving the ability of in-memory calculation.

The purpose of this invention is to realize through the following technical solutions:

An 8-tube SRAM cell, the 8-tube SRAM cell can include 6 NMOS transistors and 2 PMOS transistors, the 6 NMOS transistors are respectively defined as N1, N2, N3, N4, N5, N6; these 2 PMOS transistors are respectively Defined as P1, P2; PMOS transistor P1 and NMOS transistor N1 form the first inverter, PMOS transistor P2 and NMOS transistor N2 form the second inverter, and the two inverters are cross-coupled to form a data latch The drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are electrically connected to the storage node QB, the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2 are electrically connected to the storage node Q; the source of the NMOS transistor N3 is connected to the left column The bit line BLB is electrically connected, the gate of the NMOS transistor N3 is electrically connected to the word line WL, the drain of the NMOS transistor N3 is electrically connected to the storage node QB, the source of the NMOS transistor N4 is electrically connected to the right column bit line BL, and the NMOS transistor N4 The gate of the NMOS transistor N4 is electrically connected to the word line WL, the drain of the NMOS transistor N4 is electrically connected to the storage node Q; the gate of the NMOS transistor N6 is electrically connected to the storage node Q, the source of the NMOS transistor N6 is electrically connected to the ground terminal GND, and the NMOS transistor N6 is electrically connected to the ground terminal GND. The drain of the transistor N6 is electrically connected to the drain of the NMOS transistor N5; the gate of the NMOS transistor N5 is electrically connected to the read word line RWL, and the source of the NMOS transistor N5 is electrically connected to the read bit line RBL.

Preferably, the structure of the data latch includes: the source of the PMOS transistor P1 is electrically connected to the power supply VDD, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are electrically connected to the storage node QB, and the source of the NMOS transistor N1 is electrically connected to the storage node QB. The electrode of the PMOS transistor P1 is electrically connected to the ground terminal GND, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1 to form the first inverter; the source of the PMOS transistor P2 is electrically connected to the power supply VDD, and the drain of the PMOS transistor P2 The electrode and the drain of the NMOS transistor N2 are electrically connected to the storage node Q, the source of the NMOS transistor N2 is electrically connected to the ground terminal GND, and the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2, thereby forming a second inverter. The gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are both electrically connected to the storage node Q, and the gate of the PMOS transistor P2 and the gate of the NMOS transistor N2 are both electrically connected to the storage node QB, so that the first An inverter is cross-coupled with the second inverter to form a data latch.

A row and column Boolean operation circuit for in-memory calculation, comprising: SRAM array, row decoding unit, read word line control unit and sense amplifier SA; each Bitcell in the SRAM array adopts the above-mentioned 8-tube SRAM cell; the same The word lines WL of a row of Bitcells are all electrically connected to the same word line WL, the word lines WL of different rows of Bitcells are not electrically connected to the same word line WL, and the word lines WL of each row of Bitcells are electrically connected to the row decoding unit, thereby The row decoding unit controls the switches of the NMOS transistor N3 and the NMOS transistor N4 in each Bitcell through these word lines WL; the read word lines RWL of the same column of Bitcells are all electrically connected to the same read word line RWL, and the read word lines of different columns of Bitcells RWL is not electrically connected to the same read word line RWL, and the read word line RWL of each column of Bitcells is electrically connected to the read word line control unit, so that the read word line control unit controls the NMOS transistor N5 in each Bitcell through these read word lines RWL The left column bit lines BLB of the same column of Bitcells are all electrically connected to the same left column bit line BLB, and the left column bit lines BLB of different columns of Bitcells are not electrically connected to the same left column bit line BLB. Each of the column bit lines BLB is electrically connected to a sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref; the right column bit lines BL of the same column of Bitcells are all electrically connected to the same right column of bit lines BL, and the right column of bit cells of different columns The column bit lines BL are not electrically connected to the same right column bit line BL. The right column bit lines BL of each column of Bitcells are each electrically connected to a sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref; The sense amplifier SA electrically connected to the line BLB and/or the sense amplifier SA electrically connected to the right column bit line BL, so as to realize the column Boolean operation of the SRAM array; the read bit lines RBL of the same row of Bitcells are all connected to the same read bit line RBL Electrically connected, the read bit lines RBL of different rows of Bitcells are not electrically connected to the same read bit line RBL, the read bit lines RBL of each row of Bitcells are electrically connected to a sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref, Thus, the row Boolean operation of the SRAM array is realized.

Preferably, the SRAM array is a 256-row×64-column in-memory computing module.

Preferably, the row decoding unit controls the enable of the corresponding word line through the address bit of the SRAM, so as to control the read and write enable of the bitcell corresponding to each row.

Preferably, the read word line control unit controls the enable of the read word line RWL through the external address of the SRAM, so as to control the read enable of the bitcell corresponding to each column.

Compared with the prior art, the present invention adopts an SRAM array composed of 8-tube SRAM cells. The 8-tube SRAM cell is based on the traditional 6-tube SRAM cell, and two NMOS transistors (namely NMOS transistors N5 and NMOS transistors are added). NMOS transistor N6), and a read word line RWL and a read bit line RBL are added to the two NMOS transistors, which adds a control port for reading data to the 8-tube SRAM cell, each in the SRAM array. The 8-tube SRAM cells are all electrically connected to the word line WL, the read word line RWL, the left column bit line BLB, the right column bit line BL, and the read bit line RBL. The row decoding unit is used to control the enable of the word line WL, and the read word line is used. The line control unit controls the enable of the read word line RWL, and uses the sense amplifier SA to compare the voltages of the data read by the left column bit line BLB, the right column bit line BL, and the read bit line RBL, so as to realize the row direction Boolean operation, column Directional Boolean operation and matrix transposition calculation, which increase the function of row direction Boolean operation and matrix transposition calculation compared with the traditional 6-tube SRAM unit, which greatly improves the ability of in-memory calculation.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of a conventional 6-tube SRAM cell structure in the prior art;

2 is a schematic structural diagram of an 8-tube SRAM cell provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a row-column Boolean operation circuit for in-memory computing provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments, which do not It does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

First a description of terms that may be used in this article:

The term "and/or" means that either or both can be achieved, eg, X and/or Y means both the case of "X" or "Y" and the three cases of "X and Y" .

The terms "comprising", "comprising", "containing", "having" or other descriptions with similar meanings should be construed as non-exclusive inclusions. For example: including certain technical characteristic elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, processes, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.), should be construed to include not only a certain technical feature element explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

The row-column Boolean operation circuit for in-memory calculation provided by the present invention will be described in detail below. Contents that are not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art. If the specific conditions are not indicated in the examples of the present invention, it is carried out according to the conventional conditions in the art or the conditions suggested by the manufacturer. The reagents or instruments used in the examples of the present invention without the manufacturer's indication are conventional products that can be purchased from the market.

Example 1

As shown in FIG. 2 and FIG. 3 , the present invention provides a row and column Boolean operation circuit for in-memory calculation, the specific structure of which includes: an SRAM array, a row decoding unit, a read word line control unit, a word line WL, a left Column bit line BLB, right column bit line BL, read word line RWL, read bit line RBL and sense amplifier SA.

The SRAM array is a 256-row×64-column in-memory computing module, including 256×64 Bitcells; each Bitcell in the SRAM array adopts 8-tube SRAM cells, that is, the SRAM array includes 256×64 8-tube SRAM cells. As shown in Figure 2, the 8-tube SRAM cell includes 6 NMOS transistors and 2 PMOS transistors. The 6 NMOS transistors are defined as N1, N2, N3, N4, N5, and N6 respectively; the 2 PMOS transistors are respectively defined as P1, P2. The PMOS transistor P1 and the NMOS transistor N1 form the first inverter, the PMOS transistor P2 and the NMOS transistor N2 form the second inverter, and the two inverters are cross-coupled to form a data latch, that is, the first inverter The output of the inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter, so that the output state of the two inverters can be locked and saved, that is, The state of one bit is stored. The drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are electrically connected to the storage node QB, and the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2 are electrically connected to the storage node Q. The NMOS transistor N3 and the NMOS transistor N4 serve as pass transistors; the source of the NMOS transistor N3 is electrically connected to the left column bit line BLB, the gate of the NMOS transistor N3 is electrically connected to the word line WL, and the drain of the NMOS transistor N3 is electrically connected to the storage node QB connected, the source of the NMOS transistor N4 is electrically connected to the bit line BL of the right column, the gate of the NMOS transistor N4 is electrically connected to the word line WL, the drain of the NMOS transistor N4 is electrically connected to the storage node Q, and the data read from the word line WL is realized. write control. The gate of the NMOS transistor N6 is electrically connected to the storage node Q, the source of the NMOS transistor N6 is electrically connected to the ground terminal GND, the drain of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N5; the gate of the NMOS transistor N5 is electrically connected to the read The word line RWL is electrically connected, and the source of the NMOS transistor N5 is electrically connected to the read bit line RBL, so that data is read in the row direction.

The word lines WL of the same row of Bitcells are all electrically connected to the same word line WL, the word lines WL of different rows of Bitcells are not electrically connected to the same word line WL, and the word lines WL of each row of Bitcells are electrically connected to the row decoding unit, Thus, the row decoding unit controls the switches of the NMOS transistor N3 and the NMOS transistor N4 in each Bitcell through these word lines WL; the row decoding unit controls the enable of the corresponding word line through the address bit of the SRAM, thereby controlling the corresponding Bitcell of each row read and write enable.

The read word lines RWL of the same column of Bitcells are all electrically connected to the same read word line RWL. The read word lines RWL of different columns of Bitcells are not electrically connected to the same read word line RWL. The read word lines RWL of each column of Bitcells are connected to the read word line RWL. The line control unit is electrically connected, so that the read word line control unit controls the switch of the NMOS transistor N5 in each Bitcell through these read word lines RWL; the read word line control unit controls the enable of the read word line RWL through the external address of the SRAM, thereby Controls the read enable of the Bitcell corresponding to each column.

The left column bit lines BLB of the same column of Bitcells are all electrically connected to the same left column bit line BLB. The left column bit lines BLB of different columns of Bitcells are not electrically connected to the same left column bit line BLB. The left column bit lines of each column of Bitcells are electrically connected. Each BLB is electrically connected to a sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref; the right column bit lines BL of the same column of Bitcells are all electrically connected to the same right column bit line BL, and the right column bit lines of different columns of Bitcells are all electrically connected to the same right column bit line BL. BL is not electrically connected to the same right column bit line BL, and the right column bit line BL of each column of Bitcells is electrically connected to a sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref; The sense amplifier SA and the sense amplifier SA connected to the bit line BL of the right column are not the same sense amplifier SA; by comparing the voltage of the bit line BLB of the left column with the external reference voltage Vref of the sense amplifier SA, an AND logic can be realized, Comparing the voltage of the bit line BL with the external reference voltage Vref of the sense amplifier SA can realize NOR logic, thereby realizing the column Boolean operation of the SRAM array.

The read bit lines RBL of the same row of Bitcells are all electrically connected to the same read bit line RBL, the read bit lines RBL of different rows of Bitcells are not electrically connected to the same read bit line RBL, and the read bit lines RBL of each row of Bitcells are connected to a sensitive The amplifiers SA are electrically connected, and these sense amplifiers SA are respectively connected to a reference voltage Vref. By comparing the voltage of the read bit line RBL with the external reference voltage Vref of the sense amplifier SA, AND logic and NAND logic can be realized, thereby realizing the row of the SRAM array. Boolean operations.

Specifically, the row-column Boolean operation circuit for in-memory computing may include the following implementations:

(1) As shown in Figure 2, in the 8-tube SRAM cell, the NMOS transistor N3 and the NMOS transistor N4 are controlled by the word line WL, and the reading and writing of data are transmitted through the right column bit line BL and the left column bit line BLB. For input and output, the NMOS transistor N5 and the NMOS transistor N6 are controlled by the read word line RWL, and the data is transmitted from the read bit line RBL, so that the data can be transmitted in the row direction and the column direction respectively. The specific structure of the data latch may include: the source of the PMOS transistor P1 is electrically connected to the power supply VDD, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are electrically connected to the storage node QB, and the source of the NMOS transistor N1 is electrically connected to the storage node QB. It is electrically connected to the ground terminal GND, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1 to form a first inverter; the source of the PMOS transistor P2 is electrically connected to the power supply VDD, and the drain of the PMOS transistor P2 The drain of the NMOS transistor N2 is electrically connected to the storage node Q, the source of the NMOS transistor N2 is electrically connected to the ground terminal GND, and the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2, thereby forming a second reverse The gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are both electrically connected to the storage node Q, and the gate of the PMOS transistor P2 and the gate of the NMOS transistor N2 are both electrically connected to the storage node QB, so that the first The two inverters are cross-coupled with the second inverter to form a data latch, thereby realizing data latching.

(2) Implementation of the column Boolean operation function: As shown in FIG. 3 , the row and column Boolean operation circuit for in-memory calculation provided by Embodiment 1 of the present invention includes 256 rows×64 columns of in-memory calculation modules, and each column has 256 in-memory calculation modules. There are 256 8-tube SRAM cells on each column; 256 Bitcells on the same column are respectively connected with 256 word lines WL (for example: 256 word lines WL of WL ₀ to WL ₂₅₅ in FIG. 3 ), The 256 word lines WL are controlled by the row decoding unit. The row decoding unit mainly controls the enable of the corresponding word line through the address bits of the SRAM, thereby controlling the read and write enable of the 64 Bitcells of the corresponding row; the same The left column bit lines BLB of the 256 Bitcells on the column are all electrically connected to the same left column bit line BLB (for example, the left column bit lines BLB of the 256 Bitcells on the first column in FIG. 3 are all connected to the same left column bit line BLB. Line BLB ₀ is electrically connected), the right column bit lines BL of the 256 Bitcells on the same column are all electrically connected to the same right column bit line BL (for example: the right column bit lines of the 256 Bitcells on the first column in FIG. 3 ) BL are all electrically connected to the same right column bit line BL ₀ ); the left column bit line BLB of each column of Bitcells is electrically connected to a sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref (for example: the first in FIG. 3 ). The left column bit line BLB ₀ of one column of Bitcells is electrically connected to a single sense amplifier SA, and the sense amplifier SA is externally connected to the reference voltage Vref ₁ ); the right column bit line BL of each column of Bitcells is electrically connected to a sense amplifier SA, And these sense amplifiers SA are respectively connected to the reference voltage Vref (for example, the bit line BL ₀ of the right column of Bitcell in the first column in FIG. 3 is electrically connected to a single sense amplifier SA, and the sense amplifier SA is connected to the reference voltage Vref ₂ ); mainly By comparing the voltages of the left column bit line BLB and the right column bit line BL with the reference voltage Vref external to the sense amplifier SA, the result of the column Boolean operation can be obtained (for example: in FIG. 3, by comparing the voltage of the left column bit line BLB ₀ with the sensitive The reference voltage Vref ₁ external to the amplifier SA can obtain the result of the AND operation of Bitcell A and Bitcell B in the first column (that is, the result of A AND B). In Figure 3, by comparing the voltage of the bit line BL ₀ in the right column with the sense amplifier SA The external reference voltage Vref ₂ can obtain the NOR operation result of Bitcell A and Bitcell B in the first column (that is, the result of A NOR B). The OR operation of the result of the NOR operation of Bitcell B can obtain the result of the exclusive OR operation of Bitcell A and Bitcell B in the first column (that is, the result of A XNOR B).

(2) Realization of row Boolean operation function: As shown in FIG. 3 , the row and column Boolean operation circuit for in-memory calculation provided by Embodiment 1 of the present invention includes 256 rows×64 columns of in-memory calculation modules, and each row has 64 in-memory calculation modules. Bitcells, that is, there are 64 8-tube SRAM cells on each row; 64 Bitcells on the same row are respectively associated with 64 read word lines RWL (for example: RWL ₀ to RWL ₆₃ in Figure 3 are the 64 read word lines RWL) Connected, these 64 read word lines RWL are controlled by the read word line control unit. The read word line control unit mainly controls the enable of the read word line RWL through the external address of the SRAM, thereby controlling the corresponding 256 Bitcells of each column. read enable; the read bit lines RBL of the 64 Bitcells on the same row are all electrically connected to the same read bit line RBL (for example: the read bit lines RBL of the 64 Bitcells on the 256th row in Figure 3 are all connected to the same root RBL). The read bit line RBL ₂₅₅ is electrically connected), the read bit line RBL of each row of Bitcells is electrically connected to a separate sense amplifier SA, and these sense amplifiers SA are respectively connected to the reference voltage Vref (for example: the read bit cell in row 256 in FIG. 3 ) The bit line RBL ₂₅₅ is electrically connected to a sense amplifier SA, and the sense amplifier SA is connected to an external reference voltage Vref ₃ ); the result of the row Boolean operation can be obtained mainly by comparing the voltage of the read bit line RBL with the reference voltage Vref external to the sense amplifier SA ( For example, in FIG. 3, by comparing the voltage of the read bit line RBL ₂₅₅ with the reference voltage Vref ₃ connected to the sense amplifier SA, the AND operation result of Bitcell C and Bitcell D in row 256 (ie, the result of C AND D) can be obtained.

Further, the principle of the row-column Boolean operation circuit for in-memory calculation provided by Embodiment 1 of the present invention is as follows:

(1) Compared with the traditional 6-tube SRAM cell, the 8-tube SRAM cell provided in Embodiment 1 of the present invention adds two NMOS transistors (ie, the NMOS transistor N5 and the NMOS transistor N6), and on the two NMOS transistors A read word line RWL and a read bit line RBL are added. Data can be read out through this read word line RWL and this read bit line RBL, so that the 8-tube SRAM cell has two ports for reading data. , which provides a basis for implementing a row-column Boolean operation circuit for in-memory computing.

(2) The row-column Boolean operation circuit for in-memory calculation provided by Embodiment 1 of the present invention mainly realizes the functions of the column Boolean operation and the row Boolean operation:

①Column Boolean operation: first precharge the right column bit line BL ₀ and the left column bit line BLB ₀ to high level, if the row decoding unit controls word line WL ₀ and word line WL ₁ to be high level, then Bitcell A and The word line WL of Bitcell B is at high level, that is, the NMOS transistor N3 and NMOS transistor N4 in the 8-tube SRAM cell of Bitcell A and the 8-tube SRAM cell of Bitcell B are turned on, and the data in Bitcell A and Bitcell B will be turned on. The right column bit line BL ₀ and the left column bit line BLB ₀ are read in by discharging; when the data in Bitcell A and Bitcell B are different values, they are opposite to the right column bit line BL ₀ and the left column bit line BLB The discharge degree of ₀ will also be different, which can be divided into four cases: Bitcell A data is low level, Bitcell B data is low level; Bitcell A data is low level, Bitcell B data is high level; Bitcell A data is high level; It is high level, Bitcell B data is low level; Bitcell A data is high level, Bitcell B data is high level. At this time, by comparing the voltages of the right column bit line BL ₀ and the left column bit line BLB ₀ with the reference voltage Vref set by the sense amplifier SA, the Boolean operation of AND logical sum or non-logical logic can be realized, and then by combining the AND logical sum The result of the NOR logical Boolean operation is ORed to obtain the result of the XOR operation.

②Row Boolean operation: first precharge the read bit line RBL ₂₅₅ to high level, if the read word line control unit controls the read word lines RWL ₀ and RWL ₁ to be high level, at this time, the read word line RWL in Bitcell C and Bitcell D Both are high level, that is, the NMOS transistor N5 in the 8-tube SRAM unit as BitcellC and the 8-tube SRAM unit as Bitcell D are turned on; when the data in the Bitcell is high, the NMOS transistor N6 is turned on, and the read bit line RBL discharges is 0, when the data in the Bitcell is low, the NMOS transistor N6 is turned off, and the read bit line RBL remains high, that is, the data in Bitcell C and Bitcell D will be read into the read bit line RBL ₂₅₅ ; only when Bitcell C The read bit line RBL ₂₅₅ is high only when the data in Bitcell D and Bitcell D are both high. At this time, by comparing the voltage of the read bit line RBL ₂₅₅ with the reference voltage Vref ₃ set by the sense amplifier SA, the Boolean operation of AND logic and NAND logic can be realized.

(3) The row-column Boolean operation circuit for in-memory calculation provided in Embodiment 1 of the present invention can also realize matrix transposition calculation. If there is a 256×64 matrix, first control the read word line RWL ₀ to be high, then the read word lines in the 256 Bitcells in this column are all high, that is, 256 8-tube SRAM cells in this column The NMOS transistors N5 are all turned on, then the data is read into the read bit line RBL, that is, the data in the 256 Bitcells are read into the read bit line RBL ₀ to the read bit line RBL ₂₅₅ , so as to realize the column reading of the entire matrix. , and then enable RWL ₁ to RWL ₆₃ in turn, read out all the columns of the matrix, and then write the read columns into other memory cell structures in rows, thereby realizing the matrix transposition calculation.

Compared with the prior art, the in-memory computing architecture using the 8-tube SRAM cell structure in Embodiment 1 of the present invention can not only realize the Boolean operation of the column, but also the Boolean operation of the row, and this structure also supports the transposition calculation of the matrix, Thereby greatly improving the ability of in-memory computing.

From the above, it can be seen that the embodiment of the present invention can not only realize the Boolean operation of the column, but also can realize the Boolean operation of the row, and can also realize the matrix transposition operation, thereby greatly improving the ability of in-memory computing.

The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited to this. Substitutions should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in this Background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Claims (6)

1. An 8-transistor SRAM cell, wherein the 8-transistor SRAM cell comprises 6 NMOS transistors and 2 PMOS transistors, and the 6 NMOS transistors are respectively defined as N1, N2, N3, N4, N5 and N6; the 2 PMOS transistors are respectively defined as P1 and P2;

the PMOS transistor P1 and the NMOS transistor N1 form a first inverter, the PMOS transistor P2 and the NMOS transistor N2 form a second inverter, and the two inverters are cross-coupled to form a data latch; the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are electrically connected to the storage node QB, and the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2 are electrically connected to the storage node Q; the source of the NMOS transistor N3 is electrically connected to the left column bit line BLB, the gate of the NMOS transistor N3 is electrically connected to the word line WL, the drain of the NMOS transistor N3 is electrically connected to the storage node QB, the source of the NMOS transistor N4 is electrically connected to the right column bit line BL, the gate of the NMOS transistor N4 is electrically connected to the word line WL, and the drain of the NMOS transistor N4 is electrically connected to the storage node Q;

the gate of the NMOS transistor N6 is electrically connected to the storage node Q, the source of the NMOS transistor N6 is electrically connected to the ground GND, and the drain of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N5; the gate of NMOS transistor N5 is electrically connected to read word line RWL, and the source of NMOS transistor N5 is electrically connected to read bit line RBL.

2. The 8-pipe SRAM cell of claim 1, wherein the structure of the data latch comprises: a source of the PMOS transistor P1 is electrically connected to a power supply VDD, a drain of the PMOS transistor P1 and a drain of the NMOS transistor N1 are electrically connected to the storage node QB, a source of the NMOS transistor N1 is electrically connected to a ground GND, and a gate of the PMOS transistor P1 and a gate of the NMOS transistor N1 are electrically connected, thereby constituting a first inverter;

the source of the PMOS transistor P2 is electrically connected to the power supply VDD, the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2 are electrically connected to the storage node Q, the source of the NMOS transistor N2 is electrically connected to the ground GND, and the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2, thereby forming a second inverter;

the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are electrically connected to the storage node Q, and the gate of the PMOS transistor P2 and the gate of the NMOS transistor N2 are electrically connected to the storage node QB, so that the first inverter and the second inverter are cross-coupled to form a data latch.

3. A row-column boolean operation circuit for in-memory computing, comprising: the device comprises an SRAM array, a row decoding unit, a read word line control unit and a sensitive amplifier SA;

each Bitcell in the SRAM array employs an 8-transistor SRAM cell of any one of claims 1 to 2 above;

word lines WL of the same row of Bitcell are all electrically connected with the same word line WL, word lines WL of different rows of Bitcell are not electrically connected with the same word line WL, word lines WL of each row of Bitcell are all electrically connected with the row decoding unit, and therefore the row decoding unit controls switches of NMOS transistors N3 and NMOS transistors N4 in each Bitcell through the word lines WL;

the read word lines RWL of the Bitcell in the same column are all electrically connected with the same read word line RWL, the read word lines RWL of the Bitcell in different columns are not electrically connected with the same read word line RWL, the read word lines RWL of each column of Bitcell are all electrically connected with the read word line control unit, and therefore the read word line control unit controls the switch of the NMOS transistor N5 in each Bitcell through the read word lines RWL;

the left column bit lines BLB of the same Bitcell are electrically connected with the same left column bit line BLB, the left column bit lines BLB of different Bitcell columns are not electrically connected with the same left column bit line BLB, the left column bit line BLB of each Bitcell column is electrically connected with a sense amplifier SA, and the sense amplifiers SA are respectively externally connected with a reference voltage Vref; the right column bit lines BL of the same Bitcell are electrically connected with the same right column bit line BL, the right column bit lines BL of different Bitcell columns are not electrically connected with the same right column bit line BL, the right column bit line BL of each Bitcell column is electrically connected with a sense amplifier SA, and the sense amplifiers SA are respectively externally connected with a reference voltage Vref; the column Boolean operation of the SRAM array is realized through a sense amplifier SA electrically connected with a left column bit line BLB and/or a sense amplifier SA electrically connected with a right column bit line BL;

the reading bit lines RBL of the Bitcell in the same row are electrically connected with the same reading bit line RBL, the reading bit lines RBL of the Bitcell in different rows are not electrically connected with the same reading bit line RBL, the reading bit lines RBL of each Bitcell in each row are respectively electrically connected with a sensitive amplifier SA, and the sensitive amplifiers SA are respectively externally connected with a reference voltage Vref, so that the row Boolean operation of the SRAM array is realized.

4. A row-column boolean operation circuit according to claim 3 for in-memory computing characterized in that said SRAM array is a 256 row by 64 column in-memory computing module.

5. A row-column Boolean operation circuit for memory calculation according to claim 3 or 4, wherein the row decoding unit controls the enabling of the corresponding word line through the address bit of the SRAM, thereby controlling the read-write enabling of the Bitcell corresponding to each row.

6. A row-column Boolean operation circuit for in-memory calculation as claimed in claim 3 or 4, wherein said read word line control unit controls the read enable of the read word line RWL by the external address of the SRAM, thereby controlling the read enable of the Bitcell corresponding to each column.

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