CN118643001B - Memory data transmission bandwidth improving method based on parallel data channel architecture - Google Patents
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Abstract
The invention discloses a memory data transmission bandwidth improving method based on a parallel data channel architecture, which comprises a bus master module, a combinational logic module, an FSM module, a FIFO module, a MUX module, a crossbar_queue module and a standard memory subsystem module. And simultaneously, the standard memory subsystem module sends out data of a write response channel and a read data channel through the bus protocol, and the data are transmitted to the bus master module after being spliced and processed by the modules, so that the improvement of the transmission bandwidth of the data of the storage structure is realized. The invention has simple structure, easy realization, no need of modifying the memory subsystem, high reusability by adopting a standardized interface, and suitability for flexible quantity of memory subsystems so as to improve the data transmission bandwidth of the memory structure.
Description
Technical Field
The invention relates to the technical field of storage structures, in particular to a data transmission flow control design in the process of data transmission of the storage structures, and more particularly relates to a memory data transmission bandwidth improving method based on a parallel data channel architecture.
Background
With the continuous progress of technology, the requirements of modern computing demands on high-speed data access are continuously improved, and in order to meet the high requirements of memory bandwidth and performance, the rapid development of data storage technology is continuously pushing the performance improvement of computer systems. However, in face of the pressure on higher bandwidth demands, data storage technologies need to continually break through their own limitations and find new solutions.
Firstly, increasing the data transmission bandwidth of the memory structure by increasing the clock frequency is a common method, the development of the memory technology is also frequency increasing once, with the progress of the technology, the highest supporting frequency of the memory structure has reached 8533Mbps, and the method has the advantage that the bandwidth can be increased without changing the data bus and the channel, however, with the increase of the frequency, the requirements of the memory structure controller and the memory module on voltage and current also increase, which may cause the problems of power consumption and heat dissipation. High frequency operation requires more power supply and heat dissipation solutions, and thus system designers need to trade off between balance performance and power consumption. And secondly, increasing the number of channels is another method for improving the transmission bandwidth of the storage structure, the channels are physical connection channels for connecting the storage structure controller and the memory module, more parallel data transmission can be realized by increasing the number of channels, and the data transmission speed and the bandwidth are obviously improved. However, this approach requires changing the design of the memory fabric controller and the memory module, requires additional physical connections and more complex circuit designs, and at the same time, requires coordination between multiple channels while meeting the bus transfer protocol, thereby increasing the complexity of the design and hardware costs. Another method for improving the data transmission bandwidth of the memory structure is to expand the data bus width, the memory structure memory technology transmits data in parallel, the width of the data bus determines the data amount transmitted at one time, and the data transmission speed and the bandwidth can be greatly improved by increasing the data bus width, however, this method also needs more complex circuit design of the memory structure controller. While a wider data bus requires more pins and more complex wiring, which also increases the design and physical layout difficulties of the memory fabric controller and memory modules. In addition, the transmission bandwidth of the storage structure can be improved by optimizing the design and algorithm of the storage structure controller and improving a memory access mechanism. For example, improving the command scheduling and scheduling algorithm of the storage structure controller can improve the efficiency and concurrency of data access, thereby improving the overall bandwidth of the storage structure, and by improving the memory access mechanism, the caching algorithm and the prefetching algorithm, the memory access delay can be reduced, and the efficiency and bandwidth of data transmission of the storage structure can be further improved.
In summary, the above methods for improving the data transmission bandwidth of the storage structure need to be modified and optimized based on the existing storage technology of the storage structure, and involve the combination of hardware design and software algorithm of the system. In engineering applications, a great deal of manpower and material resources are consumed to implement the embodiments, and design, verification and test are performed. However, with continued advances in technology and increased computing demands, a continual increase in storage structure data transfer bandwidth is necessary to meet the demands of computer systems for telling data access.
Disclosure of Invention
The invention aims to provide a memory data transmission bandwidth improving method based on a parallel data channel architecture, which can improve the data transmission bandwidth of a memory structure without modifying the existing memory structure design.
The technical scheme for realizing the aim of the invention is that the memory data transmission bandwidth improving method based on the parallel data channel architecture comprises the following steps:
The bus master module sends out data of a write address channel, a write data channel and a read address channel through a bus protocol, and the data is processed by the combinational logic module, the FSM module, the FIFO module and the MUX module and then is transmitted to the standard memory subsystem module in parallel;
the standard memory subsystem module sends out data of a write response channel and a read data channel through a bus protocol, and the data is transmitted to the bus master module after being spliced and processed by the FSM module, the FIFO module, the crossbar_queue module, the MUX module and the combinational logic module;
The combination logic module comprises a combination logic_AW module, a combination logic_W module, a combination logic_B module, a combination logic_AR module and a combination logic_R module;
the FSM module comprises an FSM_AWmodule, an FSM_Wmodule, an FSM_B0 module, an FSM_B1 module, an FSM_AR module, an FSM_R0 module and an FSM_R1 module;
the FIFO module comprises a FIFO_AW module, a FIFO_W module and a FIFO_AR module;
the MUX module comprises a MUX_AW module, a MUX_W module, a MUX_B module, a MUX_AR module and a MUX_R module;
The crossbar_queue module comprises a crossbar_queue_B module and a crossbar_queue_R module;
The standard memory subsystem module comprises a memory 1 module and a memory 2 module;
The standard memory subsystem is a system module after integrating a memory structure controller and a memory module, and is provided with a standard AXI (Advanced eXtensible Interface) interface, an APB (ADVANCED PERPHERAL Bus) standard interface and clock and reset pins, wherein the Bus data bandwidth, namely DQ (Data and Quality), is configurable, specific values can be determined by referring to JEDEC (Joint Electron DEVICE ENGINEERING counter) DDR specification, 16, 32 and 64 data widths are supported, and DQs of a standard memory subsystem memory 1 module and a standard memory subsystem memory 2 module are equal.
In this scheme, the bus master module sends out address channel, data channel and address channel data through bus protocol, and the data is processed by the combinational logic module, FSM module, FIFO module and MUX module and then transmitted to the standard memory subsystem module in parallel, specifically:
in a write address channel AW CHANNEL of the bus protocol, write address channel data aw_m signals of the bus protocol are sent by a bus master module, and aw_c signals are obtained after transmission size and length information are split by a combinational logic_AW module;
when the FIFO_AW module temporarily has no stored data, and awready signals of the memory 1 module and the memory 2 module are pulled high, the aw_c signal is directly transmitted to the input end of the MUX_AW module, otherwise, the aw_c signal is stored in the FIFO_AW module;
Judging by the MUX_AW module, when the FIFO_AW module temporarily has no stored data, and awready signals of the memory 1 module and the memory 2 module are pulled high, the aw_s signal is equal to the aw_c signal, otherwise, the aw_s signal is equal to the output value aw_f signal of the FIFO_AW module, and the aw_s signal is transmitted to the memory 1 module and the memory 2 module simultaneously;
In a write data channel W channel of the bus protocol, a write data channel data w_m signal of the bus protocol is sent by a bus master module, and when data temporarily stored in the fifo_w module is not stored in the fifo_w module and wready signals of the memory 1 module and the memory 2 module are pulled high, the w_m signal can be directly transmitted to an input end of the mux_w module, otherwise the w_m signal is stored in the fifo_w module;
Judging by the MUX_W module, when the FIFO_W module temporarily has no stored data, and the wready signals of the memory 1 module and the memory 2 module are pulled high, the w_c signal is equal to the w_m signal, otherwise, the w_c signal is equal to the output value w_f of the FIFO_W module, and the w_s 0 and the w_s1 signals are obtained after the data are split by the combinational logic_W module and are respectively transmitted to the memory 1 module and the memory 2 module;
In the read address channel AR CHANNEL of the bus protocol, the data ar_m signal of the read address channel of the bus protocol is sent by the bus master module, and the ar_c signal is obtained after the transmission size and length information are split by the combinational logic_AR module;
When the information stored in the FIFO_AR module is empty and arready signals of the memory 1 module and the memory 2 module are pulled high, the ar_c signal is directly transmitted to the input end of the MUX_AR module, otherwise the ar_c signal is stored in the FIFO_AR module;
The mux_ar module determines that if there is no data temporarily stored in the fifo_ar module and the arready signals of the memory 1 module and the memory 2 module are pulled up, the ar_s signal is equal to the ar_c signal, otherwise the ar_s signal is equal to the ar_f signal of the output value of the fifo_ar, and the ar_s signal is transmitted to the memory 1 module and the memory 2 module simultaneously.
In this scheme, the standard memory subsystem module sends out write response channel and read data channel data through bus protocol, and the data are transmitted to the bus master module after being spliced by the FSM module, the FIFO module, the crossbar_queue module, the MUX module and the combinational logic module, specifically:
In a write response channel B channel of the bus protocol, a write response channel data b_s0 signal and a b_s1 signal of the bus protocol are respectively sent by a memory 1 module and a memory 2 module, the b_s0 signal passes through an fsm_b0 module, when a crossbar_queue_b module temporarily has no stored information, and a bready signal of the bus master module is pulled high, the b_s0 signal is directly transmitted to an input end of the mux_b module, otherwise, the b_s0 signal is stored in the crossbar_queue_b module;
The b_s1 signal passes through the FSM_B1 module, when the crossbar_queue_B module temporarily has no stored data, and the bready signal of the bus master is pulled high, the b_s1 signal is directly transmitted to the input end of the MUX_B module, otherwise, the b_s1 signal is stored in the crossbar_queue_B module;
When two bid_m0 and b_m1 signals in the bus protocol are the same and respectively source the memory 1 module and the memory 2 module, the MUX_B module selects two signals b_m0 and b_m1 which meet the matching condition from the b_s0, b_s1 and the output b_q signals of the crossbar_queue_B module, and then the signals are combined by the logic_B module to obtain a final b_m signal to be transmitted to the bus master module;
In a read data channel R channel of the bus protocol, a read data channel r_s0 signal and a r_s1 signal of the bus protocol are respectively sent by a memory 1 module and a memory 2 module, the r_s0 signal passes through an fsm_r0 module, when a crossbar_queue_r module temporarily has no stored information, and a rready signal of the bus master module is pulled high, the r_s0 signal is directly transmitted to an input end of the mux_r module, otherwise, the r_s0 signal is stored in the crossbar_queue_r module;
The r_s1 signal passes through the fsm_r1 module, when the crossbar_queue_r has no data stored temporarily therein, and the rready signal of the bus master module is pulled high, the r_s1 signal can be directly transmitted to the input end of the mux_r module, otherwise, the r_s1 signal is stored in the crossbar_queue_r module;
When two rid_signals in the bus protocol are the same and the signals of r_m0 and r_m1 are respectively sourced from the memory 1 module and the memory 2 module, the mux_r module selects two signals r_m0 and r_m1 meeting the matching condition from the signals of r_s0, r_s1 and the output r_q of the crossbar_queue_r module, and then the signals are transmitted to the bus master module through the combinational logic_r module to obtain the final r_m signal.
In this scheme, the w_s0 and w_s1 signals are obtained by splitting the data by the combinational logic_w module, and the width of the split data is the DQ value of the standard memory subsystem.
In this scheme, the crossbar_queue module is implemented by using a plurality of FIFO modules with ID as a matching condition.
In this scheme, the r_m0 signal and the r_m1 signal are spliced by the combinational logic_r module to obtain the r_m signal, where the width of the spliced data is the bus data bandwidth value of the standard memory subsystem.
Compared with the prior art, the invention has the remarkable advantages that:
(1) The invention adopts a simple and easy-to-implement design architecture, which not only can reduce hardware cost, but also is completely independent of the memory subsystem module. Because the memory subsystem is not required to be modified, a large amount of manpower and material resources are saved, and meanwhile, a user can complete development work in a short time, so that the data transmission bandwidth of the memory structure is improved.
(2) The invention adopts standardized interfaces, has high reusability, is not limited by the configuration of a specific memory subsystem, and can be suitable for various memory subsystems. This provides convenience for the user's quick application in existing memory subsystem designs.
(3) The invention is suitable for the flexible number of memory subsystems, and can be customized according to the user requirements so as to improve the data transmission bandwidth of the storage structure.
The invention discloses a memory data transmission bandwidth improving method based on a parallel data channel architecture, which comprises a bus master module, a combinational logic module, an FSM module, a FIFO module, a MUX module, a crossbar_queue module and a standard memory subsystem module. And simultaneously, the standard memory subsystem module sends out data of a write response channel and a read data channel through the bus protocol, and the data are transmitted to the bus master module after being spliced and processed by the modules, so that the improvement of the transmission bandwidth of the data of the storage structure is realized. The invention has simple structure, easy realization, no need of modifying the memory subsystem, high reusability by adopting a standardized interface, and suitability for flexible quantity of memory subsystems so as to improve the data transmission bandwidth of the memory structure.
Drawings
Fig. 1 is a schematic diagram of a memory data transmission bandwidth improving method based on a parallel data channel structure according to the present invention.
FIG. 2 is a diagram illustrating data splitting in a write data channel according to the present invention.
FIG. 3 is a schematic diagram of data splicing in a read data channel according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
Fig. 1 shows a flow chart of a memory data transmission bandwidth improving method based on a parallel data channel architecture according to the present invention.
The configuration of the memory 1 and the memory 2 shown in fig. 1 is the same.
As shown in fig. 1, a first aspect of the present invention provides a memory data transmission bandwidth improving method based on a parallel data channel architecture, including:
The bus master module sends out data of a write address channel, a write data channel and a read address channel through a bus protocol, and the data is processed by the combinational logic module, the FSM module, the FIFO module and the MUX module and then is transmitted to the standard memory subsystem module in parallel;
the standard memory subsystem module sends out data of a write response channel and a read data channel through a bus protocol, and the data is transmitted to the bus master module after being spliced and processed by the FSM module, the FIFO module, the crossbar_queue module, the MUX module and the combinational logic module;
The combination logic module comprises a combination logic_AW module, a combination logic_W module, a combination logic_B module, a combination logic_AR module and a combination logic_R module;
the FSM module comprises an FSM_AWmodule, an FSM_Wmodule, an FSM_B0 module, an FSM_B1 module, an FSM_AR module, an FSM_R0 module and an FSM_R1 module;
the FIFO module comprises a FIFO_AW module, a FIFO_W module and a FIFO_AR module;
the MUX module comprises a MUX_AW module, a MUX_W module, a MUX_B module, a MUX_AR module and a MUX_R module;
The crossbar_queue module comprises a crossbar_queue_B module and a crossbar_queue_R module;
The standard memory subsystem module comprises a memory 1 module and a memory 2 module;
The standard memory subsystem is a system module after integrating a memory structure controller and a memory module, and is provided with a standard AXI (Advanced eXtensible Interface) interface, an APB (ADVANCED PERPHERAL Bus) standard interface and clock and reset pins, wherein the Bus data bandwidth, namely DQ (Data and Quality), is configurable, specific values can be determined by referring to JEDEC (Joint Electron DEVICE ENGINEERING counter) DDR specification, 16, 32 and 64 data widths are supported, and DQs of a standard memory subsystem memory 1 module and a standard memory subsystem memory 2 module are equal.
According to the embodiment of the invention, the bus master module sends out data of a write address channel, a write data channel and a read address channel through a bus protocol, and the data is processed by the combinational logic module, the FSM module, the FIFO module and the MUX module and then is transmitted to the standard memory subsystem module in parallel, wherein the data is specifically as follows:
in a write address channel AW CHANNEL of the bus protocol, write address channel data aw_m signals of the bus protocol are sent by a bus master module, and aw_c signals are obtained after transmission size and length information are split by a combinational logic_AW module;
when the FIFO_AW module temporarily has no stored data, and awready signals of the memory 1 module and the memory 2 module are pulled high, the aw_c signal is directly transmitted to the input end of the MUX_AW module, otherwise, the aw_c signal is stored in the FIFO_AW module;
Judging by the MUX_AW module, when the FIFO_AW module temporarily has no stored data, and awready signals of the memory 1 module and the memory 2 module are pulled high, the aw_s signal is equal to the aw_c signal, otherwise, the aw_s signal is equal to the output value aw_f signal of the FIFO_AW module, and the aw_s signal is transmitted to the memory 1 module and the memory 2 module simultaneously;
In a write data channel W channel of the bus protocol, a write data channel data w_m signal of the bus protocol is sent by a bus master module, and when data temporarily stored in the fifo_w module is not stored in the fifo_w module and wready signals of the memory 1 module and the memory 2 module are pulled high, the w_m signal can be directly transmitted to an input end of the mux_w module, otherwise the w_m signal is stored in the fifo_w module;
Judging by the MUX_W module, when the FIFO_W module temporarily has no stored data, and the wready signals of the memory 1 module and the memory 2 module are pulled high, the w_c signal is equal to the w_m signal, otherwise, the w_c signal is equal to the output value w_f of the FIFO_W module, and the w_s 0 and the w_s1 signals are obtained after the data are split by the combinational logic_W module and are respectively transmitted to the memory 1 module and the memory 2 module;
In the read address channel AR CHANNEL of the bus protocol, the data ar_m signal of the read address channel of the bus protocol is sent by the bus master module, and the ar_c signal is obtained after the transmission size and length information are split by the combinational logic_AR module;
When the information stored in the FIFO_AR module is empty and arready signals of the memory 1 module and the memory 2 module are pulled high, the ar_c signal is directly transmitted to the input end of the MUX_AR module, otherwise the ar_c signal is stored in the FIFO_AR module;
The mux_ar module determines that if there is no data temporarily stored in the fifo_ar module and the arready signals of the memory 1 module and the memory 2 module are pulled up, the ar_s signal is equal to the ar_c signal, otherwise the ar_s signal is equal to the ar_f signal of the output value of the fifo_ar, and the ar_s signal is transmitted to the memory 1 module and the memory 2 module simultaneously.
According to the embodiment of the invention, the standard memory subsystem module sends out data of a write response channel and a read data channel through a bus protocol, and the data is transmitted to the bus master module after being spliced and processed by the FSM module, the FIFO module, the crossbar_queue module, the MUX module and the combinational logic module, specifically:
In a write response channel B channel of the bus protocol, a write response channel data b_s0 signal and a b_s1 signal of the bus protocol are respectively sent by a memory 1 module and a memory 2 module, the b_s0 signal passes through an fsm_b0 module, when a crossbar_queue_b module temporarily has no stored information, and a bready signal of the bus master module is pulled high, the b_s0 signal is directly transmitted to an input end of the mux_b module, otherwise, the b_s0 signal is stored in the crossbar_queue_b module;
The b_s1 signal passes through the FSM_B1 module, when the crossbar_queue_B module temporarily has no stored data, and the bready signal of the bus master is pulled high, the b_s1 signal is directly transmitted to the input end of the MUX_B module, otherwise, the b_s1 signal is stored in the crossbar_queue_B module;
When two bid_m0 and b_m1 signals in the bus protocol are the same and respectively source the memory 1 module and the memory 2 module, the MUX_B module selects two signals b_m0 and b_m1 which meet the matching condition from the b_s0, b_s1 and the output b_q signals of the crossbar_queue_B module, and then the signals are combined by the logic_B module to obtain a final b_m signal to be transmitted to the bus master module;
In a read data channel R channel of the bus protocol, a read data channel r_s0 signal and a r_s1 signal of the bus protocol are respectively sent by a memory 1 module and a memory 2 module, the r_s0 signal passes through an fsm_r0 module, when a crossbar_queue_r module temporarily has no stored information, and a rready signal of the bus master module is pulled high, the r_s0 signal is directly transmitted to an input end of the mux_r module, otherwise, the r_s0 signal is stored in the crossbar_queue_r module;
The r_s1 signal passes through the fsm_r1 module, when the crossbar_queue_r has no data stored temporarily therein, and the rready signal of the bus master module is pulled high, the r_s1 signal can be directly transmitted to the input end of the mux_r module, otherwise, the r_s1 signal is stored in the crossbar_queue_r module;
When two rid_signals in the bus protocol are the same and the signals of r_m0 and r_m1 are respectively sourced from the memory 1 module and the memory 2 module, the mux_r module selects two signals r_m0 and r_m1 meeting the matching condition from the signals of r_s0, r_s1 and the output r_q of the crossbar_queue_r module, and then the signals are transmitted to the bus master module through the combinational logic_r module to obtain the final r_m signal.
According to the embodiment of the invention, the w_s0 and w_s1 signals are obtained by splitting the data by the combinational logic_w module, and the split data width is the DQ value of the standard memory subsystem.
According to the embodiment of the invention, the crossbar_queue module is realized by using a plurality of FIFO modules by taking the ID as a matching condition.
According to the embodiment of the invention, the r_m0 signal and the r_m1 signal are spliced by the combinational logic_r module to obtain the r_m signal, and the width of the spliced data is the bus data bandwidth value of the standard memory subsystem.
It should be noted that the storage structure is a memory, the storage structure includes a random access memory such as DRAM, SRAM, PSRAM, HBM, flash and a memory device, and the bus protocol includes a buffer transmission protocol such as AMBA, OCP, CHI.
Compared with the prior art, the invention adopts a simple and easy-to-implement design architecture, not only can reduce the hardware cost, but also is completely independent of the memory subsystem module. Because the memory subsystem is not required to be modified, a large amount of manpower and material resources are saved, and a user can complete development work in a short time, so that the data transmission bandwidth of the memory structure is improved; in addition, the invention adopts standardized interfaces, has high reusability, is not limited by specific memory subsystem configuration, and can be suitable for various memory subsystems. The invention is suitable for flexible quantity of memory subsystems, and can be customized according to the user requirement so as to improve the data transmission bandwidth of the memory structure.
The invention discloses a memory data transmission bandwidth improving method based on a parallel data channel architecture, which comprises a bus master module, a combinational logic module, an FSM module, a FIFO module, a MUX module, a crossbar_queue module and a standard memory subsystem module. The bus master sends out data of a write address channel, a write data channel and a read address channel through a bus protocol, and the data are processed by each module and then transmitted to the memory subsystem module in parallel, and meanwhile, the memory subsystem module sends out data of a write response channel and a read data channel through the bus protocol, and the data are transmitted to the master module after being spliced by each module, so that the improvement of the transmission bandwidth of the data of the storage structure is realized. The invention has simple structure, easy realization, no need of modifying the memory subsystem, high reusability by adopting the standardized interface, and convenience for users to rapidly apply the existing memory subsystem design, and is applicable to flexible number of memory subsystems to improve the data transmission bandwidth of the memory structure.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is merely a logical function division, and there may be additional divisions of actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described as separate components may or may not be physically separate, and components displayed as units may or may not be physical units, may be located in one place or distributed on a plurality of network units, and may select some or all of the units according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present invention may be integrated in one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of hardware plus a form of software functional unit.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
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| CN105005546A (en) * | 2015-06-23 | 2015-10-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Asynchronous AXI bus structure with built-in cross point queue |
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| CN112214945B (en) * | 2020-10-13 | 2023-11-14 | 安徽芯纪元科技有限公司 | AXI bus isolation protection structure and protection method thereof |
| CN114153775B (en) * | 2021-12-10 | 2024-02-09 | 中国兵器工业集团第二一四研究所苏州研发中心 | FlexRay controller based on AXI bus |
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| CN105005546A (en) * | 2015-06-23 | 2015-10-28 | 中国兵器工业集团第二一四研究所苏州研发中心 | Asynchronous AXI bus structure with built-in cross point queue |
| CN110704351A (en) * | 2019-09-24 | 2020-01-17 | 山东华芯半导体有限公司 | Host equipment data transmission expansion method based on AXI bus |
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