CN113312304B - A kind of interconnection device, motherboard and server - Google Patents

Abstract

The invention provides an interconnection device, a main board and a server. The interconnection device includes at least two groups of interfaces and control modules. Each group of interfaces includes at least one interface unit; at least one interface unit of each group of interfaces is in one-to-one correspondence with at least one small chip of the chip module; each interface unit is connected to a corresponding small chip. The control module establishes a link between any two interface units from different groups of interfaces, so that the two chiplets corresponding to the two interface units perform data transmission. When realizing interconnection at the board level, it is only necessary to interconnect each chiplet and the interface unit of the interconnection device on the bus in the circuit board, and there is no need to interconnect each chiplet with other chiplets at the board level, reducing each The number of lead-out pins on each slot reduces the difficulty of wiring in the circuit board. Less restricted by various protocols inside the chip module, it is easy to expand to interconnection of different types of chip modules. It can greatly reduce the delay, facilitate programming and ensure multi-channel performance.

Description

A kind of interconnection device, motherboard and server

technical field

The invention relates to the technical field of computers, in particular to an interconnection device, a main board and a server.

Background technique

With the rapid development of chip technology, the current line width of the chip is already below 10 nanometers (nm). In this way, 10 billion-level transistors can be integrated on each chip, and multiple types of modules such as computing units, caches, control logic, high-speed IO, and distributed clocks can be placed on it. This poses severe challenges to chip design and verification. The test verification of the current chip often exceeds the time of chip design. The high complexity of the chip and the uncontrollable factors in the production process mean that a defect in one module of the chip will cause the entire chip to be defective or downshifted.

In order to ensure that the test process is simple and fast, and in order to ensure a good yield rate of the chip, a small chip (Chiplet, sometimes called Die) technology that effectively divides functional modules has emerged as the times require. Small chip technology can alleviate the problems caused by the above technological evolution to a certain extent. However, Chiplet technology inevitably needs to divide some interconnected buses, which will cause the component link delay and bandwidth of the external Chiplet to be greatly degraded compared with the internal bus (Internal Bus, IB for short). For example, the delay of accessing memory between X86 multi-channel (or multi-Socket (slot)) CPUs (central processing units) is more than twice the internal delay, and the delay between some complex multi-channel CPUs can reach the internal delay. more than 3 times the delay. Usually, the delay between chiplets increases, which will cause delay-sensitive applications, such as databases, big data computing, etc., to have greater performance loss when multi-channel interconnection. In other words, even if the number of Sockets increases, the performance of the system does not increase significantly, but performance may decrease instead. The main reason for the performance degradation is that such applications are not only computationally intensive, but also require a lot of memory, and the data is highly correlated with each other. In extreme cases, the application has to use only one socket (Socket) instead of multiple sockets in the entire system, otherwise the system performance will decrease instead.

At present, when multi-Chiplet or multi-Die chips are interconnected, it is generally necessary for each Chiplet to be fully interconnected with different Chiplets in another slot, so that delay and bandwidth can be guaranteed. However, this will result in the multiplication of pins on each socket, as shown in Figure 1 in the case of two Sockets with a total of 8 Chiplets. When implemented at the board level, wiring will be very difficult, resulting in a significant increase in the cost of the circuit board. In addition, a Chiplet can be used to connect to a Chiplet or Die in another slot, using this Chiplet as a bridge to connect to other Chiplets in the same slot, that is, using a remote Chiplet as a bridge for interconnection, but This interconnection method will result in a significant increase in latency.

Contents of the invention

The invention provides an interconnection device, a main board and a server to reduce the difficulty of wiring inside the circuit board, improve the expansion performance of the system, reduce time delay, facilitate programming and ensure multi-channel performance.

In a first aspect, the present invention provides an interconnection device, which includes at least two groups of interfaces corresponding to at least two slots one-to-one, and a control module. Wherein, each slot is plugged with a chip module; each chip module is provided with at least one small chip, and at least one chip module is a multi-chip module containing at least two small chips; each group of interfaces contains at least one Interface unit; at least one interface unit of each group of interfaces corresponds to at least one chiplet in the chip module corresponding to the group of interfaces; each interface unit is connected to the corresponding chiplet. The control module is used to establish a link between any two interface units from different groups of interfaces, so that the two chiplets corresponding to the two interface units can perform data transmission.

In the above scheme, the small chips in the chip modules plugged in different slots are connected through the interconnection device, and the control module of the interconnection device establishes links for the small chips in different chip modules to realize the two small chips. Data transfer between chips. Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each chiplet and the interface unit of the interconnection device on the bus in the circuit board, and there is no need to interconnect each chiplet with other chiplets at the board level, reducing The number of lead-out pins on each slot reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board. And through the control module to control different interface units in the interconnection device to establish links for data transmission, during data transmission, it is less restricted by various protocols inside the chip module, so the interconnection method has strong protocol insensitivity , easy to expand to different types of chip module interconnection. Moreover, when two small chips from different chip modules transmit data through the interconnection device, they can perform full bandwidth transmission. Compared with the prior art that uses the remote Chiplet as a bridge for interconnection, the solution of this application can greatly reduce Low latency, easy programming and guaranteed multi-channel performance.

In a specific embodiment, each interface unit includes an address and control interface and a data interface; wherein, the address and control interface is connected to the address and control interface of the chiplet corresponding to the interface unit, and the data interface is connected to the corresponding interface of the interface unit. The data interface connection of the chiplet. That is to say, each interface unit is divided into address, control interface and data interface, and adopts the method of separating the control address plane from the data plane, which is not sensitive to the equipment transmission protocol, and it is convenient for various high-speed modules using the same protocol to form a high-performance system together. And when performing data transmission between two small chips in different chip modules, one small chip first sends the address information of the small chip at the receiving end to the interconnection device, and the interconnection device decodes and configures the link. At the same time, the small chip prepares data . After the small chip is ready to send the data, the data is transmitted through the link configured by the interconnection device at the first time, reducing the delay caused by configuring the link, thereby reducing the delay of the entire system.

In a specific embodiment, when data is transmitted from any two chiplets in different chip modules, one of the two chiplets is the sending end, and the other is the receiving end. The control module includes a storage module, a cross switch matrix, an address decoding module and a monitoring module. Wherein, the storage module is used for storing the node address information of the receiving end transmitted by the sending end through the address and control interface. The crossbar matrix is connected to each data interface. The address decoding module is used to establish a data link relationship between the data interface corresponding to the sending end and the data interface corresponding to the receiving end according to the node address information, and store the data link relationship in the cache queue of the storage module. The monitoring module is used to monitor whether there is an idle link matching the data link relationship in the buffer queue in the crossbar switch matrix; the monitoring module is also used to control the crossbar according to the matching data link relationship when there is a matching idle link. The switch matrix establishes a data transmission link for the data interface corresponding to the sending end and the data interface corresponding to the receiving end. That is, through the mutual cooperation of the storage module, the address decoding module and the monitoring module, it is convenient to find that the established data link relationship can match with the idle link in time, so as to quickly complete the configuration of the data transmission link.

In a specific embodiment, the storage module is a static random access memory, so as to increase the reading and writing speed of the interconnection module when configuring the data transmission link, thereby improving the configuration efficiency of the data transmission link and reducing the time delay.

In a second aspect, the present invention also provides a motherboard, which includes a circuit board. At least two slots are arranged on the circuit board, and a chip module is plugged into each slot, wherein each chip module is provided with at least one small chip, and at least one chip module contains at least two A multi-chip module of a small chip. An interconnection device is also arranged on the main board. The interconnection device includes a control module and at least two sets of interfaces. Wherein, each group of interfaces includes at least one interface unit; at least one interface unit of each group of interfaces is in one-to-one correspondence with at least one chiplet in the chip module corresponding to the group of interfaces. Each interface unit is connected to a corresponding chiplet. The control module is used to establish a link between any two interface units from different groups of interfaces, so that the two chiplets corresponding to the two interface units can perform data transmission.

In the above scheme, the small chips in the chip modules plugged in different slots are connected through the interconnection device, and the control module of the interconnection device establishes links for the small chips in different chip modules to realize the two small chips. Data transfer between chips. Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each chiplet and the interface unit of the interconnection device on the bus in the circuit board, and there is no need to interconnect each chiplet with other chiplets at the board level, reducing The number of lead-out pins on each slot reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board and the manufacturing cost of the main board. And through the control module to control different interface units in the interconnection device to establish links for data transmission, during data transmission, it is less restricted by various protocols inside the chip module, so the interconnection method has strong protocol insensitivity , easy to expand to different types of chip module interconnection. Moreover, when two small chips from different chip modules transmit data through the interconnection device, they can perform full bandwidth transmission. Compared with the prior art that uses the remote Chiplet as a bridge for interconnection, the solution of this application can greatly reduce Low latency, easy programming and guaranteed multi-channel performance.

In a specific implementation manner, each chiplet is provided with an address, a control interface, and a data interface, and each interface unit includes an address, a control interface, and a data interface. Wherein, the address and control interface is connected with the address and control interface of the chiplet corresponding to the interface unit, and the data interface is connected with the data interface of the chiplet corresponding to the interface unit. That is to say, each interface unit is divided into address, control interface and data interface, and adopts the method of separating the control address plane from the data plane, which is not sensitive to the equipment transmission protocol, and it is convenient for various high-speed modules using the same protocol to form a high-performance system together. And when performing data transmission between two small chips in different chip modules, one small chip first sends the address information of the small chip at the receiving end to the interconnection device, and the interconnection device decodes and configures the link. At the same time, the small chip prepares data . After the small chip is ready to send the data, the data is transmitted through the link configured by the interconnection device at the first time, reducing the delay caused by configuring the link, thereby reducing the delay of the entire system.

In a specific embodiment, when any two chiplets from different chip modules transmit data, one of the two chiplets is a sending end, and the other is a receiving end. The control module includes a storage module, a cross switch matrix, an address decoding module and a monitoring module. Wherein, the storage module is used for storing the node address information of the receiving end transmitted by the sending end through the address and control interface. The crossbar matrix is connected to each data interface. The address decoding module is used to establish a data link relationship between the data interface corresponding to the sending end and the data interface corresponding to the receiving end according to the node address information, and store the data link relationship in the cache queue of the storage module. The monitoring module is used to monitor whether there is an idle link matching the data link relationship in the cache queue in the crossbar switch matrix; the monitoring module is also used to control when storing the matched idle link according to the matching data link relationship. The crossbar matrix establishes a data transmission link for the data interface corresponding to the sending end and the data interface corresponding to the receiving end. That is, through the mutual cooperation of the storage module, the address decoding module and the monitoring module, it is convenient to find that the established data link relationship can match with the idle link in time, so as to quickly complete the configuration of the data transmission link.

In a specific embodiment, each chiplet is provided with a data bus, and the data bus is connected to the address and control interface and the data interface on the chiplet. The interconnection device is not sensitive to various protocols inside each small chip, and it is convenient to expand to interconnection of different types of chip modules.

In a specific implementation, the chip module is a central processing unit and/or a dedicated high-performance chip.

In a specific embodiment, the dedicated high-performance chip is a graphics processing unit (Graphics Processing Unit, referred to as GPU), an artificial intelligence AI (Artificial Intelligence, referred to as AI chip) chip, a field programmable logic gate array (Field Programmable Gate Array, FPGA for short) or Application Specific Integrated Circuit (ASIC for short).

In a third aspect, the present invention also provides a server, which is any one of the aforementioned motherboards. The small chips in the chip modules inserted in different slots are connected through the interconnection device, and the control module of the interconnection device establishes links for the small chips in different chip modules to realize data transmission between the two small chips . Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each chiplet and the interface unit of the interconnection device on the bus in the circuit board, and there is no need to interconnect each chiplet with other chiplets at the board level, reducing The number of lead-out pins on each slot reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board and the manufacturing cost of the main board. And through the control module to control different interface units in the interconnection device to establish links for data transmission, during data transmission, it is less restricted by various protocols inside the chip module, so the interconnection method has strong protocol insensitivity , easy to expand to different types of chip module interconnection. Moreover, when two small chips from different chip modules transmit data through the interconnection device, they can perform full bandwidth transmission. Compared with the prior art that uses the remote Chiplet as a bridge for interconnection, the solution of this application can greatly reduce Low latency, easy programming and guaranteed multi-channel performance. In turn, the cost of the server is reduced, and the delay of the server is reduced.

Description of drawings

FIG. 1 is a schematic diagram of an interconnection that realizes full interconnection provided in the prior art;

FIG. 2 is a structural block diagram of realizing full interconnection through an interconnection device provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of interconnection of different types of chip modules provided by an embodiment of the present invention through an interconnection device;

FIG. 4 is a structural block diagram of separating the address control plane and the data plane to realize data transmission according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an internal module path for interconnection of two chiplets from different chip modules provided by an embodiment of the present invention.

Reference signs:

10-interconnect device 11-interface unit 111-address and control interface 112-data interface

12-Control Module 121-Crossbar Matrix 122-Cache Queue 123-Monitoring Module

20-chip module 21-small chip

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In order to facilitate the understanding of the interconnection device provided by the embodiment of the present invention, the application scenario of the interconnection device provided by the embodiment of the present invention will be described first below. Chiplets in chip modules. The interconnection device will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 2 , the interconnection device 10 provided by the embodiment of the present invention includes at least two groups of interfaces corresponding to at least two slots one-to-one. Wherein, each slot inserts a chip module 20, and at least one small chip 21 is arranged in each chip module 20, and at least one chip module 20 is a multi-chip module that includes at least two small chips 21; The interface includes at least one interface unit 11; at least one interface unit 11 of each group of interfaces corresponds to at least one small chip 21 in the chip module 20 corresponding to the group of interfaces; each interface unit 11 is connected to the corresponding small chip 21 . That is, the number of slots is equal to the number of chip modules 20 , and one chip module 20 is plugged into each slot. Each chip module 20 is provided with at least one small chip 21 , and at least one chip module 20 is a multi-chip module, and each multi-chip module is provided with at least two small chips 21 . The number of interface groups on the interconnection device 10 is equal to the number of chip modules 20 , and each chip module 20 corresponds to a group of interfaces. The number of chiplets 21 on each chip module 20 is equal to the number of interface units 11 in a group of interfaces corresponding to the chip module 20 . There is also at least two interface units 11 included in at least one group of interfaces, corresponding to at least two chiplets 21 in at least one multi-chip module. Each chiplet 21 is connected to an interface unit 11 .

When specifically determining the number of chip modules 20 , the number of chip modules 20 may be any value not less than 2, such as 2, 3, 4, 5, 10, or the like. The number of corresponding slots is equal to the number of chip modules 20, and each chip module 20 is plugged into a corresponding slot to realize the wiring connection between the chip module 20 and the circuit board. What is shown in FIG. 2 is the interconnection of two chip modules 20 , and what is shown in FIG. 3 is the interconnection of four chip modules 20 . When determining the type of the chip module 20, the chip module 20 can be a central processing unit, or a dedicated high-performance chip, or a part of the chip module 20 can be a central processing unit, and a part of the chip module 20 can be a dedicated high-performance chip. . Specifically, the dedicated high-performance chip may be a graphics processor, an artificial intelligence (AI) chip, a field programmable logic gate array, or an application-specific integrated circuit. More specifically, as shown in Figure 2, two central processing units (CPU0, CPU1) are interconnected, and as shown in Figure 3, two central processing units (CPU0, CPU1), a graphics processing unit (GPU0) A total of four chip modules 20 are interconnected with a field programmable logic gate array (FPGA). Of course, the chip module 20 can also be other types of accelerator cards. When determining the number of small chips 21 contained in each chip module 20, the number of small chips 21 contained in each chip module 20 can be 1, 2, 3, 4, etc. Any value greater than or equal to 1, and at least one chip module 20 is a multi-chip module, and the number of chiplets 21 contained in the multi-chip module is any value not less than 2, such as 2, 3, 4, etc. .

Referring to Fig. 2, the interconnection device 10 also includes a control module 12, which is used to establish a link between any two interface units 11 from different groups of interfaces, so that the two chiplets corresponding to the two interface units 11 21 for data transmission. The chiplets 21 in the chip modules 20 that are plugged into different slots are connected through the interconnection device 10, and the control module 12 of the interconnection device 10 establishes a link for the chiplets 21 in different chip modules 20 to realize the two Data transfer between chiplets 21 . Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each small chip 21 and the interface unit 11 of the interconnection device in the circuit board bus, and it is not necessary to interconnect each small chip 21 and other small chips 21 with other small chips at the board level. The chip 21 reduces the number of lead-out pins on each slot, and at the same time reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board. Moreover, the control module 12 controls the different interface units 11 in the interconnection device 10 to establish links for data transmission. During data transmission, it is less restricted by various protocols inside the chip module 20, so that the interconnection mode has a strong The protocol is insensitive, and it is convenient to extend to the interconnection of different types of chip modules 20 . Moreover, when the two small chips 21 from different chip modules 20 transmit data through the interconnection device 10, they can perform full bandwidth transmission. Significantly reduce delay, facilitate programming and ensure multi-channel performance.

When specifically setting each interface unit 11 , referring to FIG. 2 , each interface unit 11 may include an address and control interface 111 and a data interface 112 . Wherein, the address and control interface 111 is connected with the address and control interface of the chiplet 21 corresponding to the interface unit 11 , and the data interface 112 is connected with the data interface of the chiplet 21 corresponding to the interface unit 11 . That is to say, each interface unit 11 is divided into address and control interface 111 and data interface 112. The method of separating the control address plane from the data plane is not sensitive to the equipment transmission protocol, and it is convenient for various high-speed modules using the same protocol to form a high-performance system together. . And when performing data transmission between two small chips 21 in different chip modules 20, one small chip 21 first sends the address information of the receiving end small chip 21 to the interconnection device 10, and the interconnection device 10 decodes and configures the link , while the chiplet 21 prepares data. After the chiplet 21 prepares the data to be sent, the data is transmitted through the link configured by the interconnection device 10 at the first time, reducing the delay caused by configuring the link, thereby reducing the delay of the entire system. It should be understood that each interface unit 11 is not limited to the above-mentioned arrangement of dividing into an address and control interface 111 and a data interface 112 , and other arrangements can also be adopted. For example, the address and control interface 111 and the data interface 112 can be combined into one interface, and a data transmission mode of sending node address information and data together is adopted.

When specifically setting the control module 12, with reference to Fig. 2 and Fig. 4, the control module 12 may include a storage module (not shown in the figure), a crossbar switch matrix 121, an address decoding module (not shown in the figure) and a monitoring module 123. For ease of description, when any two chiplets 21 in different chip modules 20 transmit data, one of the two chiplets 21 is defined as the sending end, and the other is defined as the receiving end. The storage module in the control module 12 is used to store the node address information of the receiving end transmitted by the sending end through the address and control interface 111 . That is, after the address and control interface 111 in the interface unit 11 corresponding to the sending end receives the node address information of the receiving end transmitted from the sending end, it transfers the node address information to the storage module, so as to facilitate the subsequent processing of the node address information Decode and configure the corresponding data link relationship.

With reference to Fig. 4, the crossbar matrix 121 among them is all connected with each data interface 112, is convenient to realize the interconnection or disconnection between different data interfaces 112 by conducting or disconnecting between different nodes in the crossbar matrix 121. open. The crossbar switch matrix 121 is a switch matrix with switch gating function in the prior art.

The address decoding module is used to establish a data link relationship between the data interface 112 corresponding to the sending end and the data interface 112 corresponding to the receiving end according to the node address information, and store the data link relationship in the cache queue 122 of the storage module . That is, the address decoding module reads and decodes the node address information stored in the storage module, and according to the information obtained after decoding the node address information, establishes a data link for the data interface 112 corresponding to the sending end and the data interface 112 corresponding to the receiving end and store the established data link relationship in the cache queue 122 of the storage module for queuing, so as to facilitate subsequent configuration of corresponding data transmission links according to the established data link relationship.

With reference to Fig. 4, the monitoring module 123 wherein is used for monitoring whether there is the idle link that matches the data link relationship in the cache queue 122 in the crossbar matrix 121; The monitoring module 123 is also used for when there is a matching idle link, According to the matching data link relationship, the crossbar switch matrix 121 is controlled to establish a data transmission link for the data interface 112 corresponding to the sending end and the data interface 112 corresponding to the receiving end. That is, the monitoring module 123 monitors whether there is an idle link in the crossbar switch matrix 121 in real time, and also reads the established data link relationship in the cache queue 122 in real time. After an idle link is found, it is judged in real time whether the two nodes connected to the idle link are the same as the two nodes in each data link relationship established in the cache queue 122 . If the judgment result is the same, that is, the two small chips 21 connected in the idle link are the same as the two small chips 21 in the established data link relationship, then it is considered that there is a buffer queue in the crossbar matrix 121 The idle link that matches the data link relationship in 122. Afterwards, the monitoring module 123 controls the crossbar switch matrix 121 to establish a data transmission link for the two chiplets 21 according to the matching data link relationship, and the sending end of the two chiplets 21 sends data to the receiving end. Specifically, the small chip 21 at the sending end needs to prepare the data to be sent, and after the data is prepared, perform data transmission through the configured data transmission link. Through the mutual cooperation of the storage module, the address decoding module and the monitoring module 123, it is convenient to timely find that the established data link relationship and the idle link can match, so as to quickly complete the configuration of the data transmission link. It should be noted that the above only shows a control method for controlling the interface units 11 from different interface groups to establish links so that the two chiplets 21 corresponding to the two interface units 11 can perform data transmission. , it is also possible to use other methods that can enable the two chiplets 21 corresponding to the two interface units 11 to perform data transmission by controlling the interface units 11 of different interface groups to be turned on or off.

When the storage module is set, the storage module can be a static random access memory, so as to increase the reading and writing speed of the interconnection device when configuring the data transmission link, thereby improving the configuration efficiency of the data transmission link and reducing the time delay. It should be understood that the storage module is not limited to the SRAM shown above, and other storage media may also be used as the storage module.

In addition, the interconnection device is not limited to a circuit module formed by a circuit, in addition, an optical module may also be used as the interconnection device.

The chiplets 21 in the chip modules 20 that are plugged into different slots are connected through the interconnection device 10, and the control module 12 of the interconnection device 10 establishes a link for the chiplets 21 in different chip modules 20 to realize the two Data transfer between chiplets 21 . Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each small chip 21 and the interface unit 11 of the interconnection device in the circuit board bus, and it is not necessary to interconnect each small chip 21 and other small chips 21 with other small chips at the board level. The chip 21 reduces the number of lead-out pins on each slot, and at the same time reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board. Moreover, the control module 12 controls the different interface units 11 in the interconnection device 10 to establish links for data transmission. During data transmission, it is less restricted by various protocols inside the chip module 20, so that the interconnection mode has a strong The protocol is insensitive, and it is convenient to extend to the interconnection of different types of chip modules 20 . Moreover, when the two small chips 21 from different chip modules 20 transmit data through the interconnection device 10, they can perform full bandwidth transmission. Significantly reduce delay, facilitate programming and ensure multi-channel performance.

In addition, an embodiment of the present invention also provides a motherboard, which includes a circuit board (not shown in the figure). Specifically, the circuit board may be a printed circuit board, which is used as a carrier for setting various devices, and at the same time realizes the interconnection between different devices through the wiring in it. Referring to FIG. 2 and FIG. 3 , at least two chip modules 20 are arranged on the circuit board, and at least two slots are arranged on the circuit board, and a chip module 20 is plugged into each slot. Wherein, each chip module 20 is provided with at least one small chip 21, and at least one chip module 20 is a multi-chip module comprising at least two small chips 21, and each multi-chip module is provided with at least two small chips twenty one. That is, the number of slots is equal to the number of chip modules 20 . A chip module 20 is plugged into each slot.

When specifically determining the number of chip modules 20 , the number of chip modules 20 may be any value not less than 2, such as 2, 3, 4, 5, 10, or the like. The number of corresponding slots is equal to the number of chip modules 20, and each chip module 20 is plugged into a corresponding slot to realize the wiring connection between the chip module 20 and the circuit board. What is shown in FIG. 2 is the interconnection of two chip modules 20 , and what is shown in FIG. 3 is the interconnection of four chip modules 20 . When determining the type of the chip module 20, the chip module 20 can be a central processing unit, or a dedicated high-performance chip, or a part of the chip module 20 can be a central processing unit, and a part of the chip module 20 can be a dedicated high-performance chip. . The dedicated high-performance chip can specifically be a graphics processor, an artificial intelligence AI (Artificial Intelligence, AI chip for short) chip, a field programmable logic gate array, or an application-specific integrated circuit. More specifically, as shown in Figure 2, two central processing units (CPU0, CPU1) are interconnected, and as shown in Figure 3, two central processing units (CPU0, CPU1), a graphics processing unit (GPU0) A total of four chip modules 20 are interconnected with a field programmable logic gate array (FPGA). Of course, the chip module 20 can also be other types of accelerator cards. When determining the number of small chips 21 contained in each chip module 20, the number of small chips 21 contained in each chip module 20 can be 2, 3, 4, etc. not less than 2 Any value, and at least one chip module 20 is a multi-chip module, and the number of chiplets 21 contained in the multi-chip module is any value not less than 2, such as 2, 3, 4, etc.

Referring to FIG. 2 , an interconnection device 10 is also provided on the motherboard. The interconnection device 10 includes at least two sets of interfaces. Each group of interfaces includes at least one interface unit 11; at least one interface unit 11 of each group of interfaces corresponds to at least one chiplet 21 in the chip module 20 corresponding to the group of interfaces. Each interface unit 11 is connected to a corresponding chiplet 21 . That is, the number of interface groups on the interconnection device 10 is equal to the number of chip modules 20 , and each chip module 20 corresponds to a group of interfaces. The number of chiplets 21 on each chip module 20 is equal to the number of interface units 11 in a group of interfaces corresponding to the chip module 20 . There is also at least two interface units 11 included in at least one group of interfaces, corresponding to at least two chiplets 21 in at least one multi-chip module. Each chiplet 21 is connected to an interface unit 11 .

As shown in Figure 2, the interconnection device 10 also includes a control module 12, the control module 12 is used to establish links for any two interface units 11 from different groups of interfaces, so that the two interface units 11 corresponding to the two small The chip 21 performs data transmission. The chiplets 21 in the chip modules 20 that are plugged into different slots are connected through the interconnection device 10, and the control module 12 of the interconnection device 10 establishes a link for the chiplets 21 in different chip modules 20 to realize the two Data transfer between chiplets 21 . Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each small chip 21 and the interface unit 11 of the interconnection device in the circuit board bus, and it is not necessary to interconnect each small chip 21 and other small chips 21 with other small chips at the board level. The chip 21 reduces the number of lead-out pins on each slot, and at the same time reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board and the manufacturing cost of the main board. Moreover, the control module 12 controls the different interface units 11 in the interconnection device 10 to establish links for data transmission. During data transmission, it is less restricted by various protocols inside the chip module 20, so that the interconnection mode has a strong The protocol is insensitive, and it is convenient to extend to the interconnection of different types of chip modules 20 . Moreover, when the two small chips 21 from different chip modules 20 transmit data through the interconnection device 10, they can perform full bandwidth transmission. Significantly reduce delay, facilitate programming and ensure multi-channel performance.

When specifically setting each interface unit 11, referring to FIG. Wherein, the address and control interface 111 is connected with the address and control interface of the chiplet 21 corresponding to the interface unit 11 , and the data interface 112 is connected with the data interface of the chiplet 21 corresponding to the interface unit 11 . That is to say, each interface unit 11 is divided into address and control interface 111 and data interface 112. The method of separating the control address plane from the data plane is not sensitive to the equipment transmission protocol, and it is convenient for various high-speed modules using the same protocol to form a high-performance system together. . And when performing data transmission between two small chips 21 in different chip modules 20, one small chip 21 first sends the address information of the receiving end small chip 21 to the interconnection device 10, and the interconnection device 10 decodes and configures the link , while the chiplet 21 prepares data. After the chiplet 21 prepares the data to be sent, the data is transmitted through the link configured by the interconnection device 10 at the first time, reducing the delay caused by configuring the link, thereby reducing the delay of the entire system.

When specifically setting the address, control interface and data interface on each small chip 21, with reference to Fig. Both interface and data interface are connected. The interconnection device 10 is not sensitive to various protocols inside each small chip 21 , which facilitates expansion to interconnection of different types of chip modules 20 .

It should be understood that each interface unit 11 is not limited to the above-mentioned arrangement of dividing into an address and control interface 111 and a data interface 112 , and other arrangements can also be adopted. For example, the address and control interface 111 and the data interface 112 can be combined into one interface, and a data transmission mode of sending node address information and data together is adopted.

When specifically setting the control module 12, with reference to Fig. 2 and Fig. 4, the control module 12 may include a storage module (not shown in the figure), a crossbar switch matrix 121, an address decoding module (not shown in the figure) and a monitoring module 123. For ease of description, when any two chiplets 21 in different chip modules 20 transmit data, one of the two chiplets 21 is defined as the sending end, and the other is defined as the receiving end. The storage module in the control module 12 is used to store the node address information of the receiving end transmitted by the sending end through the address and control interface 111 . That is, after the address and control interface 111 in the interface unit 11 corresponding to the sending end receives the node address information of the receiving end transmitted from the sending end, it transfers the node address information to the storage module, so as to facilitate the subsequent processing of the node address information Decode and configure the corresponding data link relationship.

With reference to Fig. 4, the crossbar matrix 121 among them is all connected with each data interface 112, is convenient to realize the interconnection or disconnection between different data interfaces 112 by conducting or disconnecting between different nodes in the crossbar matrix 121. open. The crossbar switch matrix 121 is a switch matrix with switch gating function in the prior art.

The address decoding module is used to establish a data link relationship between the data interface 112 corresponding to the sending end and the data interface 112 corresponding to the receiving end according to the node address information, and store the data link relationship in the cache queue 122 of the storage module . That is, the address decoding module reads and decodes the node address information stored in the storage module, and according to the information obtained after decoding the node address information, establishes a data link for the data interface 112 corresponding to the sending end and the data interface 112 corresponding to the receiving end and store the established data link relationship in the cache queue 122 of the storage module for queuing, so as to facilitate subsequent configuration of corresponding data transmission links according to the established data link relationship.

As shown in Figure 4, the monitoring module 123 wherein is used to monitor whether there is an idle link matching the data link relation in the cache queue 122 in the crossbar matrix 121; When connecting, according to the matching data link relationship, the crossbar switch matrix 121 is controlled to establish a data transmission link for the data interface 112 corresponding to the sending end and the data interface 112 corresponding to the receiving end. That is, the monitoring module 123 monitors whether there is an idle link in the crossbar switch matrix 121 in real time, and also reads the established data link relationship in the cache queue 122 in real time. After an idle link is found, it is judged in real time whether the two nodes connected to the idle link are the same as the two nodes in each data link relationship established in the cache queue 122 . If the judgment result is the same, that is, the two small chips 21 connected in the idle link are the same as the two small chips 21 in the established data link relationship, then it is considered that there is a buffer queue in the crossbar matrix 121 The idle link that matches the data link relationship in 122. Afterwards, the monitoring module 123 controls the crossbar switch matrix 121 to establish a data transmission link for the two chiplets 21 according to the matching data link relationship, and the sending end of the two chiplets 21 sends data to the receiving end. Specifically, the small chip 21 at the sending end needs to prepare the data to be sent, and after the data is prepared, perform data transmission through the configured data transmission link. Through the mutual cooperation of the storage module, the address decoding module and the monitoring module 123, it is convenient to timely find that the established data link relationship and the idle link can match, so as to quickly complete the configuration of the data transmission link. It should be noted that the above only shows a control method for controlling the interface units 11 from different interface groups to establish links so that the two chiplets 21 corresponding to the two interface units 11 can perform data transmission. , it is also possible to use other methods that can enable the two chiplets 21 corresponding to the two interface units 11 to perform data transmission by controlling the interface units 11 of different interface groups to be turned on or off.

When the storage module is set, the storage module can be a static random access memory, so as to increase the reading and writing speed of the interconnection module when configuring the data transmission link, thereby improving the configuration efficiency of the data transmission link and reducing the time delay. It should be understood that the storage module is not limited to the SRAM shown above, and other storage media may also be used as the storage module.

The main data communication scenarios are described below with reference to FIG. 2 , FIG. 4 and FIG. 5 . In application, the main data communication scenarios include broadcast query and directional data query. Firstly, the specific implementation of broadcast query is introduced.

Assume that the chiplet Die0 in the chip module 20 on the left in FIG. 2 acts as the initiator of the broadcast query and needs to query the latest data in the system. The small chip Die0 broadcasts and inquires other small chips Die1, Die2, and Die3 in the same chip module 20 through the internal interconnection mode of the chip module 20, and the query is performed in a conventional manner in the prior art. The chiplet Die0 performs broadcast query to other chiplets Die4 , Die5 , Die6 , and Die7 in different chip modules 20 through the interconnection device 10 provided by this application. When inquiring specifically, first, the small chip Die0 needs to send the node address information of the small chips Die4, Die5, Die6, and Die7 to the interconnection device 10 through its corresponding address and control interface 111, and at the same time prepare the data information that needs to be queried, such as the required data address information, etc. After receiving the node address information sent by the chiplet 21Die0, the interconnection device 10 dumps it into the storage module. Decoding is performed by the decoding module, and the data link relationships of Die0-Die4, Die0-Die5, Die0-Die6, Die0-Die7 are respectively established, and then the established data link relationships are transferred to the cache queue 122 . At the same time, the monitoring module 123 queries the link status in the crossbar switch matrix 121 . If there is an idle link, if the link between Die0 and Die6 is an idle link, then configure the data transmission link of Die0-Die6, and connect the data interface 112 corresponding to Die0 and the data interface 112 corresponding to Die6. After Die0 completes the preparation of the query information, it sends the query information to Die6 for query through the data transmission link of Die0-Die6. If Die6 happens to have the latest data that needs to be queried, the latest data will be passed to Die0 through the established Die0-Die6 data transmission link. If Die6 does not have the latest data, mark the completion of this query. According to the above method, the data query of Die4, Die5, and Die7 are respectively completed in sequence.

The following introduces another common communication application scenario—directed data query. Assume that Die0 queries Die7 for data, and Die7 happens to have the latest data of the query. First, the small chip Die0 needs to send the node address information of the small chip Die7 to the interconnection device 10 through its corresponding address and the control interface 111, and at the same time prepare the address information where the query data on the small chip Die7 needs to be queried. After the interconnection device 10 configures the corresponding data transmission link, the chiplet Die0 sends the prepared address information data where the query data on the chiplet Die7 needs to be queried to the chiplet Die7 through the interconnection device 10 . At this time, referring to FIG. 5 , the basic transmission path is Core00 of Die0 -> internal bus IB0 of Die0 -> IB0 cross-slot access interface of Die0 -> data interface 112 corresponding to Die0 on interconnection device 10 -> interconnection device Data interface 112 corresponding to Die7 -> IB7 cross-slot access interface of Die7 -> internal bus IB7 of Die7 -> memory or cache of Die7. In the small chip, after Die7 receives the address information data where the query data is located, it reads the relevant query data according to the address information data where the query data is located, and transmits the query data to The small chip Die0 completes this directional query. It should be noted that Core00 and Core0n in FIG. 5 respectively represent different cores (Cores) in the chiplet Die0, and Core70 and Core7n respectively represent different cores (Cores) in the chiplet Die7.

In addition, the interconnection device is not limited to a circuit module formed by a circuit, in addition, an optical module may also be used as the interconnection device.

The chiplets 21 in the chip modules 20 that are plugged into different slots are connected through the interconnection device 10, and the control module 12 of the interconnection device 10 establishes a link for the chiplets 21 in different chip modules 20 to realize the two Data transfer between chiplets 21 . Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each small chip 21 and the interface unit 11 of the interconnection device in the circuit board bus, and it is not necessary to interconnect each small chip 21 and other small chips 21 with other small chips at the board level. The chip 21 reduces the number of lead-out pins on each slot, and at the same time reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board and the manufacturing cost of the main board. Moreover, the control module 12 controls the different interface units 11 in the interconnection device 10 to establish links for data transmission. During data transmission, it is less restricted by various protocols inside the chip module 20, so that the interconnection mode has a strong The protocol is insensitive, and it is convenient to extend to the interconnection of different types of chip modules 20 . Moreover, when the two small chips 21 from different chip modules 20 transmit data through the interconnection device 10, they can perform full bandwidth transmission. Significantly reduce delay, facilitate programming and ensure multi-channel performance.

Furthermore, an embodiment of the present invention also provides a server, where the server is any one of the aforementioned motherboards. The small chips in the chip modules inserted in different slots are connected through the interconnection device, and the control module of the interconnection device establishes links for the small chips in different chip modules to realize data transmission between the two small chips . Therefore, when realizing interconnection at the board level, it is only necessary to interconnect each chiplet and the interface unit of the interconnection device on the bus in the circuit board, and there is no need to interconnect each chiplet with other chiplets at the board level, reducing The number of lead-out pins on each slot reduces the difficulty of wiring in the circuit board, thereby reducing the processing cost of the circuit board and the manufacturing cost of the main board. And through the control module to control different interface units in the interconnection device to establish links for data transmission, during data transmission, it is less restricted by various protocols inside the chip module, so the interconnection method has strong protocol insensitivity , easy to expand to different types of chip module interconnection. Moreover, when two small chips from different chip modules transmit data through the interconnection device, they can perform full bandwidth transmission. Compared with the prior art that uses the remote Chiplet as a bridge for interconnection, the solution of this application can greatly reduce Low latency, easy programming and guaranteed multi-channel performance. In turn, the cost of the server is reduced, and the delay of the server is reduced.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. An interconnect device, comprising:

at least two groups of interfaces corresponding to the at least two slots one by one; wherein each slot is inserted with a chip module; at least one small chip is arranged in each chip module, and at least one chip module is a multi-chip module comprising at least two small chips; each set of interfaces comprises at least one interface unit; at least one interface unit of each group of interfaces corresponds to at least one chiplet in the chip module corresponding to the group of interfaces one by one; each interface unit is connected with a corresponding small chip;

and the control module is used for establishing a link for any two interface units from different groups of interfaces so that two chiplets corresponding to the two interface units can perform data transmission.

2. The interconnect device of claim 1, wherein each interface unit includes an address and control interface and a data interface; the address and control interface is connected with the address and control interface of the small chip corresponding to the interface unit, and the data interface is connected with the data interface of the small chip corresponding to the interface unit.

3. The interconnect device of claim 2, wherein when data is transmitted from any two chiplets from different chip modules, one of the two chiplets is a transmitting end and the other is a receiving end;

the control module includes:

the storage module is used for storing node address information of the receiving end, which is transmitted by the transmitting end through an address in an interface unit corresponding to the transmitting end and a control interface;

a crossbar matrix connected to the data interface in each interface unit;

the address decoding module is used for establishing a data link relation for a data interface in the interface unit corresponding to the transmitting end and a data interface in the interface unit corresponding to the receiving end according to the node address information, and storing the data link relation into a cache queue of the storage module;

the monitoring module is used for monitoring whether an idle link matched with the data link relation in the cache queue exists in the cross switch matrix; and the cross switch matrix is also used for controlling the cross switch matrix to establish a data transmission link for the data interface in the corresponding interface unit of the transmitting end and the data interface in the corresponding interface unit of the receiving end according to the matched data link relation when the matched idle link exists.

4. The interconnect device of claim 3, wherein the memory module is a static random access memory.

5. A motherboard, comprising:

a circuit board;

at least two slots arranged on the circuit board;

the chip modules are inserted into each slot, wherein each chip module is provided with at least one small chip, and at least one chip module is a multi-chip module comprising at least two small chips;

an interconnection device disposed on the motherboard, comprising:

at least two groups of interfaces corresponding to the at least two slots one by one; wherein each set of interfaces comprises at least one interface unit; at least one interface unit of each group of interfaces corresponds to at least one chiplet in the chip module corresponding to the group of interfaces one by one; each interface unit is connected with a corresponding small chip;

and the control module is used for establishing a link for any two interface units from different groups of interfaces so that two chiplets corresponding to the two interface units can perform data transmission.

6. The motherboard of claim 5, wherein each chiplet has an address and control interface and a data interface disposed thereon, each interface unit including an address and control interface and a data interface;

The address and control interface is connected with the address and control interface of the small chip corresponding to the interface unit, and the data interface is connected with the data interface of the small chip corresponding to the interface unit.

7. The motherboard of claim 6, wherein when any two chiplets from different chip modules transmit data, one of the two chiplets is a transmitting end and the other is a receiving end;

the control module includes:

the storage module is used for storing node address information of the receiving end, which is transmitted by the transmitting end through an address in an interface unit corresponding to the transmitting end and a control interface;

a crossbar matrix connected to the data interface in each interface unit;

the address decoding module is used for establishing a data link relation for the data interface in the corresponding interface unit and the data interface in the corresponding interface unit of the receiving end according to the node address information, and storing the data link relation into a cache queue of the storage module;

the monitoring module is used for monitoring whether an idle link matched with the data link relation in the cache queue exists in the cross switch matrix; and the cross switch matrix is also used for controlling the cross switch matrix to establish a data transmission link for the data interface in the corresponding interface unit of the transmitting end and the data interface in the corresponding interface unit of the receiving end according to the matched data link relation when the matched idle link exists.

8. The motherboard of claim 6 wherein a data bus is provided in each chiplet and the data bus is connected to both address and control interfaces and data interfaces on the chiplet.

9. Motherboard according to claim 5, characterized in that the chip module is a central processor and/or a dedicated high-performance chip.

10. A server comprising a motherboard according to any of claims 5 to 9.

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