CN118629979A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device comprises: a substrate, wherein a groove is formed in the substrate, and device structures are formed on two sides of the groove; the insulating medium layer is formed on the inner wall of the groove; a polysilicon structure filled in the trench; and the polysilicon structure is electrically led out through the metal interconnection structure. The technical scheme of the invention can reduce the leakage risk between adjacent device structures.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof.

Background Art

In semiconductor devices, taking NMOS devices as an example, the substrate has its own P-type light doping, a gate layer is formed on the substrate, and N-type source/drain regions are formed in the substrate on both sides of the gate layer. Adjacent device structures are mainly isolated by shallow trench isolation structures; at the same time, the NPN structure formed by the source/drain regions on both sides of the shallow trench isolation structure and the substrate can also play a certain isolation role.

However, when the substrate is etched by dry etching to form trenches corresponding to the shallow trench isolation structure, the substrate surface between adjacent trenches will be damaged, resulting in defects on the substrate surface, which in turn increases the probability of electrons passing through the shallow trench isolation structure, that is, a leakage channel is formed, which reduces the isolation effect of the shallow trench isolation structure; at the same time, the source/drain region and the gate layer will be led out through the metal interconnection structure to apply voltage to the device structure through the metal interconnection structure. When there is a potential difference between two adjacent device structures, the metal interconnection structure located above the shallow trench isolation structure will induce a weak electron channel in the substrate on the inner wall of the shallow trench isolation structure, thereby weakening the isolation effect. Therefore, the above factors lead to an increase in the risk of leakage between adjacent device structures.

Therefore, how to reduce the leakage risk between adjacent device structures is an issue that needs to be urgently addressed.

Summary of the invention

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to reduce the risk of leakage between adjacent device structures.

To achieve the above object, the present invention provides a semiconductor device, comprising:

A substrate, wherein a trench is formed in the substrate, and device structures are formed on both sides of the trench;

an insulating dielectric layer formed on the inner wall of the groove;

A polysilicon structure filled in the trench;

A metal interconnect structure, through which the polysilicon structure is electrically led out.

Optionally, there is a potential difference between the substrate and the polysilicon structure, so that a strong polysilicon sublayer is formed in the substrate on the inner wall of the trench.

Optionally, the doping type of the region where the strong multi-sublayer is located is the same as the doping type of the substrate, and the majority carrier concentration in the strong multi-sublayer is greater than the majority carrier concentration in the substrate.

Optionally, the device structure is an intrinsic device.

Optionally, the device structure includes:

A gate structure formed on the substrate at both sides of the trench;

A first source/drain region and a second source/drain region are respectively formed in the substrate at both sides of the gate structure.

Optionally, the doping types of the first source/drain region and the second source/drain region are opposite to the doping type of the region where the strong multi-sublayer is located, so that the first source/drain region and the second source/drain region on both sides of the trench form an NPN isolation structure or a PNP isolation structure with the strong multi-sublayer.

Optionally, when the doping type of the first source/drain region and the second source/drain region is N-type and the doping type of the region where the strong poly-sublayer is located is P-type, the potential applied to the substrate is greater than the potential applied to the polysilicon structure.

Optionally, the polysilicon structure is connected to a negative potential, and the substrate is grounded; or, the polysilicon structure is grounded, and the substrate is connected to a positive potential.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

providing a substrate;

forming a trench in the substrate;

forming an insulating dielectric layer on the inner wall of the trench;

Filling a polysilicon structure in the trench;

forming a device structure on both sides of the trench;

A metal interconnection structure is formed on the polysilicon structure, and the polysilicon structure is electrically led out through the metal interconnection structure.

Optionally, there is a potential difference between the substrate and the polysilicon structure, so that a strong polysilicon sublayer is formed in the substrate on the inner wall of the trench.

Optionally, the doping type of the region where the strong multi-sublayer is located is the same as the doping type of the substrate, and the majority carrier concentration in the strong multi-sublayer is greater than the majority carrier concentration in the substrate.

Optionally, the device structure is an intrinsic device.

Optionally, the step of forming a device structure on both sides of the trench includes:

forming a gate structure on the substrate at both sides of the trench;

A first source/drain region and a second source/drain region are respectively formed in the substrate at both sides of the gate structure.

Optionally, the doping types of the first source/drain region and the second source/drain region are opposite to the doping type of the region where the strong multi-sublayer is located, so that the first source/drain region and the second source/drain region on both sides of the trench form an NPN isolation structure or a PNP isolation structure with the strong multi-sublayer.

Optionally, when the doping type of the first source/drain region and the second source/drain region is N-type and the doping type of the region where the strong poly-sublayer is located is P-type, the potential applied to the substrate is greater than the potential applied to the polysilicon structure.

Optionally, the polysilicon structure is connected to a negative potential, and the substrate is grounded; or, the polysilicon structure is grounded, and the substrate is connected to a positive potential.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

1. The semiconductor device of the present invention comprises: a substrate having a groove formed therein, and device structures formed on both sides of the groove; an insulating dielectric layer formed on the inner wall of the groove; a polysilicon structure filled in the groove; and a metal interconnect structure, through which the polysilicon structure is electrically led out, so that the risk of leakage between adjacent device structures can be reduced.

2. The method for manufacturing a semiconductor device of the present invention comprises: providing a substrate; forming a groove in the substrate; forming an insulating dielectric layer on the inner wall of the groove; filling a polysilicon structure in the groove; forming a device structure on both sides of the groove; forming a metal interconnection structure on the polysilicon structure, wherein the polysilicon structure is electrically led out through the metal interconnection structure, so that the risk of leakage between adjacent device structures can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

3 to 7 are schematic diagrams of devices of a method for manufacturing the semiconductor device shown in FIG. 2 .

The reference numerals of Figures 1 to 7 are described as follows:

10 - substrate; 11 - trench; 12 - insulating dielectric layer; 13 - polysilicon structure; 14 - gate structure; 141 - gate layer; 142 - sidewall; 15 - first source/drain region; 16 - second source/drain region; 17 - conductive plug.

DETAILED DESCRIPTION

In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

An embodiment of the present invention provides a semiconductor device, comprising: a substrate having a groove formed therein, with device structures formed on both sides of the groove; an insulating dielectric layer formed on the inner wall of the groove; a polysilicon structure filled in the groove; and a metal interconnect structure, through which the polysilicon structure is electrically led out.

The semiconductor device provided by this embodiment is described in more detail below with reference to FIG. 1 . FIG. 1 is a schematic longitudinal cross-sectional view of the semiconductor device.

The substrate 10 has a groove 11 formed therein.

The material of the substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III/V or II/VI compound semiconductors, and can also include a layered substrate such as Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator, and can also include other materials besides semiconductor materials.

In one embodiment, the substrate 10 itself has doping ions with a very low concentration.

The substrate 10 on both sides of the trench 11 is an active area, and the active area can be surrounded by the trench 11 .

Well regions (not shown) may or may not be formed in the substrate 10 on both sides of the trench 11 . The doping type of the well region is the same as that of the substrate 10 , and the doping concentration of the well region is greater than that of the substrate 10 .

Device structures are formed on both sides of the trench 11. When no well regions are formed in the substrate 10 on both sides of the trench 11, the device structures on both sides of the trench 11 are intrinsic devices.

The device structure comprises:

A gate structure 14 is formed on the substrate 10 at both sides of the trench 11;

A first source/drain region 15 and a second source/drain region 16 are respectively formed in the substrate 10 at both sides of the gate structure 14 .

The gate structure 14 may include a gate dielectric layer (not shown), a gate layer 141 and a sidewall 142 . The gate dielectric layer and the gate layer 141 are formed on the substrate 10 from bottom to top, and the sidewall 142 is formed on the sidewalls of the gate dielectric layer and the gate layer 141 .

The first source/drain region 15 and the second source/drain region 16 may contact the trench 11 , and the first source/drain region 15 and the second source/drain region 16 may extend from the substrate 10 at both sides of the gate structure 14 to the substrate 10 below the spacer 142 .

When the first source/drain region 15 is a source region, the second source/drain region 16 is a drain region; when the first source/drain region 15 is a drain region, the second source/drain region 16 is a source region.

The doping type of the substrate 10 is opposite to the doping type of the first source/drain region 15 and the second source/drain region 16, so that the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 and the substrate 10 on the inner wall of the trench 11 can form an NPN isolation structure or a PNP isolation structure similar to a triode, so as to isolate the device structure on both sides of the trench 11. The doping concentration of the first source/drain region 15 and the second source/drain region 16 is greater than the doping concentration of the substrate 10. In some embodiments, the substrate 10 may be undoped, but a well region is formed in the substrate 10.

The insulating dielectric layer 12 is formed on the inner wall of the trench 11 .

The gate dielectric layer, the sidewall spacer 142 and the insulating dielectric layer 12 may be made of at least one insulating material selected from the group consisting of silicon oxide, silicon oxynitride and silicon nitride.

The polysilicon structure 13 is filled in the trench 11 .

The insulating dielectric layer 12 and the polysilicon structure 13 in the trench 11 can achieve physical isolation between the device structures on both sides of the trench 11 .

Furthermore, the polysilicon structure 13, the insulating dielectric layer 12 and the substrate 10 can be used to form a capacitor isolation structure, wherein the polysilicon structure 13 and the substrate 10 are respectively two electrode plates of the capacitor isolation structure, and the insulating dielectric layer 12 is the dielectric of the capacitor isolation structure.

The top surfaces of the insulating dielectric layer 12 and the polysilicon structure 13 may be higher or lower than the top surface of the substrate 10 , or the top surfaces of the insulating dielectric layer 12 and the polysilicon structure 13 may be flush with the top surface of the substrate 10 .

The metal interconnection structure is formed on the polysilicon structure 13, and the polysilicon structure 13 is electrically led out through the metal interconnection structure.

The metal interconnection structure may also be formed on the first source/drain region 15, the second source/drain region 16 and the gate layer 141, and the first source/drain region 15, the second source/drain region 16, the polysilicon structure 13 and the metal interconnection structure on the gate layer 141 may not be electrically connected.

The metal interconnect structure may include one or more stacked metal layers (not shown); when the metal interconnect structure includes multiple stacked metal layers, a conductive plug 17 is formed between adjacent metal layers; the bottom metal layer is also electrically connected to the first source/drain region 15, the second source/drain region 16, the polysilicon structure 13 and the gate layer 141 through the conductive plug 17, so that an electric potential can be applied to the first source/drain region 15, the second source/drain region 16, the polysilicon structure 13 and the gate layer 141 through the metal interconnect structure; in some embodiments, the metal interconnect structure may not contain a metal layer, and only rely on the conductive plug 17 to lead out the related structure.

The semiconductor device also includes: an interlayer dielectric layer (not shown), formed on the substrate 10, the interlayer dielectric layer covers the first source/drain region 15, the second source/drain region 16, the insulating dielectric layer 12, the polysilicon structure 13 and the gate structure, the metal interconnect structure is formed in the interlayer dielectric layer, and the interlayer dielectric layer exposes or leads out the topmost metal layer.

In one embodiment, when the semiconductor device is in a working state, when an electric potential is applied to any structure in the first source/drain region 15, the second source/drain region 16 and the gate layer 141 through the metal interconnect structure, so that there is a potential difference between the device structures on both sides of the trench 11, the metal interconnect structure located above the trench 11 will induce a carrier channel in the substrate 10 on the inner wall of the trench 11, and the carrier channel weakens the isolation effect of the NPN isolation structure or the PNP isolation structure formed by the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 and the substrate 10 on the inner wall of the trench 11.

It should be noted that the electrical connection method of the first source/drain region 15 , the second source/drain region 16 and the gate layer 141 is not limited, as long as a potential difference can exist between the device structures on both sides of the trench 11 .

There is a potential difference between the substrate 10 and the polysilicon structure 13, so that a strong polysilicon sublayer is formed in the substrate 10 on the inner wall of the trench 11. Since the polysilicon structure 13 is electrically led out through the metal interconnect structure, a potential difference can be formed between the substrate 10 and the polysilicon structure 13 by applying different potentials to the substrate 10 and the metal interconnect structure.

In some embodiments, the strong multi-layer extends from the lower surface of the first source/drain region 15 on one side of the groove 11 along the inner wall of the groove 11 to the lower surface of the second source/drain region 16 on the other side of the groove 11, and the doping types of the first source/drain region 15 and the second source/drain region 16 are opposite to the doping types of the region where the strong multi-layer is located, so that the first source/drain region 15 and the second source/drain region 16 on both sides of the groove 11 and the strong multi-layer form an NPN isolation structure or a PNP isolation structure similar to a transistor, so as to isolate the device structure on both sides of the groove 11.

It should be noted that in the NPN isolation structure or PNP isolation structure formed by the first source/drain region 15, the second source/drain region 16 and the substrate 10 on the inner wall of the groove 11, and in the NPN isolation structure or PNP isolation structure formed by the first source/drain region 15, the second source/drain region 16 and the strong multi-sublayer, N and P are doping types.

The doping type of the substrate 10 is the same as the doping type of the region where the strong multi-sublayer is located. Since the doping ions in the substrate 10 are inherent, the doping ion concentration in the substrate 10 is very low, and the multi-sublayer concentration in the substrate 10 is very low. The multi-sublayer in the strong multi-sublayer is generated by applying a potential difference between the substrate 10 and the polysilicon structure 13, and the multi-sublayer concentration in the strong multi-sublayer can reach a very high value. Therefore, the multi-sublayer concentration in the strong multi-sublayer is greater than the multi-sublayer concentration in the substrate 10, so that the first source/drain region 15 and the second multi-sublayer on both sides of the trench 11 are The isolation capability of the NPN isolation structure or PNP isolation structure formed by the source/drain region 16 and the strong multi-sublayer is stronger than the isolation capability of the NPN isolation structure or PNP isolation structure formed by the first source/drain region 15 and the second source/drain region 16 and the substrate 10 on both sides of the groove 11, that is, by forming the strong multi-sublayer in the substrate 10 on the inner wall of the groove 11, the isolation effect between the device structures on both sides of the groove 11 can be significantly enhanced, the influence of the carrier channel on the isolation effect is eliminated, and the leakage risk between adjacent device structures is significantly reduced. In particular, when the device structures on both sides of the groove 11 are intrinsic devices, the formation of the strong multi-sublayer can make the isolation effect between the intrinsic devices on both sides of the groove 11 better.

It should be noted that the strong majority sublayer refers to a larger majority sublayer concentration; wherein, when the doping type of the substrate 10 is P-type, the hole concentration in the strong majority sublayer is greater than the hole concentration in the substrate 10; when the doping type of the substrate 10 is N-type, the electron concentration in the strong majority sublayer is greater than the electron concentration in the substrate 10.

In one embodiment, when the doping type of the first source/drain region 15 and the second source/drain region 16 is N-type, and the doping type of the substrate 10 and the region where the strong multi-sublayer is located is P-type, the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form an NPN isolation structure with the substrate 10, and the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form an NPN isolation structure with the strong multi-sublayer. Wherein, by applying a potential greater than the potential applied to the polysilicon structure 13, an electric field is formed in the direction of the substrate 10 pointing to the polysilicon structure 13, thereby causing the electrons in the substrate 10 to move in the direction of the substrate 10 away from the polysilicon structure 13, so that the majority electrons in the substrate 10 on the inner wall of the trench 11 are holes, that is, the P-type strong multi-sublayer is formed in the substrate 10 on the inner wall of the trench 11. In other embodiments, when the doping type of the first source/drain region 15 and the second source/drain region 16 is P-type, and the doping type of the substrate 10 and the region where the strong multi-layer is located is N-type, the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form a PNP isolation structure with the substrate 10, and the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form a PNP isolation structure with the strong multi-layer.

In some embodiments, in order to make the potential applied to the substrate 10 greater than the potential applied to the polysilicon structure 13, the polysilicon structure 13 is connected to a negative potential, and the substrate 10 is grounded/not connected to a potential (floating); alternatively, the polysilicon structure 13 is grounded, and the substrate 10 is connected to a positive potential.

From the above content, it can be known that since the polysilicon structure 13 is formed in the groove 11, and the polysilicon structure 13 is electrically led out through the metal interconnection structure, it is possible to form the strong polysilicon layer in the substrate 10 on the inner wall of the groove 11 by applying an electric potential difference between the substrate 10 and the polysilicon structure 13, thereby improving the isolation effect between the device structures on both sides of the groove 11, so that there is no need to increase the width of the groove 11 to improve the isolation effect between the device structures on both sides of the groove 11, but the width of the groove 11 can be reduced, so that the spacing between adjacent device structures can be reduced, thereby improving the integration of the device; and, as the process node continues to decrease, the spacing between adjacent device structures continues to decrease, that is, the width of the groove 11 continues to decrease. If the ion implantation process is directly used on the inner wall of the groove 11 An ion implantation region with a doping type opposite to that of the first source/drain region 15 and the second source/drain region 16 is formed in the substrate 10. Since the line width of the ion implantation region is very small, it is difficult to control the range of the ion implantation, and the annealing process after the ion implantation has a great influence on the morphology of the ion implantation region, which results in the formed ion implantation region being unable to meet the isolation requirements, thereby affecting the isolation effect. In the present invention, the position of the shallow trench isolation structure is replaced with the insulating dielectric layer 12 and the polysilicon structure 13, so that by applying a potential difference between the substrate 10 and the polysilicon structure 13, the strong multi-sublayer with a doping type opposite to that of the first source/drain region 15 and the second source/drain region 16 can be formed in the substrate 10 on the inner wall of the trench 11, and then the range of the strong multi-sublayer can be controlled by controlling the size of the potential difference, so that the isolation effect is not affected by the reduction of the process node.

In summary, the semiconductor device provided by the present invention comprises: a substrate, a groove is formed in the substrate, and device structures are formed on both sides of the groove; an insulating dielectric layer is formed on the inner wall of the groove; a polysilicon structure is filled in the groove; and a metal interconnection structure, and the polysilicon structure is electrically led out through the metal interconnection structure. The semiconductor device of the present invention can reduce the risk of leakage between adjacent device structures.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 2 , FIG. 2 is a flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device includes:

Step S1, providing a substrate;

Step S2, forming a groove in the substrate;

Step S3, forming an insulating dielectric layer on the inner wall of the trench;

Step S4, filling a polysilicon structure in the trench;

Step S5, forming a device structure on both sides of the trench;

Step S6: forming a metal interconnection structure on the polysilicon structure, and electrically leading out the polysilicon structure through the metal interconnection structure.

The method for manufacturing the semiconductor device provided in this embodiment is described in more detail below with reference to FIGS. 3 to 7 . FIGS. 3 to 7 are schematic longitudinal cross-sectional views of the semiconductor device.

According to step S1, a substrate 10 is provided.

The material of the substrate 10 can be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III/V or II/VI compound semiconductors, and can also include a layered substrate such as Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator, and can also include other materials besides semiconductor materials.

In one embodiment, the substrate 10 itself has doping ions with a very low concentration.

According to step S2 , referring to FIG. 3 , a trench 11 is formed in the substrate 10 .

The groove 11 may be formed by etching the substrate 10 .

The substrate 10 on both sides of the trench 11 is an active area, and the active area can be surrounded by the trench 11 .

Well regions (not shown) may or may not be formed in the substrate 10 on both sides of the trench 11 . The doping type of the well region is the same as that of the substrate 10 , and the doping concentration of the well region is greater than that of the substrate 10 .

According to step S3 , referring to FIG. 4 , an insulating dielectric layer 12 is formed on the inner wall of the trench 11 .

The insulating dielectric layer 12 may also be formed on the substrate 10 outside the trench 11 .

According to step S4 , referring to FIG. 5 , a polysilicon structure 13 is filled in the trench 11 .

When filling the polysilicon structure 13 in the groove 11, the polysilicon structure 13 can also cover the insulating dielectric layer 12 outside the groove 11. Then, a chemical mechanical polishing process or an etching process can be used to remove the insulating dielectric layer 12 and the polysilicon structure 13 on the substrate 10 outside the groove 11. The top surfaces of the remaining insulating dielectric layer 12 and the polysilicon structure 13 can be higher or lower than the top surface of the substrate 10, or the top surfaces of the remaining insulating dielectric layer 12 and the polysilicon structure 13 can be flush with the top surface of the substrate 10.

According to step S5 , device structures are formed on both sides of the trench 11 .

When no well region is formed in the substrate 10 at both sides of the trench 11 , the device structures at both sides of the trench 11 are intrinsic devices.

6 , the step of forming the device structure on both sides of the trench 11 may include: first, forming a gate structure on the substrate 10 on both sides of the trench 11; and then, respectively forming a first source/drain region 15 and a second source/drain region 16 in the substrate 10 on both sides of the gate structure.

The gate structure 14 may include a gate dielectric layer (not shown), a gate layer 141 and a sidewall 142 . The gate dielectric layer and the gate layer 141 are formed on the substrate 10 from bottom to top, and the sidewall 142 is formed on the sidewalls of the gate dielectric layer and the gate layer 141 .

The gate dielectric layer, the sidewall spacer 142 and the insulating dielectric layer 12 may be made of at least one insulating material selected from the group consisting of silicon oxide, silicon oxynitride and silicon nitride.

The first source/drain region 15 and the second source/drain region 16 may contact the trench 11 , and the first source/drain region 15 and the second source/drain region 16 may extend from the substrate 10 at both sides of the gate structure 14 to the substrate 10 below the spacer 142 .

When the first source/drain region 15 is a source region, the second source/drain region 16 is a drain region; when the first source/drain region 15 is a drain region, the second source/drain region 16 is a source region.

The doping type of the substrate 10 is opposite to the doping type of the first source/drain region 15 and the second source/drain region 16, so that the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 and the substrate 10 on the inner wall of the trench 11 can form an NPN isolation structure or a PNP isolation structure similar to a triode, so as to isolate the device structure on both sides of the trench 11. The doping concentration of the first source/drain region 15 and the second source/drain region 16 is greater than the doping concentration of the substrate 10. In some embodiments, the substrate 10 may be undoped, but a well region is formed in the substrate 10.

The insulating dielectric layer 12 and the polysilicon structure 13 in the trench 11 can achieve physical isolation between the device structures on both sides of the trench 11 .

Furthermore, the polysilicon structure 13, the insulating dielectric layer 12 and the substrate 10 can be used to form a capacitor isolation structure, wherein the polysilicon structure 13 and the substrate 10 are respectively two electrode plates of the capacitor isolation structure, and the insulating dielectric layer 12 is the dielectric of the capacitor isolation structure.

According to step S6, a metal interconnection structure is formed on the polysilicon structure, and the polysilicon structure is electrically led out through the metal interconnection structure.

The metal interconnection structure may also be formed on the first source/drain region 15, the second source/drain region 16 and the gate layer 141, and the first source/drain region 15, the second source/drain region 16, the polysilicon structure 13 and the metal interconnection structure on the gate layer 141 may not be electrically connected.

The metal interconnect structure may include one or more stacked metal layers (not shown); when the metal interconnect structure includes multiple stacked metal layers, conductive plugs 17 are formed between adjacent metal layers; as shown in FIG7 , the bottom metal layer is also electrically connected to the first source/drain region 15, the second source/drain region 16, the polysilicon structure 13, and the gate layer 141 through the conductive plugs 17, so that an electric potential can be applied to the first source/drain region 15, the second source/drain region 16, the polysilicon structure 13, and the gate layer 141 through the metal interconnect structure. In some embodiments, the metal interconnect structure may also not contain a metal layer, and only the conductive plugs 17 are used to lead out the related structures.

The method for manufacturing the semiconductor device also includes: forming an interlayer dielectric layer (not shown), the interlayer dielectric layer is formed on the substrate 10, the interlayer dielectric layer covers the first source/drain region 15, the second source/drain region 16, the insulating dielectric layer 12, the polysilicon structure 13 and the gate structure, the metal interconnect structure is formed in the interlayer dielectric layer, and the interlayer dielectric layer exposes or leads out the topmost metal layer.

In one embodiment, in the working state of the semiconductor device, when an electric potential is applied to any structure in the first source/drain region 15, the second source/drain region 16 and the gate layer 141 through the metal interconnect structure, so that there is a potential difference between the device structures on both sides of the trench 11, the metal interconnect structure located above the trench 11 will induce the formation of a carrier channel in the substrate 10 on the inner wall of the trench 11, and the carrier channel weakens the isolation effect of the NPN isolation structure or the PNP isolation structure formed by the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 and the substrate 10 on the inner wall of the trench 11.

It should be noted that the electrical connection method of the first source/drain region 15 , the second source/drain region 16 and the gate layer 141 is not limited, as long as a potential difference can exist between the device structures on both sides of the trench 11 .

There is a potential difference between the substrate 10 and the polysilicon structure 13, so that a strong polysilicon sublayer is formed in the substrate 10 on the inner wall of the trench 11. Since the polysilicon structure 13 is electrically led out through the metal interconnect structure, a potential difference can be formed between the substrate 10 and the polysilicon structure 13 by applying different potentials to the substrate 10 and the metal interconnect structure.

In some embodiments, the strong multi-layer extends from the lower surface of the first source/drain region 15 on one side of the groove 11 along the inner wall of the groove 11 to the lower surface of the second source/drain region 16 on the other side of the groove 11, and the doping types of the first source/drain region 15 and the second source/drain region 16 are opposite to the doping types of the region where the strong multi-layer is located, so that the first source/drain region 15 and the second source/drain region 16 on both sides of the groove 11 and the strong multi-layer form an NPN isolation structure or a PNP isolation structure similar to a transistor, so as to isolate the device structure on both sides of the groove 11.

It should be noted that in the NPN isolation structure or PNP isolation structure formed by the first source/drain region 15, the second source/drain region 16 and the substrate 10 on the inner wall of the groove 11, and in the NPN isolation structure or PNP isolation structure formed by the first source/drain region 15, the second source/drain region 16 and the strong multi-sublayer, N and P are doping types.

The doping type of the substrate 10 is the same as the doping type of the region where the strong multi-sublayer is located. Since the doping ions in the substrate 10 are inherent, the doping ion concentration in the substrate 10 is very low, and the multi-sublayer concentration in the substrate 10 is very low. The multi-sublayer in the strong multi-sublayer is generated by applying a potential difference between the substrate 10 and the polysilicon structure 13, and the multi-sublayer concentration in the strong multi-sublayer can reach a very high value. Therefore, the multi-sublayer concentration in the strong multi-sublayer is greater than the multi-sublayer concentration in the substrate 10, so that the first source/drain region 15 and the second multi-sublayer on both sides of the trench 11 are The isolation capability of the NPN isolation structure or PNP isolation structure formed by the source/drain region 16 and the strong multi-sublayer is stronger than the isolation capability of the NPN isolation structure or PNP isolation structure formed by the first source/drain region 15 and the second source/drain region 16 and the substrate 10 on both sides of the groove 11, that is, by forming the strong multi-sublayer in the substrate 10 on the inner wall of the groove 11, the isolation effect between the device structures on both sides of the groove 11 can be significantly enhanced, the influence of the carrier channel on the isolation effect is eliminated, and the leakage risk between adjacent device structures is significantly reduced. In particular, when the device structures on both sides of the groove 11 are intrinsic devices, the formation of the strong multi-sublayer can make the isolation effect between the intrinsic devices on both sides of the groove 11 better.

It should be noted that the strong majority sublayer refers to a larger majority sublayer concentration; wherein, when the doping type of the substrate 10 is P-type, the hole concentration in the strong majority sublayer is greater than the hole concentration in the substrate 10; when the doping type of the substrate 10 is N-type, the electron concentration in the strong majority sublayer is greater than the electron concentration in the substrate 10.

In one embodiment, when the doping type of the first source/drain region 15 and the second source/drain region 16 is N-type, and the doping type of the substrate 10 and the region where the strong multi-sublayer is located is P-type, the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form an NPN isolation structure with the substrate 10, and the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form an NPN isolation structure with the strong multi-sublayer. Wherein, by applying a potential greater than the potential applied to the polysilicon structure 13, an electric field is formed in which the substrate 10 points to the direction of the polysilicon structure 13, thereby causing the electrons in the substrate 10 to move in the direction in which the substrate 10 is away from the polysilicon structure 13, so that the majority electrons in the substrate 10 on the inner wall of the trench 11 are holes, that is, the P-type strong multi-sublayer is formed in the substrate 10 on the inner wall of the trench 11. In other embodiments, when the doping type of the first source/drain region 15 and the second source/drain region 16 is P-type, and the doping type of the substrate 10 and the region where the strong multi-layer is located is N-type, the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form a PNP isolation structure with the substrate 10, and the first source/drain region 15 and the second source/drain region 16 on both sides of the trench 11 form a PNP isolation structure with the strong multi-layer.

In some embodiments, in order to make the potential applied to the substrate 10 greater than the potential applied to the polysilicon structure 13, the polysilicon structure 13 is connected to a negative potential, and the substrate 10 is grounded/not connected to a potential (floating); alternatively, the polysilicon structure 13 is grounded, and the substrate 10 is connected to a positive potential.

From the above content, it can be known that since the polysilicon structure 13 is formed in the groove 11, and the polysilicon structure 13 is electrically led out through the metal interconnection structure, it is possible to form the strong polysilicon layer in the substrate 10 on the inner wall of the groove 11 by applying an electric potential difference between the substrate 10 and the polysilicon structure 13, thereby improving the isolation effect between the device structures on both sides of the groove 11, so that there is no need to increase the width of the groove 11 to improve the isolation effect between the device structures on both sides of the groove 11, but the width of the groove 11 can be reduced, so that the spacing between adjacent device structures can be reduced, thereby improving the integration of the device; and, as the process node continues to decrease, the spacing between adjacent device structures continues to decrease, that is, the width of the groove 11 continues to decrease. If the ion implantation process is directly used on the inner wall of the groove 11, the ion implantation process can be directly used on the inner wall of the groove 11. An ion implantation region with a doping type opposite to that of the first source/drain region 15 and the second source/drain region 16 is formed in the substrate 10. Since the line width of the ion implantation region is very small, it is difficult to control the range of the ion implantation, and the annealing process after the ion implantation has a great influence on the morphology of the ion implantation region, which results in the formed ion implantation region being unable to meet the isolation requirements, thereby affecting the isolation effect. In the present invention, the position of the shallow trench isolation structure is replaced with the insulating dielectric layer 12 and the polysilicon structure 13, so that by applying a potential difference between the substrate 10 and the polysilicon structure 13, the strong multi-sublayer with a doping type opposite to that of the first source/drain region 15 and the second source/drain region 16 can be formed in the substrate 10 on the inner wall of the trench 11, and then the range of the strong multi-sublayer can be controlled by controlling the size of the potential difference, so that the isolation effect is not affected by the reduction of the process node.

In summary, the method for manufacturing a semiconductor device provided by the present invention comprises: providing a substrate; forming a groove in the substrate; forming an insulating dielectric layer on the inner wall of the groove; filling a polysilicon structure in the groove; forming a device structure on both sides of the groove; forming a metal interconnection structure on the polysilicon structure, and the polysilicon structure is electrically led out through the metal interconnection structure. The method for manufacturing a semiconductor device of the present invention can reduce the risk of leakage between adjacent device structures.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims (16)

1. A semiconductor device, comprising: A substrate, wherein a groove is formed in the substrate, and device structures are formed on both sides of the groove; an insulating dielectric layer formed on the inner wall of the groove; A polysilicon structure filled in the trench; A metal interconnect structure, through which the polysilicon structure is electrically led out. 2. The semiconductor device according to claim 1, characterized in that there is a potential difference between the substrate and the polysilicon structure, so that a strong polysilicon layer is formed in the substrate on the inner wall of the trench. 3. The semiconductor device as described in claim 2 is characterized in that the doping type of the region where the strong multi-sublayer is located is the same as the doping type of the substrate, and the majority carrier concentration in the strong multi-sublayer is greater than the majority carrier concentration in the substrate. 4 . The semiconductor device according to claim 1 , wherein the device structure is an intrinsic device. 5. The semiconductor device according to claim 2, wherein the device structure comprises: A gate structure formed on the substrate at both sides of the trench; A first source/drain region and a second source/drain region are respectively formed in the substrate at both sides of the gate structure. 6. The semiconductor device as described in claim 5 is characterized in that the doping types of the first source/drain region and the second source/drain region are opposite to the doping type of the region where the strong multi-sublayer is located, so that the first source/drain region and the second source/drain region on both sides of the groove form an NPN isolation structure or a PNP isolation structure with the strong multi-sublayer. 7. The semiconductor device as described in claim 6 is characterized in that the doping type of the first source/drain region and the second source/drain region is N-type, and the doping type of the region where the strong polysilicon sublayer is located is P-type, and the potential applied to the substrate is greater than the potential applied to the polysilicon structure. 8. The semiconductor device according to claim 7, characterized in that the polysilicon structure is connected to a negative potential and the substrate is grounded; or, the polysilicon structure is grounded and the substrate is connected to a positive potential. 9. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a trench in the substrate; forming an insulating dielectric layer on the inner wall of the trench; Filling a polysilicon structure in the trench; forming a device structure on both sides of the trench; A metal interconnection structure is formed on the polysilicon structure, and the polysilicon structure is electrically led out through the metal interconnection structure. 10. The method for manufacturing a semiconductor device according to claim 9, wherein there is a potential difference between the substrate and the polysilicon structure, so that a strong polysilicon layer is formed in the substrate on the inner wall of the trench. 11. The method for manufacturing a semiconductor device as described in claim 10 is characterized in that the doping type of the region where the strong multi-sublayer is located is the same as the doping type of the substrate, and the majority carrier concentration in the strong multi-sublayer is greater than the majority carrier concentration in the substrate. 12 . The method for manufacturing a semiconductor device according to claim 9 , wherein the device structure is an intrinsic device. 13. The method for manufacturing a semiconductor device according to claim 10, wherein the step of forming a device structure on both sides of the trench comprises: forming a gate structure on the substrate at both sides of the trench; A first source/drain region and a second source/drain region are respectively formed in the substrate at both sides of the gate structure. 14. The method for manufacturing a semiconductor device as described in claim 13 is characterized in that the doping types of the first source/drain region and the second source/drain region are opposite to the doping type of the region where the strong multi-sublayer is located, so that the first source/drain region and the second source/drain region on both sides of the groove form an NPN isolation structure or a PNP isolation structure with the strong multi-sublayer. 15. The method for manufacturing a semiconductor device as described in claim 14 is characterized in that when the doping type of the first source/drain region and the second source/drain region is N-type and the doping type of the region where the strong poly-sublayer is located is P-type, the potential applied to the substrate is greater than the potential applied to the polysilicon structure. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the polysilicon structure is connected to a negative potential and the substrate is grounded; or, the polysilicon structure is grounded and the substrate is connected to a positive potential.