CN118553792A - A SiC MOSFET device with low on-resistance and preparation method thereof - Google Patents

Abstract

The present invention relates to the technical field of semiconductor devices, and specifically discloses a SiC MOSFET device and a preparation method, wherein the device comprises: a metal drain, an N+ type substrate; an N+ type buffer layer, two N-type drift regions, two N-type carrier storage layers, and two P-wells; a P+ type doped region and an N+ type doped region respectively located on the two P-wells; a groove located between the two N+ type doped regions, the P-well, the N-type carrier storage layer, and the N-type drift region; a gate located in the groove; a gate oxide layer located at the outside and bottom of the gate; N-type doped regions and P-type doped regions arranged alternately laterally below the gate; another N+ type doped region located at the top of the middle N-type doped region; another P-well located at the top of the P-type doped region; a metal source located in the groove and at the top of the groove; and an oxide layer located in the groove and at the top of the groove to isolate the polysilicon gate and the metal source. The technical solution of the present invention can effectively reduce the total on-resistance and improve the overall performance.

Description

A SiC MOSFET device with low on-resistance and preparation method thereof

Technical Field

The present invention relates to the technical field of semiconductor devices, and in particular to a SiC MOSFET device with low on-resistance and a preparation method thereof.

Background Art

As a third-generation semiconductor, silicon carbide (SiC) material has excellent physical and electrical properties, a large bandgap, a high breakdown field strength, and good thermal conductivity. Power electronic devices based on SiC materials have great development potential in the fields of high temperature, high voltage, high frequency, and high-density power. With the widespread application of SiC MOSFET in high-power equipment, the market's requirements for the performance of high-power application equipment are gradually increasing. How to further reduce the on-resistance of SiC MOSFET is still urgent and urgent.

Therefore, a low on-resistance SiC MOSFET device and a preparation method are needed that can effectively reduce the total on-resistance and improve the overall performance.

Summary of the invention

One of the purposes of the present invention is to provide a SiC MOSFET device with low on-resistance, which can effectively reduce the total on-resistance and improve the overall performance.

In order to solve the above technical problems, this application provides the following technical solutions:

A low on-resistance SiC MOSFET device, comprising:

Metal drain;

An N+ type substrate located on the metal drain;

An N+ type buffer layer located on an N+ type substrate;

Two N-type drift regions are respectively located on both sides of the N+ type buffer layer;

N-type carrier storage layers respectively located on the two N-type drift regions;

P wells respectively located on two N-type carrier storage layers;

A P+ type doped region and an N+ type doped region respectively located on the two P wells;

A trench located between two N+ doped regions, a P well, an N-type carrier storage layer, and an N-type drift region;

a gate located in the trench;

The gate oxide layer located on the outside and bottom of the gate;

N-type doped regions and P-type doped regions are alternately arranged laterally below the gate;

Another N+ type doped region located on top of the middle N type doped region;

Another P-well located on top of the P-type doped region;

a metal source located in the trench and on top of the trench;

An oxide layer within and on top of the trench that isolates the polysilicon gate from the metal source.

Furthermore, the P-well has a P+ doping region and an N+ doping region, and the P+ doping region is located outside the N+ doping region.

Furthermore, the laterally alternately arranged N-type doping regions and P-type doping regions include three N-type doping regions located at both sides of the trench and in the middle of the trench, and a U-shaped P-type doping region located between the N-type doping regions.

Furthermore, the N-columns and P-columns formed by the alternately arranged N-type doped regions and P-type doped regions constitute a super junction structure.

Furthermore, the gate is a polysilicon gate.

A second object of the present invention is to provide a method for preparing a SiC MOSFET device with low on-resistance, comprising the following steps:

S1. Select an N+ type substrate;

S2, forming an N+ type buffer layer on an N+ type substrate by epitaxial growth;

S3, continuing epitaxial growth on the N+ type buffer layer to form an N type drift region;

S4, etching the top of the N-type drift region to form a trench structure;

S5, etching the N-type drift region below the trench to the surface of the N+ buffer layer, and performing epitaxial growth of the N column to the bottom of the trench;

S6, etching the N column below the trench to the surface of the N+ buffer layer, and performing epitaxial growth of the P column to the bottom of the trench;

S7, etching the P column below the trench, and performing epitaxial growth of the N column to the bottom of the trench;

S8, performing N ion implantation on the surface of the N-type drift region to form an N-type carrier storage layer;

S9, performing Al ion implantation on the surface of the N-type drift region and the surface of the P column at the bottom of the trench to form a P well;

S10, performing Al ion implantation on the surface of the P well above the N-type carrier storage layer to form a P+ type doped region;

S11, performing N ion implantation on the surface of the P well above the N-type carrier storage layer and the surface of the N column in the middle of the bottom of the trench to form an N+ type doping region;

S12, thermally oxidizing and growing _SiO2 in the trench to form a gate oxide layer;

S13, depositing polysilicon on the gate oxide layer in the trench;

S14, etching the polysilicon to the surface of the N+ doped region, and depositing _SiO2 to form an oxide layer from the chip surface to the bottom of the trench;

S15. Deposit Al metal on the top and bottom of the chip to form a gate, source and drain.

Furthermore, the N+ type substrate is a SiC N+ type substrate.

Further, in S4, dry etching is performed on the top of the N-type drift region to form a trench structure;

In S5, the N-type drift region below the trench is dry-etched to the surface of the N+ buffer layer;

In S6, the N column below the trench is dry-etched to the surface of the N+ buffer layer;

In S7, the P column below the trench is dry-etched;

In S14, the polysilicon is dry-etched to the surface of the N+ doped region.

The SiC MOSFET of this solution has two conductive channels, which are located on the surface of the P-type doped region on the sidewall of the trench and the bottom of the trench. In addition, the present invention integrates a superjunction structure below the trench, which is composed of N columns and P columns composed of alternating N-type and P-type doped regions. The surface of the P column of the superjunction structure also forms a second conductive channel.

Based on SiC MOSFET, this solution adds a second conductive channel at the bottom of the trench, further increasing the channel density and thus reducing the on-resistance. At the same time, the integrated superjunction structure significantly reduces the on-resistance of the drift region by increasing the doping concentration of the drift region. Through the combination of dual conductive channels and superjunction structure, the present invention significantly reduces the total on-resistance of SiC MOSFET and improves its overall performance.

In summary, this solution can increase the channel density of SiC MOSFET, reduce the on-resistance of SiC MOSFET, and improve the overall performance of SiC MOSFET.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a low on-resistance SiC MOSFET device;

FIG2 is a schematic diagram of a SiC N+ substrate in a method for preparing a low on-resistance SiC MOSFET device;

FIG3 is a schematic diagram of epitaxial growth to form an N+ type buffer layer in a method for preparing a low on-resistance SiC MOSFET device;

FIG4 is a schematic diagram of epitaxial growth to form an N-type drift region in a method for preparing a low on-resistance SiC MOSFET device;

FIG5 is a schematic diagram of dry etching to form trenches in a method for preparing a low on-resistance SiC MOSFET device;

FIG6 is a schematic diagram of dry etching and epitaxial growth to form an N column in a method for preparing a low on-resistance SiC MOSFET device;

FIG7 is a schematic diagram of dry etching and epitaxial growth to form a P column in a method for preparing a low on-resistance SiC MOSFET device;

FIG8 is a schematic diagram of dry etching and epitaxial growth to form an N column in a method for preparing a low on-resistance SiC MOSFET device;

FIG9 is a schematic diagram of forming an N-type carrier storage layer by N ion implantation in a method for preparing a low on-resistance SiC MOSFET device;

FIG10 is a schematic diagram of forming a P-well by Al ion implantation in a method for preparing a low on-resistance SiC MOSFET device;

FIG11 is a schematic diagram of forming a P+ type doped region by Al ion implantation in a method for preparing a low on-resistance SiC MOSFET device;

FIG12 is a schematic diagram of forming an N+ type doped region by N ion implantation in a method for preparing a low on-resistance SiC MOSFET device;

FIG13 is a schematic diagram of a method for preparing a low on-resistance SiC MOSFET device by thermally oxidizing and growing SiO2 in a trench to form a gate oxide layer;

FIG14 is a schematic diagram of depositing polysilicon in a trench in a method for preparing a low on-resistance SiC MOSFET device;

FIG. 15 is a schematic diagram of dry etching and deposition of an oxide layer in a method for preparing a low on-resistance SiC MOSFET device.

DETAILED DESCRIPTION

The following is further described in detail through specific implementation methods:

Example

A low on-resistance SiC MOSFET device of this embodiment, as shown in FIG1 , includes:

Metal drain (Drain),

N+ substrate located on the metal drain.

N+ buffer layer (N+ Buffer) located on the N+ substrate.

Two N-type drift regions (N-Drift) located on both sides of the N+ type buffer layer.

N-type carrier storage layer (NCSL) located on two N-type drift regions,

P wells (P Well) located on two N-type carrier storage layers (NCSL);

A P+ doped region and an N+ doped region respectively located on two P wells (P Well), wherein the P+ doped region is located outside the device;

The trench is located between two N+ doped regions, the P well, the N-type carrier storage layer, and the N-type drift region.

The polysilicon gate located in the trench;

The gate oxide layer (Gate Oxide) located on the outside and bottom of the polysilicon gate;

The N-type doped region and P-type doped region are arranged alternately in the horizontal direction below the polysilicon gate trench. Specifically, it includes three N-type doped regions located on both sides of the trench and in the middle of the trench, and a U-shaped P-type doped region located between the N-type doped regions. The N-columns and P-columns formed by the alternating N-type and P-type doped regions constitute a super junction structure.

Another N+ type doped region located on top of the middle N type doped region;

Another P well (P Well) located on top of the P-type doped region;

A metal source located in the trench and on top of the trench;

An oxide layer located inside and on top of the trench that isolates the gate from the metal source.

When a positive voltage is applied to the gate and exceeds the threshold voltage, the P-well surface on both sides of the gate oxide layer and the bottom of the trench is inverted to N-type, forming a conductive channel. Electrons flow from the source, through the N+ doped region, and then through the channel into the N-type carrier storage layer, N-type drift region, N+ buffer layer, N+ substrate, and then out of the drain. The direction of the current is opposite to the direction of electron flow, and the current flows from the drain to the source in sequence. When no voltage is applied to the gate or a negative voltage is applied, the conductive channel is closed, electrons cannot flow from the drain to the source, and the device is in a blocking state. A positive voltage is applied to the drain. At this time, the device can withstand a very high forward blocking voltage.

The SiC MOSFET device of the present invention has two conductive channels, respectively on the P-well surface of the groove sidewall and the groove bottom. When the device is turned on, the two conductive channels can provide paths for electron flow, thereby improving the channel density of the device, thereby greatly reducing the on-resistance of the device. The present invention integrates a superjunction structure under the groove, increases the concentration of the drift region, and thus reduces the resistance of the drift region. Through the dual conductive channels and superjunction structure, the on-resistance of the device is greatly reduced, and the comprehensive performance of the SiC MOSFET is improved.

This embodiment also provides a method for preparing a SiC MOSFET device with low on-resistance, comprising the following steps:

S1. Select a SiC N+ substrate, as shown in FIG2.

S2. Form an N+ type buffer layer on the SiC N+ type substrate by epitaxial growth, as shown in FIG3 .

S3. Continue epitaxial growth on the N+ type buffer layer to form an N type drift region, as shown in FIG. 4 .

S4. Perform dry etching on the top of the N-type drift region to form a trench structure, as shown in FIG5 .

S5. Dry-etch the N-type drift region below the trench to the surface of the N+ buffer layer, and perform epitaxial growth of the N column to the bottom of the trench, as shown in FIG6 .

S6, dry-etching the N column below the trench to the surface of the N+ buffer layer, and epitaxially growing the P column to the bottom of the trench, as shown in FIG. 7 .

S7, dry-etching the P column below the trench, and epitaxially growing the N column to the bottom of the trench, as shown in FIG8 .

S8. Perform N ion implantation on the surface of the N-type drift region to form an N-type carrier storage layer, as shown in FIG. 9 .

S9. Perform Al ion implantation on the surface of the N-type drift region and the surface of the P column at the bottom of the trench to form a P well, as shown in FIG. 10 .

S10 , performing Al ion implantation on the surface of the P-well above the N-type carrier storage layer to form a P+ type doped region, as shown in FIG. 11 .

S11. Perform N ion implantation on the surface of the P well above the N-type carrier storage layer and the surface of the N column in the middle of the bottom of the trench to form an N+ type doped region, as shown in FIG. 12 .

S12, thermally oxidizing and growing _SiO2 in the trench to form a gate oxide layer, as shown in FIG13 .

S13, depositing polysilicon on the gate oxide layer in the trench, as shown in FIG14 .

S14, dry-etching the polysilicon to the surface of the N+ doped region, and depositing _SiO2 to form an oxide layer from the chip surface to the bottom of the trench, as shown in FIG15 .

S15. Al metal is deposited on the top and bottom of the chip to form a gate, a source and a drain, as shown in FIG1 .

It is very difficult to match the concentration of the N column and the P column of the super junction structure. The super junction structure requires the same concentration and width of the N column and the P column to achieve the conductivity modulation effect. In this solution, the top of the N column and the P column (below the groove) is used as the channel of the ohmic contact and Pwell, and the concentration is more difficult to control. In this solution, the surface concentration of the N column and the P column is inconsistent with the concentration of the main body below, which can be compatible with the super junction structure and form a conductive channel and ohmic contact. The surface concentration of the N column and the P column and the concentration range of the main body below need to be determined according to the voltage and current level of the designed device. In this embodiment, the range of N+ is 1e19cm-3 to 1e21cm-3; the range of Pwell is 1e16cm-3 to 1e17cm-3; the range of N column and P column is 1e15cm-3 to 1e17cm-3.

In this scheme, the combination of two conductive channels and a superjunction structure can reduce the on-resistance of the device by using two technologies at the same time without increasing the cell pitch of the device, so that the device's specific on-resistance (on-resistance × area) is lower, which is closer to the limit of SiC MOSFET's specific on-resistance.

The above are only embodiments of the present invention. The invention is not limited to the fields involved in this implementation case. The common sense such as the known specific structures and characteristics in the scheme is not described in detail here. The ordinary technicians in the relevant field know all the common technical knowledge in the technical field to which the invention belongs before the application date or the priority date, can obtain all the existing technologies in the field, and have the ability to apply the conventional experimental means before that date. The ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which should also be regarded as the protection scope of the present invention, which will not affect the effect of the implementation of the present invention and the practicality of the patent. The protection scope required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to explain the content of the claims.

Claims (8)

1. A low on-resistance SiC MOSFET device, comprising: Metal drain; An N+ type substrate located on the metal drain; An N+ type buffer layer located on an N+ type substrate; Two N-type drift regions are respectively located on both sides of the N+ type buffer layer; N-type carrier storage layers respectively located on the two N-type drift regions; P wells respectively located on two N-type carrier storage layers; A P+ type doped region and an N+ type doped region respectively located on the two P wells; A trench located between two N+ doped regions, a P well, an N-type carrier storage layer, and an N-type drift region; a gate located in the trench; The gate oxide layer located on the outside and bottom of the gate; N-type doped regions and P-type doped regions are alternately arranged laterally below the gate; Another N+ type doped region located on top of the middle N type doped region; Another P-well located on top of the P-type doped region; a metal source located in the trench and on top of the trench; An oxide layer within and on top of the trench that isolates the polysilicon gate from the metal source. 2. The low on-resistance SiC MOSFET device according to claim 1, characterized in that: the P+ doped region and the N+ doped region on the P well, the P+ doped region is located outside the N+ doped region. 3. The low on-resistance SiC MOSFET device according to claim 2, characterized in that: the N-type doped regions and P-type doped regions alternately arranged laterally include three N-type doped regions respectively located on both sides of the trench and in the middle of the trench, and a U-shaped P-type doped region located between the N-type doped regions. 4. The low on-resistance SiC MOSFET device according to claim 3, characterized in that: the N-columns and P-columns formed by the alternately arranged N-type doped regions and P-type doped regions constitute a super junction structure. 5. The low on-resistance SiC MOSFET device according to claim 4, wherein the gate is a polysilicon gate. 6. A method for preparing a low on-resistance SiC MOSFET device, characterized in that it comprises the following steps: S1. Select an N+ type substrate; S2, forming an N+ type buffer layer on an N+ type substrate by epitaxial growth; S3, continuing epitaxial growth on the N+ type buffer layer to form an N type drift region; S4, etching the top of the N-type drift region to form a trench structure; S5, etching the N-type drift region below the trench to the surface of the N+ buffer layer, and performing epitaxial growth of the N column to the bottom of the trench; S6, etching the N column below the trench to the surface of the N+ buffer layer, and performing epitaxial growth of the P column to the bottom of the trench; S7, etching the P column below the trench, and performing epitaxial growth of the N column to the bottom of the trench; S8, performing N ion implantation on the surface of the N-type drift region to form an N-type carrier storage layer; S9, performing Al ion implantation on the surface of the N-type drift region and the surface of the P column at the bottom of the trench to form a P well; S10, performing Al ion implantation on the surface of the P well above the N-type carrier storage layer to form a P+ type doped region; S11, performing N ion implantation on the surface of the P well above the N-type carrier storage layer and the surface of the N column in the middle of the bottom of the trench to form an N+ type doping region; S12, thermally oxidizing and growing _SiO2 in the trench to form a gate oxide layer; S13, depositing polysilicon on the gate oxide layer in the trench; S14, etching the polysilicon to the surface of the N+ doped region, and depositing _SiO2 to form an oxide layer from the chip surface to the bottom of the trench; S15. Deposit Al metal on the top and bottom of the chip to form a gate, source and drain. 7. The method for preparing a low on-resistance SiC MOSFET device according to claim 6, wherein the N+ type substrate is a SiC N+ type substrate. 8. The method for preparing a SiC MOSFET device with low on-resistance according to claim 7, characterized in that: in S4, dry etching is performed on the top of the N-type drift region to form a trench structure; In S5, the N-type drift region below the trench is dry-etched to the surface of the N+ buffer layer; In S6, the N column below the trench is dry-etched to the surface of the N+ buffer layer; In S7, the P column below the trench is dry-etched; In S14, the polysilicon is dry-etched to the surface of the N+ doped region.